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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2063 occurrences of 1034 keywords
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Results
Found 3191 publication records. Showing 3191 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
68 | Valentin Muresan, Xiaojun Wang 0001, Valentina Muresan, Mircea Vladutiu |
Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods |
54 | Bapiraju Vinnakota |
Monitoring power dissipation for fault detection. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
power monitoring, CMOS IC testing, VLSI, monitoring, integrated circuit testing, fault detection, fault location, CMOS integrated circuits, power dissipation, frequency-domain analysis, frequency domain analysis, test vectors |
49 | Joong-ho Park, Bang-Hyun Sung, Seok-Yoon Kim |
An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Razak Hossain, Menghui Zheng, Alexander Albicki |
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
49 | Satish L. Rege |
Performance and power dissipation analysis for CCD memory systems. |
AFIPS National Computer Conference |
1976 |
DBLP DOI BibTeX RDF |
|
48 | Roman Ostroumov, Kang L. Wang |
On Power Dissipation in Information Processing. |
ITNG |
2008 |
DBLP DOI BibTeX RDF |
nanoscale architectures, CMOS, power dissipation |
48 | Peter Diener, Ernst Nils Dorband, Erik Schnetter, Manuel Tiglio |
Optimized High-Order Derivative and Dissipation Operators Satisfying Summation by Parts, and Applications in Three-dimensional Multi-block Evolutions. |
J. Sci. Comput. |
2007 |
DBLP DOI BibTeX RDF |
High order finite differencing, multi-block evolutions, artificial dissipation, accuracy, numerical stability |
48 | Björn Sjögreen, H. C. Yee 0001 |
Multiresolution Wavelet Based Adaptive Numerical Dissipation Control for High Order Methods. |
J. Sci. Comput. |
2004 |
DBLP DOI BibTeX RDF |
low dissipation, high order finite difference method, TVD schemes, wavelets, multi resolution, shock waves |
48 | Xiaowei Li 0001, Huawei Li 0001, Yinghua Min |
Reducing Power Dissipation during At-Speed Test Application. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
Test-pair Ordering, Power Dissipation, At-speed Test |
48 | Bapiraju Vinnakota |
Monitoring Power Dissipation for Fault Detection. |
J. Electron. Test. |
1997 |
DBLP DOI BibTeX RDF |
I DDt test, power dissipation test, spectral analysis, I DDQ test |
48 | Zhanping Chen, Kaushik Roy 0001, Tan-Li Chou |
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
Monte Carlo based approach, maximum bounds, minimum bounds, power dissipation estimation, power sensitivity, primary inputs, signal properties, signal switching, uncertain specifications, logic CAD, CMOS logic circuits, power estimation, CMOS circuits, signal probability, statistical technique |
45 | Thomas D. Burd, Robert W. Brodersen |
Energy efficient CMOS microprocessor design. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
energy efficient CMOS microprocessor design, portable electronics, battery weight, battery size, heat dissipation, computation modes, power analysis methodology, energy efficiency quantification, computer architecture, computer architectures, throughput, parallel machines, energy consumption, energy conservation, microprocessor chips, design principles, power dissipation, CMOS digital integrated circuits, integrated circuit modelling, cooling, figures of merit, desktop computers |
43 | Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest |
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC) |
43 | Irith Pomeranz, Sudhakar M. Reddy |
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Francisco-Javier Veredas, Jordi Carrabina |
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Krishnan Sundaresan, Nihar R. Mahapatra |
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. |
HPCA |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu |
A Method to Reduce Power Dissipation during Test for Sequential Circuits. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
43 | D. Sármány, Mike A. Botchev, Jaap J. W. van der Vegt |
Dispersion and Dissipation Error in High-Order Runge-Kutta Discontinuous Galerkin Discretisations of the Maxwell Equations. |
J. Sci. Comput. |
2007 |
DBLP DOI BibTeX RDF |
High-order nodal discontinuous Galerkin methods, Numerical dispersion and dissipation, Strong-stability-preserving Runge-Kutta methods, Maxwell equations |
43 | Bernardo Cockburn, Bo Dong |
An Analysis of the Minimal Dissipation Local Discontinuous Galerkin Method for Convection-Diffusion Problems. |
J. Sci. Comput. |
2007 |
DBLP DOI BibTeX RDF |
Minimal dissipation local discontinuous Galerkin method, convection-diffusion equation |
43 | Jan Nordström |
Conservative Finite Difference Formulations, Variable Coefficients, Energy Estimates and Artificial Dissipation. |
J. Sci. Comput. |
2006 |
DBLP DOI BibTeX RDF |
Artificial dissipation, variable coefficients, stability, finite differences, energy estimate |
43 | Ken Mattsson, Magnus Svärd, Jan Nordström |
Stable and Accurate Artificial Dissipation. |
J. Sci. Comput. |
2004 |
DBLP DOI BibTeX RDF |
high order finite difference methods, artificial dissipation, numerical stability |
43 | Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura |
Routing methodology for minimizing 1nterconnect energy dissipation. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
routing, SoC, analysis, crosstalk, energy dissipation |
43 | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu |
Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
Test generation, Fault simulation, Power dissipation, CMOS circuit |
43 | Payam Heydari, Massoud Pedram |
Interconnect Energy Dissipation in High-Speed ULSI Circuits. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Ultra-large integrated (ULSI) circuits, Energy dissipation CMOS circuits, RLC circuits, Interconnect, Transmission lines |
41 | Man Lung Mui, Kaustav Banerjee, Amit Mehrotra |
Supply and power optimization in leakage-dominant technologies. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Debasis Samanta, Ajit Pal |
Synthesis of Dual-VT Dynamic CMOS Circuits. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT |
40 | Kei-Yong Khoo, Alan N. Willson Jr. |
Single-transistor transparent-latch clocking. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits |
40 | Saed G. Younis, Thomas F. Knight Jr. |
Non-dissipative rail drivers for adiabatic circuits. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics |
38 | Giorgio Casinovi |
Effect of the switching order on power dissipation inswitched-capacitor circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Jörg Henkel |
A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
38 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Extensions to Programmable DSP architectures for Reduced Power Dissipation. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Low Power Design, DSP Architecture |
38 | Yanbing Li, Jörg Henkel |
A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
38 | Brian S. Cherkauer, Eby G. Friedman |
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. |
IEEE Trans. Very Large Scale Integr. Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
37 | ByungMoon Kim, Yingjie Liu, Ignacio Llamas, Jarek Rossignac |
Advections with Significantly Reduced Dissipation and Diffusion. |
IEEE Trans. Vis. Comput. Graph. |
2007 |
DBLP DOI BibTeX RDF |
dissipation, diffusion, smoke, fluid, Advection |
35 | H. C. Yee 0001, Björn Sjögreen |
Non-Linear Filtering and Limiting in High Order Methods for Ideal and Non-Ideal MHD. |
J. Sci. Comput. |
2006 |
DBLP DOI BibTeX RDF |
High order schemes filtering, MHD, shock-capturing, shock/turbulence interactions, nonlinear filtering, limiting |
34 | Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra |
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
address bus, low power, encoding, energy dissipation |
34 | Valentin Muresan, Xiaojun Wang 0001, Valentina Muresan, Mircea Vladutiu |
Power-Constrained Block-Test List Scheduling. |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
Block-Test Scheduling, Tree-Growing Technique, Power Dissipation, List Scheduling |
34 | Hirendu Vaishnav, Massoud Pedram |
Delay optimal partitioning targeting low power VLSI circuits. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
clustering, VLSI, partitioning, logic CAD, circuit CAD, integrated logic circuits, power dissipation, VLSI circuits, logic partitioning, delay optimal |
34 | José Monteiro 0001, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh |
Optimization of combinational and sequential logic circuits for low power using precomputation. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle |
34 | Mircea R. Stan, Wayne P. Burleson |
Coding a terminated bus for low power. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses |
32 | Nauman Aslam, William J. Phillips, William Robertson 0001, Shyamala C. Sivakumar |
Balancing Energy Dissipation in Clustered Wireless Sensor Networks. |
ISPA Workshops |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Mitsunaga Kinjo, Shigeo Sato, Koji Nakajima |
Energy Dissipation Effect on a Quantum Neural Network. |
ICONIP (2) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Amir Averbuch, Boris Epstein 0002, Neta Rabin, Eli Turkel |
Edge-enhancement postprocessing using artificial dissipation. |
IEEE Trans. Image Process. |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki Mukherjee, Hao Li |
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh |
Effect of traffic localization on energy dissipation in NoC-based interconnect. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Yu Hu 0001, Xiaowei Li 0001, Huawei Li 0001, Xiaoqing Wen |
Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. |
PRDC |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba |
Static Compaction Techniques to Control Scan Vector Power Dissipation. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing |
32 | Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou |
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. |
DFT |
1999 |
DBLP DOI BibTeX RDF |
Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing |
32 | Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro 0001, João Marques-Silva 0001 |
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Uming Ko, Poras T. Balsara |
Short-circuit power driven gate sizing technique for reducing power dissipation. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
32 | Srinivas Devadas, Kurt Keutzer, Jacob K. White 0001 |
Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
32 | Paul M. Chau, Scott R. Powell |
Power dissipation of VLSI array processing systems. |
J. VLSI Signal Process. |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Seongmoon Wang, Wenlong Wei |
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs |
31 | Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001 |
On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
dynamic and partial FPGA reconfiguration, on-line adaptation, power dissipation |
31 | Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz |
On test generation for transition faults with minimized peak power dissipation. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
test generation, power dissipation, transition faults |
29 | Hanif Fatemi, Shahin Nazarian, Massoud Pedram |
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Houman Homayoun, Ted H. Szymanski |
Reducing the Instruction Queue Leakage Power in Superscalar Processors. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Raid Ayoub, Alex Orailoglu |
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Krishnan Sundaresan, Nihar R. Mahapatra |
An Accurate Energy and Thermal Model for Global Signal Buses. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Man Lung Mui, Kaustav Banerjee, Amit Mehrotra |
Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici |
Scan Architecture for Shift and Capture Cycle Power Reduction. |
DFT |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Tohru Ishihara, Kunihiro Asada |
A system level memory power optimization technique using multiple supply and threshold voltages. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Vishal Dalal, C. P. Ravikumar |
Software Power Optimizations In An Embedded System. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Rajamohana Hegde, Naresh R. Shanbhag |
Toward achieving energy efficiency in presence of deep submicron noise. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
Scan-Based Tests with Low Switching Activity. |
IEEE Des. Test Comput. |
2007 |
DBLP DOI BibTeX RDF |
scan shift, test response capture, supply current, power dissipation, switching activity, scan-based test |
28 | K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti 0001, Vivekananda M. Vedula |
Power Virus Generation Using Behavioral Models of Circuits. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models |
28 | Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti |
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation |
28 | Pawan Kapur, Gaurav Chandra, Krishna Saraswat |
Power estimation in global interconnects and its reduction using a novel repeater optimization methodology. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
repeaters, power dissipation, global interconnects |
28 | John F. Kolen, Tim Hutcheson |
A Low-Cost, High-Density Mounting System for Computer Clusters. |
CLUSTER |
2001 |
DBLP DOI BibTeX RDF |
mounting system, heat dissipation, power distribution |
28 | Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet |
A symbolic simulation approach in resolving signals' correlation. |
Annual Simulation Symposium |
1996 |
DBLP DOI BibTeX RDF |
signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools |
28 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Design tradeoffs in high speed multipliers and FIR filters. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed |
28 | Joep L. W. Kessels |
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes |
28 | William C. Athas, Nestoras Tzartzanis |
Energy recovery for low-power CMOS. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI |
28 | Javier Fernández-Fidalgo, Luis Ramírez, Panagiotis Tsoutsanis, Ignasi Colominas, Xesús Nogueira |
A reduced-dissipation WENO scheme with automatic dissipation adjustment. |
J. Comput. Phys. |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Yue Li, Lin Fu, Nikolaus A. Adams |
A low-dissipation shock-capturing framework with flexible nonlinear dissipation control. |
J. Comput. Phys. |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Yue Li, Lin Fu, Nikolaus A. Adams |
A low-dissipation shock-capturing framework with flexible nonlinear dissipation control. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
28 | Shuliang Liu |
Experimental study of debris flow velocity and energy dissipation in soft-based energy dissipation drainage canal. |
IEEA |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Yapeng Zhang, Xu Hu, Xi Feng, Yi Hu, Xiaoke Tang |
An Analysis of Power Dissipation Analysis and Power Dissipation optimization Methods in Digital Chip Layout Design. |
ICCT |
2019 |
DBLP DOI BibTeX RDF |
|
28 | E. M. J. Komen, L. H. Camilo, Afaque Shams, Bernard J. Geurts, Barry Koren |
A quantification method for numerical dissipation in quasi-DNS and under-resolved DNS, and effects of numerical dissipation in quasi-DNS and under-resolved DNS of turbulent channel flows. |
J. Comput. Phys. |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Marc-Antoine Brossault |
Suivi temporel de la dynamique des structures : apports du théorème fluctuation-dissipation et de la dynamique lente pour l'évaluation de l'intégrité des structures de génie civil. (Temporal monitoring of the dynamics of structures : contributions of the fluctuation-dissipation theorem and of the slow dynamics to assess the state of health of engineering structures). |
|
2017 |
RDF |
|
28 | Hacène Meglouli |
La phytoremédiation assistée par les champignons mycorhiziens à arbuscules des sols historiquement contaminés par les dioxines/furanes : Conséquences sur le microbiote du sol et sur la dissipation des polluants. (Arbuscular mycorrhizal fungi - assisted phytoremediation of aged dioxin/furan-contaminated soil : Consequences on microbiota and pollutant dissipation). |
|
2017 |
RDF |
|
28 | Hongling Su, Shengtai Li |
Energy/dissipation-preserving Birkhoffian multi-symplectic methods for Maxwell's equations with dissipation terms. |
J. Comput. Phys. |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Eric Bonnetier, Lukás Jakabcin, Stéphane Labbé, Anne Replumaz |
Numerical simulation of a class of models that combine several mechanisms of dissipation: Fracture, plasticity, viscous dissipation. |
J. Comput. Phys. |
2014 |
DBLP DOI BibTeX RDF |
|
28 | Lukás Jakabcin |
Modélisation, analyse et simulation numérique de solides combinant plasticité, rupture et dissipation visqueuse. (Modeling, analysis and numerical simulation of solids combining plasticity, fracture and viscous dissipation). |
|
2014 |
RDF |
|
28 | Francisco Rus, Francisco R. Villatoro |
Adiabatic perturbations for compactons under dissipation and numerically-induced dissipation. |
J. Comput. Phys. |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Michel Franken, Stefano Stramigioli |
Internal dissipation in passive sampled haptic feedback systems. |
IROS |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Xiaojun Ma, Jing Huang 0001, Fabrizio Lombardi |
A model for computing and energy dissipation of molecular QCA devices and circuits. |
ACM J. Emerg. Technol. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
thermodynamic analysis, emerging technology, reversible computing, QCA |
26 | Eduardo Mojica-Nava, Nicanor Quijano, Alain Gauthier, Naly Rakoto-Ravalontsalama |
Stability analysis of switched polynomial systems using dissipation inequalities. |
CDC |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Fumihiko Asano, Zhi Wei Luo |
The Effect of Semicircular Feet on Energy Dissipation by Heel-strike in Dynamic Biped Locomotion. |
ICRA |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Noureddine Chabini |
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Malav Shah, Dipankar Nagchoudhuri |
BIST Scheme for Low Heat Dissipation and Reduced Test Application Time. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Ireneusz Brzozowski, Andrzej Kos |
Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De |
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Il-soo Lee, Yong Min Hur, Tony Ambler |
The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Chandra Krintz, Ye Wen, Richard Wolski |
Application-level prediction of battery dissipation. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
application-level prediction, battery life estimation, resource-restricted devices |
26 | Giorgio Casinovi, Chad Young |
Estimation of power dissipation in switched-capacitor circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
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26 | Eugeni Isern 0001, Miquel Roca 0001, Francesc Moll |
Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Shrutin Ulman |
Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi |
Power Dissipation Reductions with Genetic Algorithms. |
Evolvable Hardware |
2003 |
DBLP DOI BibTeX RDF |
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