|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 380 occurrences of 267 keywords
|
|
|
Results
Found 824 publication records. Showing 813 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
114 | Gin Yee, Carl Sechen |
Clock-Delayed Domino for Adder and Combinational Logic Desig. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 332-337, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
110 | Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita |
Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 92-98, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Clock-delayed domino circuit, Fault simulation, crosstalk fault |
107 | David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah |
Timing verification of sequential domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 127-132, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
domino gates, sequential domino circuits, static timing verification, logic testing, input signals |
103 | Jovanka Ciric, Gin Yee, Carl Sechen |
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 277-282, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
103 | Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang |
Charge sharing fault analysis and testing for CMOS domino logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 435-440, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors |
100 | Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone |
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 77-85, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit |
92 | Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim |
Charge-Sharing-Problem Reduced Split-Path Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 201-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
92 | Min Zhao 0001, Sachin S. Sapatnekar |
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1322-1336, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
92 | Maik Bollmann, Rainer Hoischen, Michael Jesikiewicz, Christoph Justkowski, Bärbel Mertsching |
Playing Domino: A Case Study for an Active Vision System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICVS ![In: Computer Vision Systems, First International Conference, ICVS '99, Las Palmas, Gran Canaria, Spain, January 13-15, 1999, Proceedings, pp. 392-411, 1999, Springer, 3-540-65459-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
92 | Hans L. Bodlaender, Joost Engelfriet |
Domino Treewith (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
WG ![In: Graph-Theoretic Concepts in Computer Science, 20th International Workshop, WG '94, Herrsching, Germany, June 16-18, 1994, Proceedings, pp. 1-13, 1994, Springer, 3-540-59071-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
89 | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh |
Low-power dual Vth pseudo dual Vdd domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 273-277, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages |
89 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Optimal Timing for Skew-Tolerant High-Speed Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 41-46, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
keeper, optimal timing, noise, skew, domino logic, dynamic circuit |
87 | Rouwaida Kanj, Elyse Rosenbaum |
Critical evaluation of SOI design guidelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(9), pp. 885-894, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
82 | Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer |
False-Noise Analysis for Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 784-789, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
82 | Gin Yee, Carl Sechen |
Clock-delayed domino for dynamic circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 425-430, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
82 | Erich Grädel |
Domino Games with an Application to the Complexity of Boolean Algebras with Bounded Quantifier Alternations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 88, 5th Annual Symposium on Theoretical Aspects of Computer Science, Bordeaux, France, February 11-13, 1988, Proceedings, pp. 98-107, 1988, Springer, 3-540-18834-7. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
78 | Aiqun Cao, Ruibing Lu, Chen Li 0004, Cheng-Kok Koh |
Postlayout optimization for synthesis of Domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(4), pp. 797-821, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
optimization, synthesis, Domino logic |
78 | Andrea Frosini, Giulia Simi |
The Reconstruction of a Bicolored Domino Tiling from Two Projections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DGCI ![In: Discrete Geometry for Computer Imagery, 10th International Conference, DGCI 2002, Bordeaux, France, April 3-5, 2002, Proceedings, pp. 136-144, 2002, Springer, 3-540-43380-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Domino tiling, Reconstruction Problem, NP-completeness |
76 | Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry |
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(2), pp. 71-78, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
71 | Peiyi Zhao, Jason McNeely, Magdy A. Bayoumi, Pradeep Kumar Golconda, Weidong Kuang |
A Low Power Domino with Differential-Controlled-Keeper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1625-1628, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
71 | Wei Ling, Yvon Savaria |
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 688-693, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
71 | Kwang-Il Oh, Lee-Sup Kim |
A clock delayed sleep mode domino logic for wide dynamic OR gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 176-179, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clock delay, low power, leakage, sleep mode, dynamic circuits |
71 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 260-265, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
71 | Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita |
Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 176-181, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
71 | Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang |
Charge-sharing alleviation and detection for CMOS domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2), pp. 266-280, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
71 | Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang |
Skew-tolerant high-speed (STHS) domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 154-157, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
67 | Zhiyu Liu, Volkan Kursun |
Leakage current starved domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 428-433, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage |
67 | Zhiyu Liu, Volkan Kursun |
Leakage Biased Sleep Switch Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 318-323, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage |
67 | Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell |
Electrical Behavior of GOS Fault affected Domino Logic Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 183-189, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Gate-Oxide Short (GOS), Electrical analysis Boolean test, Domino logic, Defect modeling |
67 | Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi |
A high speed and leakage-tolerant domino logic for high fan-in gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 478-481, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high speed, noise immunity, deep submicron, fan-in, domino |
67 | Aiqun Cao, Cheng-Kok Koh |
Post-layout logic optimization of domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 820-825, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, synthesis, layout, domino logic |
67 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 467-472, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage |
67 | Eric W. MacDonald, Nur A. Touba |
Testing domino circuits in SOI technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 441-446, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits |
67 | Alvernon Walker, Algernon P. Henry, Parag K. Lala |
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 272-280, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current |
65 | Debasis Samanta, Nishant Sinha 0001, Ajit Pal |
Synthesis of High Performance Low Power Dynamic CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 99-104, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
64 | Malgorzata Domino, Krzysztof Domino, Zdzislaw Gajewski |
An application of higher order multivariate cumulants in modelling of myoelectrical activity of porcine uterus during early pregnancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biosyst. ![In: Biosyst. 175, pp. 30-38, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
61 | Alvaro A. Cárdenas, Svetlana Radosavac, John S. Baras |
Evaluation of detection algorithms for MAC layer misbehavior: theory and experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 17(2), pp. 605-617, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CUSUM, SPRT, intrusion detection, DOMINO, misbehavior, IEEE 802.11 MAC |
60 | Hadrien Cambazard, John Horan, Eoin O'Mahony, Barry O'Sullivan |
Fast and Scalable Domino Portrait Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPAIOR ![In: Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 5th International Conference, CPAIOR 2008, Paris, France, May 20-23, 2008, Proceedings, pp. 51-65, 2008, Springer, 978-3-540-68154-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 136-145, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Dhiren M. Parmar, Monalisa Sarma, Debasis Samanta |
A Novel Approach to Domino Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 401-406, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001 |
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 415-420, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Ge Yang 0004, Zhongda Wang, Sung-Mo Kang |
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 222-227, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Volkan Kursun, Eby G. Friedman |
Domino logic with variable threshold voltage keeper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1080-1093, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Timing constraints for domino logic gates with timing-dependent keepers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1), pp. 96-103, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Rahul Kundu, R. D. (Shawn) Blanton |
ATPG for Noise-Induced Switch Failures in Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 765-769, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Roy Mader, Ivan S. Kourtev |
Reduced dynamic swing domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 33-36, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Noise constrained transistor sizing and power optimization for dual Vst domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(5), pp. 532-541, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
60 | Sungwook Kim, Gerald E. Sobelman |
Efficient digit-serial FIR filters with skew-tolerant domino. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 369-372, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
60 | Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith |
Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 257-260, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
60 | Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul |
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 211-214, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
60 | Jonathan T.-Y. Chang, Edward J. McCluskey |
Detecting resistive shorts for CMOS domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 890-899, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
60 | Niraj K. Jha |
Testing for multiple faults in domino-CMOS logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 109-116, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
56 | Jinhui Wang, Lei Zuo, Na Gong, Daming Gao, Shuqin Geng, Wang Zhang, Ligang Hou, Xiaohong Peng, Wuchen Wu |
Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 844-851, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Dual threshold domino OR, Leakage power, Speed, Wavelet Neural Networks |
56 | Bo Fu, Qiaoyan Yu, Paul Ampadu |
Energy-delay minimization in nanoscale domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 316-319, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay, energy, leakage, low voltage, domino |
56 | Zhiyu Liu, Volkan Kursun |
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 31-36, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage |
56 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang |
Minimum delay optimization for domino circuits - a coupling-aware approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(2), pp. 202-213, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Logic synthesis, coupling, domino logic, delay minimization |
56 | Jung-Lin Yang, Erik Brunvand |
Using dynamic domino circuits in self-timed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 253-256, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
asynchronous circuits, domino logic, self-timed circuits |
56 | Ayoob E. Dooply, Kenneth Y. Yun |
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 200-214, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault |
56 | Ron Lin |
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 520-522, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
shift switching, asynchronous VLSI comparator, precharged CMOS domino logic, VLSI, semaphore |
54 | Min Zhao 0001, Sachin S. Sapatnekar |
Timing-driven partitioning for two-phase domino and mixed static/domino implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 107-110, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
54 | Volkan Kursun, Eby G. Friedman |
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 104-109, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry |
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 155-160, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
49 | Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng |
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 594-598, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Yi Liang, Lei Wang 0004, Jianfeng Zhan, Ruihua Di |
A Performance Model for Domino Mail Server. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (3) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 3: Grid Computing / Distributed and Parallel Computing / Information Security, December 12-14, 2008, Wuhan, China, pp. 473-476, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
49 | Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou |
Testable Designs of Multiple Precharged Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 461-465, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Zhiyu Liu, Volkan Kursun |
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1311-1319, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Yi-Yu Liu, TingTing Hwang |
Crosstalk-Aware Domino-Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 1155-1161, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Yi-Yu Liu, TingTing Hwang |
Crosstalk-aware domino logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1312-1317, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Chris Worman, Boting Yang |
On the Computation of Colored Domino Tilings of Simple and Non-simple Orthogonal Polygons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAAC ![In: Algorithms and Computation, 16th International Symposium, ISAAC 2005, Sanya, Hainan, China, December 19-21, 2005, Proceedings, pp. 859-868, 2005, Springer, 3-540-30935-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | William J. Cook, Daniel G. Espinoza, Marcos Goycoolea |
A Study of Domino-Parity and k-Parity Constraints for the TSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCO ![In: Integer Programming and Combinatorial Optimization, 11th International IPCO Conference, Berlin, Germany, June 8-10, 2005, Proceedings, pp. 452-467, 2005, Springer, 3-540-26199-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
Low-power domino circuits using NMOS pull-up on off-critical paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 533-538, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Amir Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani |
Domino logic with an efficient variable threshold voltage keeper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1674-1677, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Yonghee Im, Kaushik Roy 0001 |
LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 45-54, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | P. C. Chen, James B. Kuo |
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 441-444, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Yonghee Im, Kaushik Roy 0001 |
A logic-aware layout methodology to enhance the noise immunity of domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 637-640, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Rahul Kundu, R. D. (Shawn) Blanton |
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 122-130, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm |
A technique for Improving dual-output domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 508-511, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain |
A System-Level Solution to Domino Synthesis with 2 GHz Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 164-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Volkan Kursun, Eby G. Friedman |
Low swing dual threshold voltage domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 47-52, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou |
On Testability of Multiple Precharged Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 299-304, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
49 | Tan-Li Chou, Kaushik Roy 0001 |
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10), pp. 1257-1265, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
49 | Niraj K. Jha |
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3), pp. 332-336, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
49 | Alan M. Sykes |
A second generation DOMINO for statisticians. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the international conference on APL: APL in transition, APL 1987, Dallas, TX, USA, May 10-14, 1987., pp. 369-380, 1987, ACM, 0-89791-226-8. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
APL |
45 | Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya |
An Efficient Parallel Prefix Sums Architecture with Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(9), pp. 922-931, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
shift switching, binary prefix sums, binary counting, VLSI design, scalable architectures, domino logic, Hardware-algorithms |
45 | Min Zhao 0001, Sachin S. Sapatnekar |
Technology mapping algorithms for domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(2), pp. 306-335, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
XOR/XNOR logic, dual-monotonic gates, parameterized library, phase assignment, synthesis, technology mapping, Domino logic |
45 | C. Mohan 0001 |
A Database Perspective on Lotus Domino/Notes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: SIGMOD 1999, Proceedings ACM SIGMOD International Conference on Management of Data, June 1-3, 1999, Philadelphia, Pennsylvania, USA., pp. 507, 1999, ACM Press, 1-58113-084-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Lotus Domino, heterogeneous data access, groupware, replication, recovery, logging, semi-structured data, Lotus Notes, ARIES, Notes |
45 | Rong Lin, Koji Nakano, Stephan Olariu, Albert Y. Zomaya |
An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS/SPDP ![In: 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 12-16 April 1999, San Juan, Puerto Rico, Proceedings, pp. 273-277, 1999, IEEE Computer Society, 0-7695-0143-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Special-purpose parallel architectures, digital signal processing, computer arithmetic, VLSI design, domino logic |
43 | Volkan Kursun, Zhiyu Liu |
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | T. J. Thorp, G. S. Yee, Carl M. Sechen |
Design and synthesis of dynamic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 141-149, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001 |
Synthesis of Selectively Clocked Skewed Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 229-234, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Alexandre Solomatnikov, Kaushik Roy 0001, Cheng-Kok Koh, Dinesh Somasekhar |
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 241-246, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin |
A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 182-, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | Norman D. Thomson |
Applying Matrix Divide in APL and J. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the International Conference on APL 1994: The Language and Its Applications, Antwerp, Belgium, September 11-15, 1994., pp. 211-219, 1994, ACM, 0-89791-675-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
APL, J |
40 | Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi |
Noise-tolerant high fan-in dynamic CMOS circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 134-137, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits |
40 | Fatih Hamzaoglu, Mircea R. Stan |
Circuit-level techniques to control gate leakage for sub-100nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 60-63, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low power, MTCMOS, gate leakage, domino circuits |
40 | Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser |
Logic optimization by output phase assignment in dynamic logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 2-7, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
dynamic logic synthesis, logic duplication, minimum logic duplication penalty, output phase assignment, logic design, heuristic algorithms, optimal algorithms, domino logic, logic optimization, area overhead, logic functions, inverters |
38 | Maxim Raya, Imad Aad, Jean-Pierre Hubaux, Alaeddine El Fawal |
DOMINO: Detecting MAC Layer Greedy Behavior in IEEE 802.11 Hotspots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 5(12), pp. 1691-1705, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
greedy behavior, IEEE 802.11, medium access control, network monitoring, wireless local-area networks, Public networks |
38 | Amir Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha |
Low power and high performance clock delayed domino logic using saturated keeper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Ivan E. Sutherland |
GasP Control for Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 12-22, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Aiqun Cao, Ruibing Lu, Cheng-Kok Koh |
Post-layout logic duplication for synthesis of domino circuits with complex gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 260-265, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 813 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ >>] |
|