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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 64 occurrences of 43 keywords
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Results
Found 92 publication records. Showing 92 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
76 | Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong |
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 42-50, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, low power, power efficient, dual-Vdd, dual-Vt |
49 | Qi Wang, Sarma B. K. Vrudhula |
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 556-562, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low power, CMOS circuits, dual Vt |
35 | Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 |
Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(6), pp. 660-671, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Akhilesh Kumar, Mohab Anis |
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 735-740, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 |
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 14-19, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process variation, yield, leakage, dual-Vt, metal gate |
26 | Jungseob Lee, Azadeh Davoodi |
Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3018-3021, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Akhilesh Kumar, Mohab Anis |
Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1), pp. 53-66, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Debasis Samanta, Ajit Pal |
Synthesis of Dual-VT Dynamic CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 303-308, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT |
24 | Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar |
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 486-491, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Dual-Vt design, multiple threshold, optimization, sizing |
21 | Jaehyun Kim, Youngsoo Shin |
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 797-802, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 995-1000, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy 0001 |
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 125-130, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud |
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 105-110, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, low power circuit design, subthreshold leakage, dual threshold voltage |
18 | Debasis Samanta, Ajit Pal |
Synthesis of Low Power High Performance Dual-VT PTL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 85-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang 0001, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De |
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(2), pp. 91-95, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Debasis Samanta, Ajit Pal |
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 193-198, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Muhammad E. S. Elrabaa, Mohamed I. Elmasry |
Split-Gate Logic circuits for multi-threshold technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 798-801, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Navid Azizi, Andreas Moshovos, Farid N. Najm |
Low-leakage asymmetric-cell SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 48-51, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low-leakage, low-power, SRAM, dual-Vt |
14 | Jungseob Lee, Lin Xie, Azadeh Davoodi |
A Dual-Vt low leakage SRAM array robust to process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 580-583, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang |
Energy-efficient skewed static logic with dual Vt: design and synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 64-70, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng |
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 594-598, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
13 | Vivek De |
Leakage-tolerant design techniques for high performance processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 28-28, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Volkan Kursun, Eby G. Friedman |
Low swing dual threshold voltage domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 47-52, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 851-860, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Dongwoo Lee, David T. Blaauw, Dennis Sylvester |
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 399-404, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Sandeep Gupta, Jaya Singh, Abhijit Roy |
A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 526-530, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power |
10 | Steven Hsu, Amit Agarwal 0001, Kaushik Roy 0001, Ram Krishnamurthy 0001, Shekhar Borkar |
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 103-106, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-Vt/Vcc, flip-flop, hot spot, level converter |
10 | Feng Gao 0017, John P. Hayes |
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 31-36, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, linear programming, gate sizing, dual Vt |
10 | Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 149-154, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ARM processor, Low power design, CVS, Dual-Vt |
10 | Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw |
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 436-441, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low-power-design, leakage, dual-Vt |
9 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan |
Achieving continuous VT performance in a dual VT process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 393-398, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw |
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(2), pp. 79-90, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Qi Wang, Sarma B. K. Vrudhula |
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3), pp. 306-318, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang |
Energy-efficient skewed static logic design with dual Vt. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 882-885, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
8 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 273-274, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
8 | Lin Yuan, Gang Qu 0001 |
Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 548-551, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Somsubhra Mondal, Seda Ogrenci Memik |
Power Optimization Techniques for SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-2, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester |
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 494-499, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Ge Yang 0004, Zhongda Wang, Sung-Mo Kang |
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 222-227, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Statistical optimization of leakage power considering process variations using dual-Vth and sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 773-778, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, variability, leakage |
8 | Li Yang, J. S. Yuan |
Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 278-279, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang |
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 59-64, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
8 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 561-564, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
5 | Alireza Shafaei, Massoud Pedram |
Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 457-462, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
5 | Hong Zhu 0009, Volkan Kursun |
2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2932-2935, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
5 | Na Gong, Jinhui Wang, Ramalingam Sridhar |
Variation Aware Sleep Vector Selection in Dual Vt Dynamic OR Circuits for Low Leakage Register File Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7), pp. 1970-1983, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
5 | S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjƶland, Peter Nilsson 0001 |
Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(4-5), pp. 494-504, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
5 | Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues |
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference, Bucharest, Romania, September 16-20, 2013, pp. 197-200, 2013, IEEE, 978-1-4799-0643-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
5 | Wei Ting Loke, Yajun Ha, Wenfeng Zhao |
A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, pp. 221-226, 2012, IEEE Computer Society, 978-1-4673-0974-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
5 | Wei Ting Loke, Yajun Ha |
A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings, pp. 174-186, 2012, Springer, 978-3-642-28364-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
5 | Jinhui Wang, Na Gong, Ligang Hou, Xiaohong Peng, Ramalingam Sridhar, Wuchen Wu |
Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 51(9-11), pp. 1498-1502, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
5 | Junjun Gu, Gang Qu 0001, Lin Yuan, Cheng Zhuo |
Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, California, USA, November 7-10, 2011, pp. 732-735, 2011, IEEE Computer Society, 978-1-4577-1399-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
5 | Na Gong, Jinhui Wang, Ramalingam Sridhar |
PVT variations aware optimal sleep vector determination of dual VT domino OR circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011, pp. 359-364, 2011, IEEE, 978-1-4577-1616-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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5 | Wenbin Liu, Jinhui Wang, Wuchen Wu, Xiaohong Peng, Ligang Hou |
A study of dual-Vt configurations of an 8T SRAM cell in 45nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 295-298, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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5 | Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino |
Dual-Vt assignment policies in ITD-aware synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 41(9), pp. 547-553, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
5 | Jun Seomun, Seungwhun Paik, Youngsoo Shin |
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010, pp. 581-586, 2010, IEEE, 978-1-60558-837-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
5 | Junjun Gu, Gang Qu 0001, Lin Yuan |
Enhancing dual-Vt design with consideration of on-chip temperature variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings, pp. 542-547, 2010, IEEE Computer Society, 978-1-4244-8936-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
5 | Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano |
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009, pp. 104-111, 2009, IEEE Computer Society, 978-1-4244-4377-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
5 | Na Gong, Baozeng Guo, Jianzhong Lou, Jinhui Wang |
Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 39(9), pp. 1149-1155, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi |
A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 4(2), pp. 191-201, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Sudip Roy 0001, Ajit Pal |
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 282-289, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi |
A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 45-50, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino |
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 217-220, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Sherif A. Tawfik, Volkan Kursun |
Low power and robust 7T dual-Vt SRAM circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1452-1455, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
5 | Yu Wang 0002, Huazhong Yang, Hui Wang 0004 |
Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 15(2), pp. 197-216, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
5 | Akhilesh Kumar, Mohab Anis |
Dual-Vt FPGA design for leakage power reduction (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 272, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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5 | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De |
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 567-573, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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5 | Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar |
Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(9), pp. 1536-1543, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
5 | Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De |
A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(5), pp. 839-842, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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5 | Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar |
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003, pp. 617-620, 2003, IEEE, 0-7803-7842-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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5 | Sriram R. Vangal, Mark A. Anders 0001, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar |
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(11), pp. 1421-1432, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
5 | Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De |
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pp. 207-212, 2001, ACM, 1-58113-371-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
5 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Noise constrained power optimization for dual VT domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 158-161, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
5 | Qi Wang, Sarma B. K. Vrudhula |
Static power optimization of deep submicron CMOS circuits for dual VT technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 490-496, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
4 | David Bol, Denis Flandre, Jean-Didier Legat |
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 21-26, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power |
4 | Bruno Bougard, Bjorn De Sutter, Sebastien Rabou, David Novo, Osman Allam, Steven Dupont, Liesbet Van der Perre |
A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 716-721, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
4 | Mu-Tien Chang, Po-Tsang Huang, Wei Hwang |
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 175-178, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
4 | Soheil Ghiasi |
Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 127-129, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
4 | Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny |
Low-leakage repeaters for NoC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 600-603, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
4 | Chris H. Kim, Steven Hsu, Ram Krishnamurthy 0001, Shekhar Borkar, Kaushik Roy 0001 |
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 100-105, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
4 | Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato |
A leakage-energy-reduction technique for highly-associative caches in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 32(3), pp. 50-54, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cache memories, embedded processors, leakage current |
4 | Seiichiro Fujii, Toshinori Sato |
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 217-226, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
4 | Navid Azizi, Farid N. Najm |
An Asymmetric SRAM Cell to Lower Gate Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 534-539, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
4 | Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim |
Charge-Sharing-Problem Reduced Split-Path Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 201-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
4 | Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson |
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 225-230, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
4 | Dongwoo Lee, David T. Blaauw |
Static leakage reduction through simultaneous threshold voltage and state assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 191-194, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
4 | Jason Stinson, Stefan Rusu |
A 1.5GHz third generation itaniumĀ® 2 processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 706-709, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
on-die cache, reliability, test, design methodology, processor |
4 | James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan |
Subthreshold leakage modeling and reduction techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 141-148, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
4 | Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
Reducing leakage in a high-performance deep-submicron instruction cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 77-89, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
4 | Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch |
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 112-125, 2000, Springer, 3-540-42329-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
4 | Martin Margala |
Low-Power SRAM Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 115-122, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
design, VLSI, low-power, SRAM, low-voltage |
4 | David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards |
Emerging power management tools for processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 143-148, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power CAD, standby leakage, power distribution |
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