Search results for "equivalence-Checking"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
69	In-Ho Moon, Per Bjesse, Carl Pixley	A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.	DATE	2007	DBLP DOI BibTeX RDF
67	Radu Mateescu 0001, Emilie Oudot	Improved On-the-Fly Equivalence Checking Using Boolean Equation Systems.	SPIN	2008	DBLP DOI BibTeX RDF
66	Tathagato Rai Dastidar, P. P. Chakrabarti 0001	A verification system for transient response of analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response
64	Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma	Non-cycle-accurate sequential equivalence checking.	DAC	2009	DBLP DOI BibTeX RDF	unit product machine, model checking, formal verification, high level synthesis, sequential equivalence checking
64	Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple	Combinational equivalence checking through function transformation.	ICCAD	2002	DBLP DOI BibTeX RDF	combinational verification, equivalence checking
61	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?	VTS	2002	DBLP DOI BibTeX RDF
59	Dan Zhu, Tun Li, Yang Guo 0003, Sikun Li	2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions.	ISQED	2008	DBLP DOI BibTeX RDF	cutpoints, Program slicing, Sequential equivalence checking
59	Stefan Disch, Christoph Scholl 0001	Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets.	ASP-DAC	2007	DBLP DOI BibTeX RDF	shared circuit structures, incremental SAT techniques, bounded model checking, combinational equivalence checking
57	Bijan Alizadeh, Masahiro Fujita	Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions.	ATVA	2007	DBLP DOI BibTeX RDF	Formal Verification, System on a Chip (SoC), Communication System, Canonical Representation, Sequential Equivalence Checking
56	Vishwani D. Agrawal	Choice of Tests for Logic Verification and Equivalence Checking.	VLSI Design	2000	DBLP DOI BibTeX RDF	fault simulation, Equivalence checking, Hamming codes, logic verification
56	Hiroaki Yoshida, Masahiro Fujita	Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences.	ISQED	2009	DBLP DOI BibTeX RDF
55	Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita	Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs.	ISQED	2006	DBLP DOI BibTeX RDF
53	Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla	Leveraging sequential equivalence checking to enable system-level to RTL flows.	DAC	2008	DBLP DOI BibTeX RDF	formal verification, high-level synthesis, equivalence checking, system-level models, RTL models
53	Li Tan	An Abstract Schema for Equivalence-Checking Games.	VMCAI	2002	DBLP DOI BibTeX RDF
51	Demos Anastasakis, Lisa McIlwain, Slawomir Pilarski	Efficient equivalence checking with partitions and hierarchical cut-points.	DAC	2004	DBLP DOI BibTeX RDF	verification, logic design, equivalence checking
51	Simon Jolly, Atanas N. Parashkevov, Tim McDougall	Automated equivalence checking of switch level circuits .	DAC	2002	DBLP DOI BibTeX RDF	MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking
51	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking
51	João Marques-Silva 0001, Thomas Glass	Combinational Equivalence Checking Using Satisfiability and Recursive Learning.	DATE	1999	DBLP DOI BibTeX RDF	Boolean Satisfiability, Recursive Learning, Combinational Equivalence Checking
50	Gabriel P. Bischoff, Karl S. Brace, Gianpiero Cabodi	A Compositional Approach for Equivalence Checking of Sequential Circuits with Unknown Reset State and Overlapping Partitions.	EUROCAST	2007	DBLP DOI BibTeX RDF
50	Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu	Automatic decomposition for sequential equivalence checking of system level and RTL descriptions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
50	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states
48	Dirk W. Hoffmann, Thomas Kropf	Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction.	CHARME	1999	DBLP DOI BibTeX RDF	Automatic error correction, design error diagnosis, formal methods, equivalence checking
48	In-Ho Moon	Compositional verification of retiming and sequential optimizations.	DAC	2008	DBLP DOI BibTeX RDF	conditional equivalence, retime offset, sequential equivalence, retiming, compositional verification
47	Eugene Goldberg	On equivalence checking and logic synthesis of circuits with a common specification.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	common specification, scalable equivalence checking, scalable logic synthesis, toggle equivalence
47	Subash Shankar, Masahiro Fujita	Rule-Based Approaches for Equivalence Checking of SpecC Programs.	MEMOCODE	2008	DBLP DOI BibTeX RDF
47	Masahiro Fujita	Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.	CHARME	2005	DBLP DOI BibTeX RDF
46	Xiaowei Li 0001, Guanghui Li 0001, Ming Shao	Formal Verification Techniques Based on Boolean Satisfiability Problem.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	incremental satisfiability, minimal unsatisfiable formula, model checking, equivalence checking
45	Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen	Novel Probabilistic Combinational Equivalence Checking.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
43	Yexin Zheng, Michael S. Hsiao, Chao Huang	SAT-based equivalence checking of threshold logic designs for nanotechnologies.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	SAT, nanotechnology, equivalence checking, threshold logic
43	Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod	Combinational equivalence checking for threshold logic circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	nano devices, EDA, equivalence checking, threshold logic
43	Philippe Georgelin, Venkat Krishnaswamy	Towards a C++-based design methodology facilitating sequential equivalence checking.	DAC	2006	DBLP DOI BibTeX RDF	modeling methodology, sequential equivalence checking
43	Paul Tafertshofer, Andreas Ganz, Manfred Henftling	A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists.	ICCAD	1997	DBLP DOI BibTeX RDF	SAT-based implication engine, circuit clause description, efficient ATPG, implication evaluation, indirect implications, netlist optimization, structure based methods, graph algorithms, automatic testing, logic circuits, graph model, equivalence checking, implication graph
43	Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva 0001	Towards Equivalence Checking Between TLM and RTL Models.	MEMOCODE	2007	DBLP DOI BibTeX RDF
43	Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, Basant Dwivedi, Antara Ghosh	Construction of concrete verification models from C++.	DAC	2008	DBLP DOI BibTeX RDF	formal verification, C++, pointers, equivalence checking, dynamic memory allocation
42	In-Ho Moon, Carl Pixley	Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders.	FMCAD	2004	DBLP DOI BibTeX RDF
42	Eugene Goldberg, Kanupriya Gulati	On Complexity of Internal and External Equivalence Checking.	DSD	2007	DBLP DOI BibTeX RDF
42	Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen	Equivalence checking of combinational circuits using Boolean expression diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
39	Jason Baumgartner, Hari Mony, Michael L. Case, Jun Sawada, Karen Yorav	Scalable conditional equivalence checking: An automated invariant-generation based approach.	FMCAD	2009	DBLP DOI BibTeX RDF
38	Radu Mateescu 0001, Emilie Oudot	Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation Systems.	MEMOCODE	2008	DBLP DOI BibTeX RDF
38	Changrui Yu, Hongwei Wang 0009, Yan Luo	Extended Ontology Model and Ontology Checking Based on Description Logics.	FSKD	2006	DBLP DOI BibTeX RDF
37	Jacob A. Abraham, Daniel G. Saab	Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.	VLSI Design	2007	DBLP DOI BibTeX RDF
37	Jie-Hong Roland Jiang, Wei-Lun Hung	Inductive equivalence checking under retiming and resynthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
37	Alfred Kölbl, Jerry R. Burch, Carl Pixley	Memory Modeling in ESL-RTL Equivalence Checking.	DAC	2007	DBLP DOI BibTeX RDF
37	Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau	Expression equivalence checking using interval analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
37	Eugene Goldberg	Equivalence Checking of Circuits with Parameterized Specifications.	SAT	2005	DBLP DOI BibTeX RDF
37	Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau	Equivalence checking of arithmetic expressions using fast evaluation.	CASES	2005	DBLP DOI BibTeX RDF	expression equivalence, mutual exclusion, interval analysis
37	Damien Bergamini, Nicolas Descoubes, Christophe Joubert, Radu Mateescu 0001	BISIMULATOR: A Modular Tool for On-the-Fly Equivalence Checking.	TACAS	2005	DBLP DOI BibTeX RDF
37	Dominik Stoffel, Wolfgang Kunz	Equivalence checking of arithmetic circuits on the arithmetic bit level.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
37	C. A. J. van Eijk	Sequential equivalence checking based on structural similarities.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
37	Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther 0001	A Method for Approximate Equivalence Checking.	ISMVL	2000	DBLP DOI BibTeX RDF
37	C. A. J. van Eijk	Sequential Equivalence Checking without State Space Traversal.	DATE	1998	DBLP DOI BibTeX RDF
36	Xiushan Feng, Alan J. Hu	Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification.	DAC	2006	DBLP DOI BibTeX RDF	cutpoints, formal equivalence checking, software, RTL
36	Dominik Stoffel, Wolfgang Kunz	Record & play: a structural fixed point iteration for sequential circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
36	Zurab Khasidashvili, Daher Kaiss, Doron Bustan	A compositional theory for post-reboot observational equivalence checking of hardware.	FMCAD	2009	DBLP DOI BibTeX RDF
36	Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai	Robust Boolean reasoning for equivalence checking and functional property verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
35	Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao	Fortifying analog models with equivalence checking and coverage analysis.	DAC	2010	DBLP DOI BibTeX RDF	analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation
35	Masahiro Fujita	Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	formal verification, High-level synthesis, equivalence checking, behavior synthesis
35	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer	AQUILA: An Equivalence Checking System for Large Sequential Designs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	state exploration, formal verification, Design verification, equivalence checking
35	Aarti Gupta, Pranav Ashar	Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.	VLSI Design	1998	DBLP DOI BibTeX RDF	ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs)
35	Alexandre V. Bystrov, I. B. Verbistskaite	Implementing Model Checking and Equivalence Checking for Time Petri Nets by the RT-MEC Tool.	PaCT	1999	DBLP DOI BibTeX RDF
35	Dirk W. Hoffmann, Thomas Kropf	Automatic Error Correction of Tri-State Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	Automatic error correction, tri-states, fault diagnosis, BDDs, equivalence checking
34	Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén	Improvements to combinational equivalence checking.	ICCAD	2006	DBLP DOI BibTeX RDF
34	K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens	Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code.	DATE	2005	DBLP DOI BibTeX RDF
34	Jiunn-Chern Chen, Yirng-An Chen	Equivalence checking of integer multipliers.	ASP-DAC	2001	DBLP DOI BibTeX RDF
32	Nikolaos D. Liveris, Hai Zhou 0001, Prithviraj Banerjee	Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
32	Brian Kahne, Magdy S. Abadir	Retiming Verification Using Sequential Equivalence Checking.	MTV	2005	DBLP DOI BibTeX RDF
32	Vladimir A. Zakharov, Ivan Zakharyaschev	On the Equivalence-Checking Problem for a Model of Programs Related with Multi-tape Automata.	CIAA	2004	DBLP DOI BibTeX RDF
32	Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann	Design Of Provably Correct Storage Arrays.	VLSI Design	2001	DBLP DOI BibTeX RDF
31	Changrui Yu, Yan Luo	Term Consistency Checking of Ontology Model Based on Description Logics.	KSEM	2007	DBLP DOI BibTeX RDF
30	Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler	Utilizing don't care states in SAT-based bounded sequential problems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	don't care states, unreachable states, satisfiability, bounded model checking, sequential equivalence checking
30	Subash Chandar G., S. Vaideeswaran	Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers.	ASP-DAC	2001	DBLP DOI BibTeX RDF
29	Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara	Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas.	ATVA	2004	DBLP DOI BibTeX RDF
29	Sven Verdoolaege, Gerda Janssens, Maurice Bruynooghe	Equivalence Checking of Static Affine Programs Using Widening to Handle Recurrences.	CAV	2009	DBLP DOI BibTeX RDF
29	Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes	Improving SAT-based Combinational Equivalence Checking through circuit preprocessing.	ICCD	2008	DBLP DOI BibTeX RDF
29	Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz	Structural FSM traversal.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
29	Tadaaki Tanimoto, Suguru Sasaki, Akio Nakata, Teruo Higashino	A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata.	ATVA	2004	DBLP DOI BibTeX RDF
27	Radu Mateescu 0001	CAESAR_SOLVE: A generic library for on-the-fly resolution of alternation-free Boolean equation systems.	Int. J. Softw. Tools Technol. Transf.	2006	DBLP DOI BibTeX RDF	Boolean equation system, Verification, Temporal logic, Bisimulation, Partial-order reduction
27	Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes	BenCGen: a digital circuit generation tool for benchmarks.	SBCCI	2008	DBLP DOI BibTeX RDF	benchmarks, sat solvers, combinational equivalence checking
27	Kelvin Ng	Challenges in using system-level models for RTL verification.	DAC	2008	DBLP DOI BibTeX RDF	simulation, equivalence checking, system-level model, RTL models
27	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Fixing Design Errors with Counterexamples and Resynthesis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking
27	Chandan Karfa, Dipankar Sarkar 0001, Chittaranjan A. Mandal, Chris Reade	Hand-in-hand verification of high-level synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FSMD model, formal verification, high-level synthesis, equivalence checking
27	Tao Feng 0012, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin	Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Formal verification, equivalence checking, symbolic simulation
27	Maher N. Mneimneh, Karem A. Sakallah	Principles of Sequential-Equivalence Verification.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	conceptual and algorithmic approache, ATPG, sequential-equivalence checking, satisfiability solvers
27	Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain	Solving the latch mapping problem in an industrial setting.	DAC	2003	DBLP DOI BibTeX RDF	latch mapping, combinational equivalence checking
27	Wael M. Elseaidy, Rance Cleaveland	A tool for modeling and verifying real-time systems.	ICECCS	1995	DBLP DOI BibTeX RDF	real-time systems verification, verification environment, graphical design la, Modechart, textually based language, Temporal CCS, system minimization, active structural control systems, real-time systems, formal verification, software tools, visual languages, equivalence checking, modeling tool
27	Martin Gebser, Torsten Schaub, Hans Tompits, Stefan Woltran	Alternative Characterizations for Program Equivalence under Answer-Set Semantics Based on Unfounded Sets.	FoIKS	2008	DBLP DOI BibTeX RDF
27	Michele Boreale, Rocco De Nicola, Rosario Pugliese	Proof Techniques for Cryptographic Processes.	LICS	1999	DBLP DOI BibTeX RDF	Logical aspects of protocol security, Formal methods, Semantics, Concurrency
26	Marc Herbstritt, Vanessa Struve, Bernd Becker 0001	Application of Lifting in Partial Design Analysis.	MTV	2007	DBLP DOI BibTeX RDF
26	Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita	Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis.	HLDVT	2006	DBLP DOI BibTeX RDF
24	Weixin Wu, Michael S. Hsiao	Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber 0001, Christian Jacobi 0002, Matthias Pflanz	Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.	ASP-DAC	2008	DBLP DOI BibTeX RDF
24	Carl Pixley	Practical Considerations Concerning HL-to -RT Equivalence Checking.	Haifa Verification Conference	2008	DBLP DOI BibTeX RDF
24	Shih-Chieh Wu, Chun-Yao Wang	PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
24	Weixin Wu, Michael S. Hsiao	Mining global constraints for improving bounded sequential equivalence checking.	DAC	2006	DBLP DOI BibTeX RDF	multi-node constraint, SAT, mining
24	Wei Huang, Pushan Tang, Min Ding 0004	Sequential equivalence checking using cuts.	ASP-DAC	2005	DBLP DOI BibTeX RDF
24	Mona Safar, M. Watheq El-Kharashi, Ashraf Salem	An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking.	IWSOC	2005	DBLP DOI BibTeX RDF
24	Lun Li, Mitchell A. Thornton, Stephen A. Szygenda	A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking.	ISVLSI	2004	DBLP DOI BibTeX RDF
24	Prabhat Mishra 0001, Nikil D. Dutt	A Methodology for Validation of Microprocessors using Equivalence Checking.	MTV	2003	DBLP DOI BibTeX RDF
24	Zhan Xu, Xiaolang Yan, Yongjiang Lu, Haitong Ge	Equivalence Checking Using Independent Cuts.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
24	Petr Jancar, Antonín Kucera 0001, Faron Moller, Zdenek Sawa	Equivalence-Checking with One-Counter Automata: A Generic Method for Proving Lower Bounds.	FoSSaCS	2002	DBLP DOI BibTeX RDF