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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 245 occurrences of 144 keywords
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Results
Found 515 publication records. Showing 515 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
69 | In-Ho Moon, Per Bjesse, Carl Pixley |
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1170-1175, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
67 | Radu Mateescu 0001, Emilie Oudot |
Improved On-the-Fly Equivalence Checking Using Boolean Equation Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 15th International SPIN Workshop, Los Angeles, CA, USA, August 10-12, 2008, Proceedings, pp. 196-213, 2008, Springer, 978-3-540-85113-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
66 | Tathagato Rai Dastidar, P. P. Chakrabarti 0001 |
A verification system for transient response of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 31:1-31:39, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response |
64 | Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol Mathur, Nikhil Sharma |
Non-cycle-accurate sequential equivalence checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 460-465, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
unit product machine, model checking, formal verification, high level synthesis, sequential equivalence checking |
64 | Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple |
Combinational equivalence checking through function transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 526-533, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
combinational verification, equivalence checking |
61 | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 275-280, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
59 | Dan Zhu, Tun Li, Yang Guo 0003, Sikun Li |
2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 637-642, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cutpoints, Program slicing, Sequential equivalence checking |
59 | Stefan Disch, Christoph Scholl 0001 |
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 938-943, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
shared circuit structures, incremental SAT techniques, bounded model checking, combinational equivalence checking |
57 | Bijan Alizadeh, Masahiro Fujita |
Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings, pp. 129-144, 2007, Springer, 978-3-540-75595-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Formal Verification, System on a Chip (SoC), Communication System, Canonical Representation, Sequential Equivalence Checking |
56 | Vishwani D. Agrawal |
Choice of Tests for Logic Verification and Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 306-311, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fault simulation, Equivalence checking, Hamming codes, logic verification |
56 | Hiroaki Yoshida, Masahiro Fujita |
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 366-370, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
55 | Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita |
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 370-375, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla |
Leveraging sequential equivalence checking to enable system-level to RTL flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 816-821, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal verification, high-level synthesis, equivalence checking, system-level models, RTL models |
53 | Li Tan |
An Abstract Schema for Equivalence-Checking Games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VMCAI ![In: Verification, Model Checking, and Abstract Interpretation, Third International Workshop, VMCAI 2002, Venice, Italy, January 21-22, 2002, Revised Papers, pp. 65-78, 2002, Springer, 3-540-43631-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Demos Anastasakis, Lisa McIlwain, Slawomir Pilarski |
Efficient equivalence checking with partitions and hierarchical cut-points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 539-542, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
verification, logic design, equivalence checking |
51 | Simon Jolly, Atanas N. Parashkevov, Tim McDougall |
Automated equivalence checking of switch level circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 299-304, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking |
51 | Pranav Ashar, Aarti Gupta, Sharad Malik |
Using complete-1-distinguishability for FSM equivalence checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 569-590, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking |
51 | João Marques-Silva 0001, Thomas Glass |
Combinational Equivalence Checking Using Satisfiability and Recursive Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 145-149, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Boolean Satisfiability, Recursive Learning, Combinational Equivalence Checking |
50 | Gabriel P. Bischoff, Karl S. Brace, Gianpiero Cabodi |
A Compositional Approach for Equivalence Checking of Sequential Circuits with Unknown Reset State and Overlapping Partitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2007, 11th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 12-16, 2007, Revised Selected Papers, pp. 505-514, 2007, Springer, 978-3-540-75866-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
50 | Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu |
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 27-29 July 2006, Embassy Suites, Napa, California, USA, pp. 71-80, 2006, IEEE Computer Society, 1-4244-0421-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee |
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(4), pp. 600-625, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states |
48 | Dirk W. Hoffmann, Thomas Kropf |
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 157-171, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Automatic error correction, design error diagnosis, formal methods, equivalence checking |
48 | In-Ho Moon |
Compositional verification of retiming and sequential optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 131-136, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
conditional equivalence, retime offset, sequential equivalence, retiming, compositional verification |
47 | Eugene Goldberg |
On equivalence checking and logic synthesis of circuits with a common specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 102-107, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
common specification, scalable equivalence checking, scalable logic synthesis, toggle equivalence |
47 | Subash Shankar, Masahiro Fujita |
Rule-Based Approaches for Equivalence Checking of SpecC Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 39-48, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Masahiro Fujita |
Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 340-344, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Xiaowei Li 0001, Guanghui Li 0001, Ming Shao |
Formal Verification Techniques Based on Boolean Satisfiability Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(1), pp. 38-47, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
incremental satisfiability, minimal unsatisfiable formula, model checking, equivalence checking |
45 | Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen |
Novel Probabilistic Combinational Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 365-375, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Yexin Zheng, Michael S. Hsiao, Chao Huang |
SAT-based equivalence checking of threshold logic designs for nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 225-230, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SAT, nanotechnology, equivalence checking, threshold logic |
43 | Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod |
Combinational equivalence checking for threshold logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 102-107, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nano devices, EDA, equivalence checking, threshold logic |
43 | Philippe Georgelin, Venkat Krishnaswamy |
Towards a C++-based design methodology facilitating sequential equivalence checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 93-96, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
modeling methodology, sequential equivalence checking |
43 | Paul Tafertshofer, Andreas Ganz, Manfred Henftling |
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 648-655, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
SAT-based implication engine, circuit clause description, efficient ATPG, implication evaluation, indirect implications, netlist optimization, structure based methods, graph algorithms, automatic testing, logic circuits, graph model, equivalence checking, implication graph |
43 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva 0001 |
Towards Equivalence Checking Between TLM and RTL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30 - June 1st, Nice, France, pp. 113-122, 2007, IEEE Computer Society, 1-4244-1050-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, Basant Dwivedi, Antara Ghosh |
Construction of concrete verification models from C++. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 942-947, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal verification, C++, pointers, equivalence checking, dynamic memory allocation |
42 | In-Ho Moon, Carl Pixley |
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004, Proceedings, pp. 144-158, 2004, Springer, 3-540-23738-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Eugene Goldberg, Kanupriya Gulati |
On Complexity of Internal and External Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 197-206, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen |
Equivalence checking of combinational circuits using Boolean expression diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 903-917, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
39 | Jason Baumgartner, Hari Mony, Michael L. Case, Jun Sawada, Karen Yorav |
Scalable conditional equivalence checking: An automated invariant-generation based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 120-127, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Radu Mateescu 0001, Emilie Oudot |
Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 73-74, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Changrui Yu, Hongwei Wang 0009, Yan Luo |
Extended Ontology Model and Ontology Checking Based on Description Logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD ![In: Fuzzy Systems and Knowledge Discovery, Third International Conference, FSKD 2006, Xi'an, China, September 24-28, 2006, Proceedings, pp. 607-610, 2006, Springer, 3-540-45916-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Jacob A. Abraham, Daniel G. Saab |
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 6, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Jie-Hong Roland Jiang, Wei-Lun Hung |
Inductive equivalence checking under retiming and resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 326-333, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Alfred Kölbl, Jerry R. Burch, Carl Pixley |
Memory Modeling in ESL-RTL Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 205-209, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau |
Expression equivalence checking using interval analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 830-842, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Eugene Goldberg |
Equivalence Checking of Circuits with Parameterized Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing, 8th International Conference, SAT 2005, St. Andrews, UK, June 19-23, 2005, Proceedings, pp. 107-121, 2005, Springer, 3-540-26276-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau |
Equivalence checking of arithmetic expressions using fast evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 147-156, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
expression equivalence, mutual exclusion, interval analysis |
37 | Damien Bergamini, Nicolas Descoubes, Christophe Joubert, Radu Mateescu 0001 |
BISIMULATOR: A Modular Tool for On-the-Fly Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 11th International Conference, TACAS 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-8, 2005, Proceedings, pp. 581-585, 2005, Springer, 3-540-25333-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Dominik Stoffel, Wolfgang Kunz |
Equivalence checking of arithmetic circuits on the arithmetic bit level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5), pp. 586-597, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | C. A. J. van Eijk |
Sequential equivalence checking based on structural similarities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7), pp. 814-819, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther 0001 |
A Method for Approximate Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 447-452, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | C. A. J. van Eijk |
Sequential Equivalence Checking without State Space Traversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 618-623, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Xiushan Feng, Alan J. Hu |
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 1063-1068, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cutpoints, formal equivalence checking, software, RTL |
36 | Dominik Stoffel, Wolfgang Kunz |
Record & play: a structural fixed point iteration for sequential circuit verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 394-399, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design |
36 | Zurab Khasidashvili, Daher Kaiss, Doron Bustan |
A compositional theory for post-reboot observational equivalence checking of hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 136-143, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai |
Robust Boolean reasoning for equivalence checking and functional property verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1377-1394, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao |
Fortifying analog models with equivalence checking and coverage analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 425-430, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation |
35 | Masahiro Fujita |
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 610-626, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
formal verification, High-level synthesis, equivalence checking, behavior synthesis |
35 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer |
AQUILA: An Equivalence Checking System for Large Sequential Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(5), pp. 443-464, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
state exploration, formal verification, Design verification, equivalence checking |
35 | Aarti Gupta, Pranav Ashar |
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 222-225, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ATPG techniques, circuit similarity, formal verification, combinational circuits, Boolean satisfiability (SAT), combinational equivalence checking, Binary Decision Diagrams (BDDs) |
35 | Alexandre V. Bystrov, I. B. Verbistskaite |
Implementing Model Checking and Equivalence Checking for Time Petri Nets by the RT-MEC Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 5th International Conference, PaCT-99, St. Petersburg, Russia, September 6-10, 1999, Proceedings, pp. 194-199, 1999, Springer, 3-540-66363-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Dirk W. Hoffmann, Thomas Kropf |
Automatic Error Correction of Tri-State Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 51-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Automatic error correction, tri-states, fault diagnosis, BDDs, equivalence checking |
34 | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén |
Improvements to combinational equivalence checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 836-843, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens |
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1310-1315, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Jiunn-Chern Chen, Yirng-An Chen |
Equivalence checking of integer multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 169-174, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Nikolaos D. Liveris, Hai Zhou 0001, Prithviraj Banerjee |
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 636-641, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Brian Kahne, Magdy S. Abadir |
Retiming Verification Using Sequential Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 138-142, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Vladimir A. Zakharov, Ivan Zakharyaschev |
On the Equivalence-Checking Problem for a Model of Programs Related with Multi-tape Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIAA ![In: Implementation and Application of Automata, 9th International Conference, CIAA 2004, Kingston, Canada, July 22-24, 2004, Revised Selected Papers, pp. 293-305, 2004, Springer, 3-540-24318-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann |
Design Of Provably Correct Storage Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 196-, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Changrui Yu, Yan Luo |
Term Consistency Checking of Ontology Model Based on Description Logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KSEM ![In: Knowledge Science, Engineering and Management, Second International Conference, KSEM 2007, Melbourne, Australia, November 28-30, 2007, Proceedings, pp. 496-501, 2007, Springer, 978-3-540-76718-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler |
Utilizing don't care states in SAT-based bounded sequential problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 264-269, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
don't care states, unreachable states, satisfiability, bounded model checking, sequential equivalence checking |
30 | Subash Chandar G., S. Vaideeswaran |
Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 175-180, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara |
Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings, pp. 108-119, 2004, Springer, 3-540-23610-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Sven Verdoolaege, Gerda Janssens, Maurice Bruynooghe |
Equivalence Checking of Static Affine Programs Using Widening to Handle Recurrences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 599-613, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes |
Improving SAT-based Combinational Equivalence Checking through circuit preprocessing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 40-45, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz |
Structural FSM traversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5), pp. 598-619, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Tadaaki Tanimoto, Suguru Sasaki, Akio Nakata, Teruo Higashino |
A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings, pp. 179-195, 2004, Springer, 3-540-23610-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Radu Mateescu 0001 |
CAESAR_SOLVE: A generic library for on-the-fly resolution of alternation-free Boolean equation systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 8(1), pp. 37-56, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Boolean equation system, Verification, Temporal logic, Bisimulation, Partial-order reduction |
27 | Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes |
BenCGen: a digital circuit generation tool for benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 164-169, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
benchmarks, sat solvers, combinational equivalence checking |
27 | Kelvin Ng |
Challenges in using system-level models for RTL verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 812-815, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, equivalence checking, system-level model, RTL models |
27 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Fixing Design Errors with Counterexamples and Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 944-949, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
simulation-based verification, digital design errors, error-correction framework, resynthesis techniques, goal-directed search, entropy-guided search, counterexamples, digital designs, combinational equivalence-checking |
27 | Chandan Karfa, Dipankar Sarkar 0001, Chittaranjan A. Mandal, Chris Reade |
Hand-in-hand verification of high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 429-434, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FSMD model, formal verification, high-level synthesis, equivalence checking |
27 | Tao Feng 0012, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin |
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 627-650, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Formal verification, equivalence checking, symbolic simulation |
27 | Maher N. Mneimneh, Karem A. Sakallah |
Principles of Sequential-Equivalence Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(3), pp. 248-257, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
conceptual and algorithmic approache, ATPG, sequential-equivalence checking, satisfiability solvers |
27 | Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain |
Solving the latch mapping problem in an industrial setting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 442-447, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
latch mapping, combinational equivalence checking |
27 | Wael M. Elseaidy, Rance Cleaveland |
A tool for modeling and verifying real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 1st IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '95), November 6-10, 1995, Fort Lauderdale, Florida, USA, pp. 70-, 1995, IEEE Computer Society, 0-8186-7123-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
real-time systems verification, verification environment, graphical design la, Modechart, textually based language, Temporal CCS, system minimization, active structural control systems, real-time systems, formal verification, software tools, visual languages, equivalence checking, modeling tool |
27 | Martin Gebser, Torsten Schaub, Hans Tompits, Stefan Woltran |
Alternative Characterizations for Program Equivalence under Answer-Set Semantics Based on Unfounded Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FoIKS ![In: Foundations of Information and Knowledge Systems, 5th International Symposium, FoIKS 2008, Pisa, Italy, February 11-15, 2008, Proceedings, pp. 24-41, 2008, Springer, 978-3-540-77683-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Michele Boreale, Rocco De Nicola, Rosario Pugliese |
Proof Techniques for Cryptographic Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LICS ![In: 14th Annual IEEE Symposium on Logic in Computer Science, Trento, Italy, July 2-5, 1999, pp. 157-166, 1999, IEEE Computer Society, 0-7695-0158-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Logical aspects of protocol security, Formal methods, Semantics, Concurrency |
26 | Marc Herbstritt, Vanessa Struve, Bernd Becker 0001 |
Application of Lifting in Partial Design Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA, pp. 33-38, 2007, IEEE Computer Society, 978-0-7695-3241-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita |
Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, Monterey, CA, USA, Nov 9-10, 2006, pp. 162-169, 2006, IEEE Computer Society, 1-4244-0679-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Weixin Wu, Michael S. Hsiao |
Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 197-201, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber 0001, Christian Jacobi 0002, Matthias Pflanz |
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 398-403, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Carl Pixley |
Practical Considerations Concerning HL-to -RT Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings, pp. 6, 2008, Springer, 978-3-642-01701-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Shih-Chieh Wu, Chun-Yao Wang |
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 104-109, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Weixin Wu, Michael S. Hsiao |
Mining global constraints for improving bounded sequential equivalence checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 743-748, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-node constraint, SAT, mining |
24 | Wei Huang, Pushan Tang, Min Ding 0004 |
Sequential equivalence checking using cuts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 455-458, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Mona Safar, M. Watheq El-Kharashi, Ashraf Salem |
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 419-424, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Lun Li, Mitchell A. Thornton, Stephen A. Szygenda |
A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 32-38, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Prabhat Mishra 0001, Nikil D. Dutt |
A Methodology for Validation of Microprocessors using Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA, pp. 83-88, 2003, IEEE Computer Society, 0-7695-2045-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Zhan Xu, Xiaolang Yan, Yongjiang Lu, Haitong Ge |
Equivalence Checking Using Independent Cuts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 482-487, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Petr Jancar, Antonín Kucera 0001, Faron Moller, Zdenek Sawa |
Equivalence-Checking with One-Counter Automata: A Generic Method for Proving Lower Bounds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FoSSaCS ![In: Foundations of Software Science and Computation Structures, 5th International Conference, FOSSACS 2002. Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2002 Grenoble, France, April 8-12, 2002, Proceedings, pp. 172-186, 2002, Springer, 3-540-43366-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
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