Search results for "flip-flop"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
193	Kuo-Hsing Cheng, Yung-Hsiang Lin	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
160	Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri	A robust, fast pulsed flip-flop design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flip-flop, latch
159	Saihua Lin, Huazhong Yang, Rong Luo	High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.	ISVLSI	2007	DBLP DOI BibTeX RDF
158	Pramod Kumar Meher	Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
155	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
146	Liam P. Maguire, T. Martin McGinnity, L. J. McDaid	From a Fuzzy Flip-Flop to a MVL Flip-Flop.	ISMVL	1999	DBLP DOI BibTeX RDF	MVL flip-flop, MOS implementation, fuzzy reasoning
141	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Pre-capturing static pulsed flip-flops.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
140	Amit Jain, David T. Blaauw	Slack borrowing in flip-flop based sequential circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	timing analysis
136	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
133	Motoi Inaba, Koichi Tanno, Okihiko Ishizuka	Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Multi-valued flip-flop, Down literal circuit, Analog inverter, Voltage comparator, NMIN circuit
121	Fatemeh Aezinia, Ali Afzali-Kusha, Caro Lucas	Optimizing High Speed Flip-Flop Using Genetic Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
121	Tolga Yalçin, Neslin Ismailoglu	Design of a fully-static differential low-power CMOS flip-flop.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
120	Kee Sup Kim, Charles R. Kime	Partial scan flip-flop selection by use of empirical testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	scan flip-flop selection, serial scan, design for testability, testability, partial scan
119	Marius Padure, Sorin Cotofana, Stamatis Vassiliadis	Design and experimental results of a CMOS flip-flop featuring embedded threshold logic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
119	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
117	Bo Fu, Paul Ampadu	Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency.	ISCAS	2007	DBLP DOI BibTeX RDF
113	Mohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi	Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops.	ISVLSI	2002	DBLP DOI BibTeX RDF	noise, power, flip-flop, deep submicron
111	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology.	ISVLSI	2006	DBLP DOI BibTeX RDF
111	A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha	Low power low leakage clock gated static pulsed flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
105	Jun Seomun, Jae-Hyun Kim, Youngsoo Shin	Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
104	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
95	Gerard Elineau, Werner Wiesbeck	An New J-K Flip-Flop for Synchronizers.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Arbiter circuit, data intersection, tunnel diode flip-flop, flip-flop, synchronizer circuit
95	Leo Sintonen	A Clocked Multivalued Flip-Flop.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	N-valued logic design, N-valued logic devices, N-state flip-flop, multivalued flip-flop, multivalued sequential circuits
93	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto	Single-Event Upset Analysis and Protection in High Speed Circuits.	ETS	2006	DBLP DOI BibTeX RDF
92	Chul Soo Kim, Joo-Seong Kim, Bai-Sun Kong, Yongsam Moon, Young-Hyun Jun	Presetting pulse-based flip-flop.	ISCAS	2008	DBLP DOI BibTeX RDF
92	Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini	A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	multiple-valued clock, CMOS, flip-flops, multiple-valued logic
92	Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra	A novel high-speed sense-amplifier-based flip-flop.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
92	Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao	Flip-Flop and Repeater Insertion for Early Interconnect Planning.	DATE	2002	DBLP DOI BibTeX RDF
92	Mark Vesterbacka	A robust differential scan flip-flop.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
92	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Energy recovery clocking scheme and flip-flops for ultra low-energy applications.	ISLPED	2003	DBLP DOI BibTeX RDF	flip-flop, clock, clock tree, energy recovery, adiabatic
91	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
90	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Conditional pre-charge techniques for power-efficient dual-edge clocking.	ISLPED	2002	DBLP DOI BibTeX RDF	clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution
89	Jun Seomun, Jaehyun Kim, Youngsoo Shin	Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.	DAC	2007	DBLP DOI BibTeX RDF
89	Sang-Dae Shin, Hun Choi, Bai-Sun Kong	Variable sampling window flip-flop for low-power application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
87	Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni	All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates.	OSC	2009	DBLP DOI BibTeX RDF	optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA)
87	Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic	Level conversion for dual-supply systems.	ISLPED	2003	DBLP DOI BibTeX RDF	level conversion, flip-flop, dual-supply voltage
84	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
84	Zhong-Ching Lu, Ting-Chi Wang	Concurrent flip-flop and buffer insertion with adaptive blockage avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
84	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	ARVLSI	2001	DBLP DOI BibTeX RDF
83	Omid Sarbishei, Mohammad Maymandi-Nejad	Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops.	ISCAS	2007	DBLP DOI BibTeX RDF
81	Håvard Pedersen Alstad, Snorre Aunet	Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology.	DDECS	2008	DBLP DOI BibTeX RDF
81	S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha	Double edge triggered Feedback Flip-Flop in sub 100NM technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
79	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.	ISCAS	2007	DBLP DOI BibTeX RDF
77	Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki	Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
75	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty	A TMR Scheme for SEU Mitigation in Scan Flip-Flops.	ISQED	2007	DBLP DOI BibTeX RDF
74	Jaehyun Kim, Youngsoo Shin	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.	ICCAD	2007	DBLP DOI BibTeX RDF
73	Rubil Ahmadi	A Hold Friendly Flip-Flop For Area Recovery.	ISCAS	2007	DBLP DOI BibTeX RDF
73	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante	Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.	DATE	1998	DBLP DOI BibTeX RDF
72	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
72	Dong Xiang, Yi Xu	Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals.	VTS	2001	DBLP DOI BibTeX RDF
72	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	On variable clock methods for path delay testing of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
71	Gustavo Neuberger, Gilson I. Wirth, Ricardo Reis 0001	Protecting digital circuits against hold time violation due to process variability.	SBCCI	2009	DBLP DOI BibTeX RDF	flip-flop characterization, hold time violations, race immunity, clock skew, process variability
68	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
67	G. Lacroix, Philippe Marchegay, G. Piel	Comments on "The Anomalous Behavior of Flip-Flops in Synchronizer Circuits".	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	uncertainty interval, Anomalous response of flip-flop, flip-flop metastable state, asynchronous interactions, synchronizer failures
66	Xiaoding Chen, Michael S. Hsiao	Energy-Efficient Logic BIST Based on State Correlation Analysis.	VTS	2003	DBLP DOI BibTeX RDF
66	Chau-Shen Chen, TingTing Hwang	Layout Driven Selection and Chaining of Partial Scan Flip-Flops.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization
65	Dong-Shong Liang, Kwang-Jow Gan	New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits.	DELTA	2008	DBLP DOI BibTeX RDF	negative differential resistance(NDR), monostable-bistable transition logic elements(MOBILE)
65	Saihua Lin, Rong Luo, Huazhong Yang, Hui Wang 0004	A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices.	APCCAS	2006	DBLP DOI BibTeX RDF
65	Myint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo	A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
65	Hui Zhang, Pinaki Mazumder	Design of a new sense amplifier flip-flop with improved power-delay-product.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
65	Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel	Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.	PATMOS	2004	DBLP DOI BibTeX RDF
65	Jacek Kluska, Zbigniew Hajduk	Digital Implementation of Fuzzy Petri Net Based on Asynchronous Fuzzy RS Flip-Flop.	ICAISC	2004	DBLP DOI BibTeX RDF
65	Satoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi	Flexible processor based on full-adder/ d-flip-flop merged module.	ASP-DAC	2001	DBLP DOI BibTeX RDF
65	Chulwoo Kim, Sung-Mo Kang	A low-power reduced swing single clock flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
65	Nikola Nedovic, Vojin G. Oklobdzija	Dynamic Flip-Flop with Improved Power.	ICCD	2000	DBLP DOI BibTeX RDF
65	Richard F. Hobson, Allan R. Dyck	A Multiple-Input Single-Phase Clock Flip-Flop Family.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
65	Hideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto	A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
64	Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta 0001	Optimization of Master-Slave Flip-Flops for High-Performance Applications.	PATMOS	2006	DBLP DOI BibTeX RDF
63	Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang	Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.	ISCAS	2006	DBLP DOI BibTeX RDF
63	Pradeep Varma, Ashutosh Chakraborty	Low-Voltage, Double-Edge-Triggered Flip Flop.	PATMOS	2003	DBLP DOI BibTeX RDF
63	Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou	A high-performance low-power static differential double edge-triggered flip-flop.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
61	Uthman Alsaiari, Resve A. Saleh	Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits.	ISQED	2008	DBLP DOI BibTeX RDF	Partitioning, Redundancy, Yield, Flip-Flop
61	Dong Xiang, Kaiwei Li, Hideo Fujiwara	Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
61	Subhasish Mitra, Edward J. McCluskey	Design Diversity for Concurrent Error Detection in Sequential Logic Circuts.	VTS	2001	DBLP DOI BibTeX RDF
60	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	A unified approach in the analysis of latches and flip-flops for low-power systems.	ISLPED	1998	DBLP DOI BibTeX RDF	master-slave latch, optimization, timing, flip-flop, power measurement
58	Safar Hatami, Hamed Abrishami, Massoud Pedram	Statistical timing analysis of flip-flops considering codependent setup and hold times.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time
58	Vivek Joshi, David T. Blaauw, Dennis Sylvester	Soft-edge flip-flops for improved timing yield: design and optimization.	ICCAD	2007	DBLP DOI BibTeX RDF
58	Hsing-Chung Liang, Chung-Len Lee	An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
56	Eric L. Hill, Mikko H. Lipasti	Transparent mode flip-flops for collapsible pipelines.	ICCD	2007	DBLP DOI BibTeX RDF
56	Ben Choi 0002, Kunal Tipnis	New Components for Building Fuzzy Logic Circuits.	FSKD (2)	2007	DBLP DOI BibTeX RDF
56	Chao Yan 0001, Mark R. Greenstreet	Circuit Level Verification of a High-Speed Toggle.	FMCAD	2007	DBLP DOI BibTeX RDF
56	Fatemeh Aezinia, S. Najafzadeh, Ali Afzali-Kusha	Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops.	APCCAS	2006	DBLP DOI BibTeX RDF
56	Clint Morgan, Darko Stefanovic, Cristopher Moore, Milan N. Stojanovic	Building the Components for a Biomolecular Computer.	DNA	2004	DBLP DOI BibTeX RDF
56	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
56	Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi	Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process.	IOLTS	2019	DBLP DOI BibTeX RDF
56	Motoki Tokumasu, Hiroshige Fujii, Masako Ohta, Tsunealu Fuse, Atsushi Kameyama	A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF).	CICC	2002	DBLP DOI BibTeX RDF
55	Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang	Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
55	Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001, Gilson I. Wirth, Ralf Brederlow, Christian Pacha	Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
55	Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar	Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic.	ISQED	2006	DBLP DOI BibTeX RDF
55	Peiyi Zhao, Pradeep Kumar Golconda, C. Archana, Magdy A. Bayoumi	A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.	ISVLSI	2004	DBLP DOI BibTeX RDF
55	Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He 0001	Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.	ISQED	2004	DBLP DOI BibTeX RDF
53	Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
53	Li Ding 0002, Pinaki Mazumder, N. Srinivas	A dual-rail static edge-triggered latch.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
53	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
53	Arun Balakrishnan, Srimat T. Chakradhar	Peripheral Partitioning and Tree Decomposition for Partial Scan.	VLSI Design	1998	DBLP DOI BibTeX RDF
52	Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe 0001, Marios C. Papaefthymiou	A 225 MHz resonant clocked ASIC chip.	ISLPED	2003	DBLP DOI BibTeX RDF	adiabatic logic, resonant LC tank, single phase, VLSI, CMOS, flip-flop, low energy, clock generator
52	Jongsun Park 0001, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy 0001	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
50	Varun Arora, Indranil Sengupta 0001	A Unified Approach to Partial Scan Design using Genetic Algorithm.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
50	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicitstate enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
50	Sudipta Bhawmik, Indradeep Ghosh	A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF