Search results for "gate-count"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
74	Minoru Watanabe, Fuminori Kobayashi	A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
72	Mao Nakajima, Daisaku Seto, Minoru Watanabe	A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time.	IPDPS	2008	DBLP DOI BibTeX RDF
69	Shinichi Kato, Minoru Watanabe	Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI.	SAMOS	2009	DBLP DOI BibTeX RDF
68	Minoru Watanabe, Fuminori Kobayashi	A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ARC	2006	DBLP DOI BibTeX RDF
47	Minoru Watanabe, Fuminori Kobayashi	An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit.	IPDPS	2005	DBLP DOI BibTeX RDF
44	Daisaku Seto, Minoru Watanabe	An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
43	Daisaku Seto, Minoru Watanabe	Analysis of retention time under multi-configuration on a DORGA.	SoCC	2008	DBLP DOI BibTeX RDF
41	Minoru Watanabe, Fuminori Kobayashi	An Improved Dynamic Optically Reconfigurable Gate Array.	ISVLSI	2005	DBLP DOI BibTeX RDF
40	Myung Hoon Sunwoo, Seong Keun Oh	A Multiplierless 2-D Convolver Chip for Real-Time Image Processing.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	image processing, VLSI design, VLSI architecture, convolution, multiplier, digital filter
35	Hussain Al-Asaad, John P. Hayes	Logic Design Validation via Simulation and Automatic Test Pattern Generation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	test generation, logic design, fault simulation, error modeling, design validation
35	Thomas W. Williams	Testing in Nanometer Technologies.	DATE	1999	DBLP DOI BibTeX RDF
33	Fei Li 0003, Lei He 0001, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy	High-level area and power-up current estimation considering rich cell library.	ASP-DAC	2004	DBLP DOI BibTeX RDF
32	Rui Zhang, Niraj K. Jha	State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi	272 Gate Count Optically Differential Reconfigurable Gate Array VLSI.	ERSA	2007	DBLP BibTeX RDF
30	Minoru Watanabe, Fuminori Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
30	Minoru Watanabe	An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI.	SoCC	2007	DBLP DOI BibTeX RDF
30	Minoru Watanabe, Fuminori Kobayashi	A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
29	James Donald, Niraj K. Jha	Reversible logic synthesis with Fredkin and Peres gates.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Quantum computing, reversible logic
27	Mao Nakajima, Minoru Watanabe	Fast Optical Reconfiguration of a Nine-Context DORGA.	ARC	2009	DBLP DOI BibTeX RDF
27	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
27	Minoru Watanabe, Fuminori Kobayashi	Power consumption advantage of a dynamic optically reconfigurable gate array.	IPDPS	2006	DBLP DOI BibTeX RDF
27	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Fredkin/Toffoli Templates for Reversible Logic Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
27	Lihui Ni, Zhijin Guan, Wenying Zhu	A General Method of Constructing the Reversible Full-Adder.	IITSI	2010	DBLP DOI BibTeX RDF	reversible full-adder, reversible gates, gate count, garbage outputs
27	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
26	Yu-Kun Lin, Chun-Wei Ku, De-Wei Li, Tian-Sheuan Chang	A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder.	IEEE Trans. Circuits Syst. Video Technol.	2009	DBLP DOI BibTeX RDF
24	Akashi Satoh	ASIC hardware implementations for 512-bit hash function Whirlpool.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Shuguang Zhao, Licheng Jiao	Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm.	Genet. Program. Evolvable Mach.	2006	DBLP DOI BibTeX RDF	Evolutionary design of circuits, Knowledge discovery, Evolvable hardware, Multi-objective genetic algorithm, Adaptive genetic algorithm
24	Kavel M. Büyüksahin, Farid N. Najm	High-level area estimation.	ISLPED	2002	DBLP DOI BibTeX RDF	boolean networks, area estimation
24	Hussain Al-Asaad, John P. Hayes	Design verification via simulation and automatic test pattern generation.	ICCAD	1995	DBLP DOI BibTeX RDF	test generation, logic simulation, Design verification, error models
23	Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi	A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays.	IPDPS	2007	DBLP DOI BibTeX RDF
23	Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi	An optically differential reconfigurable gate array with a holographic memory.	IPDPS	2006	DBLP DOI BibTeX RDF
23	Minoru Watanabe, Fuminori Kobayashi	Optically Reconfigurable Gate Arrays vs. ASICs.	APCCAS	2006	DBLP DOI BibTeX RDF
23	Arash Reyhani-Masoleh, M. Anwar Hasan	Efficient digit-serial normal basis multipliers over binary extension fields.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	security, finite field, normal basis, Digit-serial multiplier
23	Fei Li 0003, Lei He 0001, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy	High Level Area and Current Estimation.	PATMOS	2003	DBLP DOI BibTeX RDF
22	Jen-Chuan Chih, Kun-Lung Chen, Sau-Gee Chen	A CORDIC processor with efficient table-lookup schemes for rotations and on-line scale factor compensations.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
22	Von-Kyoung Kim, Tom Chen 0001, Mick Tegethoff	Fault Coverage Estimation for Early Stage of VLSI Design.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
21	Steve Thakur	An optimization of the addition gate count in Plonkish circuits.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
21	John Burke, Biswajit Basu, Ciaran McGoldrick	Reduced Gate Count for Quantum State Preparation of 2D Data.	QCE	2023	DBLP DOI BibTeX RDF
21	Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani	Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.	ISMVL	2023	DBLP DOI BibTeX RDF
21	Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder	Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS.	RADIOELEKTRONIKA	2023	DBLP DOI BibTeX RDF
21	Korbinian Staudacher, Tobias Guggemos, Sophia Grundner-Culemann, Wolfgang Gehrke	Reducing 2-QuBit Gate Count for ZX-Calculus based Quantum Circuit Optimization.	QPL	2022	DBLP DOI BibTeX RDF
21	Sunyeop Kim, Insung Kim, Seonggyeom Kim, Seokhie Hong	Toffoli gate count Optimized Space-Efficient Quantum Circuit for Binary Field Multiplication.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
21	Marcus Dansarie	sboxgates: A program for finding low gate count implementations of S-boxes.	J. Open Source Softw.	2021	DBLP DOI BibTeX RDF
21	Ian van Hoof	Space-efficient quantum multiplication polynomials for binary finite fields with sub-quadratoc Toffoli gate count.	Quantum Inf. Comput.	2020	DBLP DOI BibTeX RDF
21	Iggy van Hoof	Space-efficient quantum multiplication of polynomials for binary finite fields with sub-quadratic Toffoli gate count.	CoRR	2019	DBLP BibTeX RDF
21	Cupjin Huang, Michael Newman, Mario Szegedy	Explicit lower bounds on strong simulation of quantum circuits in terms of $T$-gate count.	CoRR	2019	DBLP BibTeX RDF
21	Iggy van Hoof	Space-efficient quantum multiplication of polynomials for binary finite fields with sub-quadratic Toffoli gate count.	IACR Cryptol. ePrint Arch.	2019	DBLP BibTeX RDF
21	Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, W. Shu, Joseph S. Chang, Bah-Hwee Gwee	Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design.	ISCAS	2019	DBLP DOI BibTeX RDF
21	Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka	A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications.	A-SSCC	2018	DBLP DOI BibTeX RDF
21	Sungkyung Park 0001, Chester Sungchung Park	Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
21	Shane Kepley, Rainer Steinwandt	Quantum circuits for 2n-multiplication with subquadratic gate count.	Quantum Inf. Process.	2015	DBLP DOI BibTeX RDF
21	Katherine L. Brown, Anmer Daskin, Sabre Kais, Jonathan P. Dowling	Reducing the number of ancilla qubits and the gate count required for creating large controlled operations.	Quantum Inf. Process.	2015	DBLP DOI BibTeX RDF
21	Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani	A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
21	Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu	A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
21	Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao	A novel low gate-count serializer topology with Multiplexer-Flip-Flops.	ISCAS	2012	DBLP DOI BibTeX RDF
21	José Sarmento, John T. Stonick	A minimal-gate-count fully digital frequency-tracking oversampling CDR circuit.	ISCAS	2010	DBLP DOI BibTeX RDF
21	Lei Chen, Shinji Kimura	Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
21	Matthew Kwan	Reducing the Gate Count of Bitslice DES.	IACR Cryptol. ePrint Arch.	2000	DBLP BibTeX RDF
20	Jae Hyun Baek, Myung Hoon Sunwoo	New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
20	Jaehyun Baek, Myung Hoon Sunwoo	Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Jang Woong Park, Jae Hyun Baek, Myung Hoon Sunwoo	Enhanced Degree Computationless Modified Euclid's Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Wei-Kai Chan, Shao-Yi Chien	Subword Parallel Architecture for Connected Component Labeling and Morphological Operations.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Elena Trichina, Tymur Korkishko	Secure AES Hardware Module for Resource Constrained Devices.	ESAS	2004	DBLP DOI BibTeX RDF
20	Siddika Berna Örs, Ahmet Dervisoglu	Modeling Bit Multiplication Blocks for DSP Applications Using VHDL.	EUROMICRO	1999	DBLP DOI BibTeX RDF
20	Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry	Low-Power Design of Finite Field Multipliers for Wireless Applications.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	architecture, low power, finite fields, multiplier
20	Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee	RSYN: a system for automated synthesis of reliable multilevel circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
19	Jimson Mathew, Hafizur Rahaman 0001, Babita R. Jose, Dhiraj K. Pradhan	Design of Reversible Finite Field Arithmetic Circuits with Error Detection.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Minoru Watanabe, Naoki Yamaguchi	An Acceleration and Optimization Method for Optical Reconfiguration.	VLSI Design	2008	DBLP DOI BibTeX RDF
19	Pallav Gupta, Abhinav Agrawal 0002, Niraj K. Jha	An Algorithm for Synthesis of Reversible Logic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Synthesis of Fredkin-Toffoli reversible networks.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Lu Xiao 0003, Howard M. Heys	Hardware Design and Analysisof Block Cipher Components.	ICISC	2002	DBLP DOI BibTeX RDF
19	Arash Reyhani-Masoleh, M. Anwar Hasan	Efficient digit-serial normal basis multipliers over GF(2m).	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	Eric M. Schwarz, Michael J. Flynn	Cost-efficient high-radix division.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
16	Weining Hao, Martin Radetzki	A data traffic efficient H.264 deblocking IP.	ISCAS	2008	DBLP DOI BibTeX RDF
16	Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz	ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.	DFT	2008	DBLP DOI BibTeX RDF
16	Rui Zhang, Pallav Gupta, Lin Zhong 0001, Niraj K. Jha	Threshold network synthesis and optimization and its application to nanotechnologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
16	Sourabh Saluja, Anshul Kumar	Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Malcolm Taylor, Chi-En Daniel Yin, Min Wu, Gang Qu 0001	A Hardware-Assisted Data Hiding Based Approach in Building High-Performance Trusted Computing Systems.	HOST	2008	DBLP DOI BibTeX RDF
14	Leonid Bolotnyy, Gabriel Robins	Physically Unclonable Function-Based Security and Privacy in RFID Systems.	PerCom	2007	DBLP DOI BibTeX RDF
14	Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu	Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Khaled R. Heloue, Navid Azizi, Farid N. Najm	Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation.	DAC	2007	DBLP DOI BibTeX RDF
14	Heinz Mattes, Claus Dworski, Sebastian Sattler	Controlled Sine Wave Fitting for ADC Test.	ITC	2004	DBLP DOI BibTeX RDF
10	Ahsan Shabbir, Sander Stuijk, Akash Kumar 0001, Bart D. Theelen, Bart Mesman, Henk Corporaal	A predictable communication assist.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	fpga's, communication, predictable, dma, ca, mp-soc
10	Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng	A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	H.264, MPEG, Video decoder
10	Azam Beg	Improving Nano-circuit Reliability Estimates by Using Neural Methods.	NanoNet	2009	DBLP DOI BibTeX RDF	probability of failure, nano-metric circuits, reliability model, neural network model, Reliability estimation
10	Yexin Zheng, Chao Huang	A novel Toffoli network synthesis algorithm for reversible logic.	ASP-DAC	2009	DBLP DOI BibTeX RDF
10	Mathieu Renauld, François-Xavier Standaert, Nicolas Veyrat-Charvillon	Algebraic Side-Channel Attacks on the AES: Why Time also Matters in DPA.	CHES	2009	DBLP DOI BibTeX RDF
10	Wooyoung Jang, David Z. Pan	An SDRAM-aware router for Networks-on-Chip.	DAC	2009	DBLP DOI BibTeX RDF	Networks-on-Chip, memory, flow control, router
10	Ke Xu 0014, Chiu-sing Choy	A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
10	Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching-Yeh Chen, Shao-Yi Chien, Liang-Gee Chen	Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.	IEEE Trans. Circuits Syst. Video Technol.	2008	DBLP DOI BibTeX RDF
10	Reeba Korah, J. Raja Paul Perinbam	FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	pipelining, H.264, quantization, integer transform
10	Chun-Lung Hsu, Yu-Sheng Huang	A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter
10	Yi-Hau Chen, Shao-Yi Chien, Ching-Yeh Chen, Yu-Wen Huang, Liang-Gee Chen	Analysis and Hardware Architecture Design of Global Motion Estimation.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	MPEG-4 advanced simple profile, Mosaic, Gradient descent, Global motion estimation, Sprites
10	Martin Hell, Thomas Johansson 0001, Alexander Maximov, Willi Meier	The Grain Family of Stream Ciphers.	The eSTREAM Finalists	2008	DBLP DOI BibTeX RDF
10	Kavallur Gopi Smitha, A. Prasad Vinod 0001	A reconfigurable low complexity architecture for channel adaptation in cognitive radio.	PIMRC	2008	DBLP DOI BibTeX RDF
10	Tejaswi Gowda, Sarma B. K. Vrudhula	Decomposition based approach for synthesis of multi-level threshold logic circuits.	ASP-DAC	2008	DBLP DOI BibTeX RDF
10	Ruchika Verma, Ali Akoglu	A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation.	IPDPS	2008	DBLP DOI BibTeX RDF
10	Gregor Papa, Tomasz Garbolino, Franc Novak	Deterministic Test Pattern Generator Design.	EvoWorkshops	2008	DBLP DOI BibTeX RDF
10	Nicolas T. Courtois, Gregory V. Bard, David A. Wagner 0001	Algebraic and Slide Attacks on KeeLoq.	FSE	2008	DBLP DOI BibTeX RDF	unbalanced Feistel ciphers, Gröbner bases, KeeLoq, block ciphers, SAT solvers, algebraic cryptanalysis, slide attacks
10	Tsung-Han Tsai 0001, Yu-Nan Pan	High Efficiency Architecture of Fast Block Motion Estimation with Real-Time QFHD on H.264 Video Coding.	ISM	2008	DBLP DOI BibTeX RDF