Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
74 | Minoru Watanabe, Fuminori Kobayashi |
A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1214-1217, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
72 | Mao Nakajima, Daisaku Seto, Minoru Watanabe |
A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-6, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
69 | Shinichi Kato, Minoru Watanabe |
Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 139-148, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
68 | Minoru Watanabe, Fuminori Kobayashi |
A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 268-273, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Minoru Watanabe, Fuminori Kobayashi |
An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Daisaku Seto, Minoru Watanabe |
An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 117-118, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Daisaku Seto, Minoru Watanabe |
Analysis of retention time under multi-configuration on a DORGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 131-134, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Minoru Watanabe, Fuminori Kobayashi |
An Improved Dynamic Optically Reconfigurable Gate Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 136-141, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Myung Hoon Sunwoo, Seong Keun Oh |
A Multiplierless 2-D Convolver Chip for Real-Time Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 38(1), pp. 63-71, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
image processing, VLSI design, VLSI architecture, convolution, multiplier, digital filter |
35 | Hussain Al-Asaad, John P. Hayes |
Logic Design Validation via Simulation and Automatic Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(6), pp. 575-589, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
test generation, logic design, fault simulation, error modeling, design validation |
35 | Thomas W. Williams |
Testing in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 5-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Fei Li 0003, Lei He 0001, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy |
High-level area and power-up current estimation considering rich cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 899-904, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Rui Zhang, Niraj K. Jha |
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 317-322, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi |
272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ERSA ![In: Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, pp. 259-264, 2007, CSREA Press, 1-60132-026-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
30 | Minoru Watanabe, Fuminori Kobayashi |
A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 124-125, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip |
30 | Minoru Watanabe |
An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2007 IEEE International SOC Conference, Tampere, Finland, November 19-21, 2007, pp. 75-78, 2007, IEEE, 978-1-4244-1592-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Minoru Watanabe, Fuminori Kobayashi |
A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 108-109, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | James Donald, Niraj K. Jha |
Reversible logic synthesis with Fredkin and Peres gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(1), pp. 2:1-2:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Quantum computing, reversible logic |
27 | Mao Nakajima, Minoru Watanabe |
Fast Optical Reconfiguration of a Nine-Context DORGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 123-132, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Shinya Kubota, Minoru Watanabe |
A nine-context programmable optically reconfigurable gate array with semiconductor lasers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 269-274, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
holographic memory, optically reconfigurable gate arrays, field programmable gate arrays |
27 | Minoru Watanabe, Fuminori Kobayashi |
Power consumption advantage of a dynamic optically reconfigurable gate array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Fredkin/Toffoli Templates for Reversible Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 256-261, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Lihui Ni, Zhijin Guan, Wenying Zhu |
A General Method of Constructing the Reversible Full-Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IITSI ![In: Third International Symposium on Intelligent Information Technology and Security Informatics, IITSI 2010, Jinggangshan, China, April 2-4, 2010, pp. 109-113, 2010, IEEE Computer Society, 978-0-7695-4020-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reversible full-adder, reversible gates, gate count, garbage outputs |
27 | Akhilesh Tyagi |
A Reduced-Area Scheme for Carry-Select Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(10), pp. 1163-1170, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders |
26 | Yu-Kun Lin, Chun-Wei Ku, De-Wei Li, Tian-Sheuan Chang |
A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 19(3), pp. 432-436, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Akashi Satoh |
ASIC hardware implementations for 512-bit hash function Whirlpool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2917-2920, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Shuguang Zhao, Licheng Jiao |
Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Genet. Program. Evolvable Mach. ![In: Genet. Program. Evolvable Mach. 7(3), pp. 195-210, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Evolutionary design of circuits, Knowledge discovery, Evolvable hardware, Multi-objective genetic algorithm, Adaptive genetic algorithm |
24 | Kavel M. Büyüksahin, Farid N. Najm |
High-level area estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 271-274, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
boolean networks, area estimation |
24 | Hussain Al-Asaad, John P. Hayes |
Design verification via simulation and automatic test pattern generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 174-180, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
test generation, logic simulation, Design verification, error models |
23 | Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi |
A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-7, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi |
An optically differential reconfigurable gate array with a holographic memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Minoru Watanabe, Fuminori Kobayashi |
Optically Reconfigurable Gate Arrays vs. ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1164-1167, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Arash Reyhani-Masoleh, M. Anwar Hasan |
Efficient digit-serial normal basis multipliers over binary extension fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(3), pp. 575-592, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
security, finite field, normal basis, Digit-serial multiplier |
23 | Fei Li 0003, Lei He 0001, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy |
High Level Area and Current Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 259-268, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Jen-Chuan Chih, Kun-Lung Chen, Sau-Gee Chen |
A CORDIC processor with efficient table-lookup schemes for rotations and on-line scale factor compensations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3315-3318, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Von-Kyoung Kim, Tom Chen 0001, Mick Tegethoff |
Fault Coverage Estimation for Early Stage of VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 105-108, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Steve Thakur |
An optimization of the addition gate count in Plonkish circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 1264, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
21 | John Burke, Biswajit Basu, Ciaran McGoldrick |
Reduced Gate Count for Quantum State Preparation of 2D Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QCE ![In: IEEE International Conference on Quantum Computing and Engineering, QCE 2023, Bellevue, WA, USA, September 17-22, 2023, pp. 344-345, 2023, IEEE, 979-8-3503-4323-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani |
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 53rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2023, Matsue, Japan, May 22-24, 2023, pp. 153-157, 2023, IEEE, 978-1-6654-6416-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Pritam Bhattacharjee, G. Naveen Goud, Vipin K. Singh, Vijay P. Yadav, Abir J. Mondal, Alak Majumder |
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RADIOELEKTRONIKA ![In: 33rd International Conference Radioelektronika, RADIOELEKTRONIKA 2023, Pardubice, Czech Republic, April 19-20, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-9834-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Korbinian Staudacher, Tobias Guggemos, Sophia Grundner-Culemann, Wolfgang Gehrke |
Reducing 2-QuBit Gate Count for ZX-Calculus based Quantum Circuit Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QPL ![In: Proceedings 19th International Conference on Quantum Physics and Logic, QPL 2022, Wolfson College, Oxford, UK, 27 June - 1 July 2022., pp. 29-45, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Sunyeop Kim, Insung Kim, Seonggyeom Kim, Seokhie Hong |
Toffoli gate count Optimized Space-Efficient Quantum Circuit for Binary Field Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1095, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
21 | Marcus Dansarie |
sboxgates: A program for finding low gate count implementations of S-boxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Open Source Softw. ![In: J. Open Source Softw. 6(62), pp. 2946, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Ian van Hoof |
Space-efficient quantum multiplication polynomials for binary finite fields with sub-quadratoc Toffoli gate count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Quantum Inf. Comput. ![In: Quantum Inf. Comput. 20(9&10), pp. 721-735, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Iggy van Hoof |
Space-efficient quantum multiplication of polynomials for binary finite fields with sub-quadratic Toffoli gate count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1910.02849, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Cupjin Huang, Michael Newman, Mario Szegedy |
Explicit lower bounds on strong simulation of quantum circuits in terms of $T$-gate count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.04764, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Iggy van Hoof |
Space-efficient quantum multiplication of polynomials for binary finite fields with sub-quadratic Toffoli gate count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2019, pp. 1170, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, W. Shu, Joseph S. Chang, Bah-Hwee Gwee |
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka |
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Sungkyung Park 0001, Chester Sungchung Park |
Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(9), pp. 1750132:1-1750132:24, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Shane Kepley, Rainer Steinwandt |
Quantum circuits for 2n-multiplication with subquadratic gate count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Quantum Inf. Process. ![In: Quantum Inf. Process. 14(7), pp. 2373-2386, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Katherine L. Brown, Anmer Daskin, Sabre Kais, Jonathan P. Dowling |
Reducing the number of ancilla qubits and the gate count required for creating large controlled operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Quantum Inf. Process. ![In: Quantum Inf. Process. 14(3), pp. 891-899, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Takashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani |
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 97-D(9), pp. 2253-2261, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu |
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11), pp. 2600-2610, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao |
A novel low gate-count serializer topology with Multiplexer-Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 245-248, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | José Sarmento, John T. Stonick |
A minimal-gate-count fully digital frequency-tracking oversampling CDR circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 2099-2102, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Lei Chen, Shinji Kimura |
Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12), pp. 3111-3118, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Matthew Kwan |
Reducing the Gate Count of Bitslice DES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2000, pp. 51, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
20 | Jae Hyun Baek, Myung Hoon Sunwoo |
New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 915-920, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Jaehyun Baek, Myung Hoon Sunwoo |
Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Jang Woong Park, Jae Hyun Baek, Myung Hoon Sunwoo |
Enhanced Degree Computationless Modified Euclid's Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 305-308, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Wei-Kai Chan, Shao-Yi Chien |
Subword Parallel Architecture for Connected Component Labeling and Morphological Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 936-939, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Elena Trichina, Tymur Korkishko |
Secure AES Hardware Module for Resource Constrained Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESAS ![In: Security in Ad-hoc and Sensor Networks, First European Workshop, ESAS 2004, Heidelberg, Germany, August 6, 2004, Revised Selected Papers, pp. 215-230, 2004, Springer, 3-540-24396-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Siddika Berna Örs, Ahmet Dervisoglu |
Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1402-1405, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry |
Low-Power Design of Finite Field Multipliers for Wireless Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 19-25, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
architecture, low power, finite fields, multiplier |
20 | Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee |
RSYN: a system for automated synthesis of reliable multilevel circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(2), pp. 186-195, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Jimson Mathew, Hafizur Rahaman 0001, Babita R. Jose, Dhiraj K. Pradhan |
Design of Reversible Finite Field Arithmetic Circuits with Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 453-459, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Minoru Watanabe, Naoki Yamaguchi |
An Acceleration and Optimization Method for Optical Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 607-612, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Pallav Gupta, Abhinav Agrawal 0002, Niraj K. Jha |
An Algorithm for Synthesis of Reversible Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2317-2330, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller |
Synthesis of Fredkin-Toffoli reversible networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 765-769, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Lu Xiao 0003, Howard M. Heys |
Hardware Design and Analysisof Block Cipher Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2002, 5th International Conference Seoul, Korea, November 28-29, 2002, Revised Papers, pp. 164-181, 2002, Springer, 3-540-00716-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Arash Reyhani-Masoleh, M. Anwar Hasan |
Efficient digit-serial normal basis multipliers over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 781-784, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Eric M. Schwarz, Michael J. Flynn |
Cost-efficient high-radix division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(4), pp. 293-305, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
16 | Weining Hao, Martin Radetzki |
A data traffic efficient H.264 deblocking IP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3430-3433, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz |
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 385-393, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Rui Zhang, Pallav Gupta, Lin Zhong 0001, Niraj K. Jha |
Threshold network synthesis and optimization and its application to nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), pp. 107-118, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Sourabh Saluja, Anshul Kumar |
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 761-764, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Malcolm Taylor, Chi-En Daniel Yin, Min Wu, Gang Qu 0001 |
A Hardware-Assisted Data Hiding Based Approach in Building High-Performance Trusted Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings, pp. 93-96, 2008, IEEE Computer Society, 978-1-4244-2401-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Leonid Bolotnyy, Gabriel Robins |
Physically Unclonable Function-Based Security and Privacy in RFID Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom ![In: Fifth Annual IEEE International Conference on Pervasive Computing and Communications (PerCom 2007), 19-23 March 2007, White Plains, New York, USA, pp. 211-220, 2007, IEEE Computer Society, 978-0-7695-2787-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu |
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3135-3138, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Khaled R. Heloue, Navid Azizi, Farid N. Najm |
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 93-98, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Heinz Mattes, Claus Dworski, Sebastian Sattler |
Controlled Sine Wave Fitting for ADC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 963-971, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
10 | Ahsan Shabbir, Sander Stuijk, Akash Kumar 0001, Bart D. Theelen, Bart Mesman, Henk Corporaal |
A predictable communication assist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 97-98, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga's, communication, predictable, dma, ca, mp-soc |
10 | Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng |
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(1), pp. 17:1-17:17, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
H.264, MPEG, Video decoder |
10 | Azam Beg |
Improving Nano-circuit Reliability Estimates by Using Neural Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 270-275, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
probability of failure, nano-metric circuits, reliability model, neural network model, Reliability estimation |
10 | Yexin Zheng, Chao Huang |
A novel Toffoli network synthesis algorithm for reversible logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 739-744, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Mathieu Renauld, François-Xavier Standaert, Nicolas Veyrat-Charvillon |
Algebraic Side-Channel Attacks on the AES: Why Time also Matters in DPA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings, pp. 97-111, 2009, Springer, 978-3-642-04137-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Wooyoung Jang, David Z. Pan |
An SDRAM-aware router for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 800-805, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Networks-on-Chip, memory, flow control, router |
10 | Ke Xu 0014, Chiu-sing Choy |
A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 18(3), pp. 363-374, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching-Yeh Chen, Shao-Yi Chien, Liang-Gee Chen |
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 18(1), pp. 98-109, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Reeba Korah, J. Raja Paul Perinbam |
FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 261-269, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pipelining, H.264, quantization, integer transform |
10 | Chun-Lung Hsu, Yu-Sheng Huang |
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 211-229, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter |
10 | Yi-Hau Chen, Shao-Yi Chien, Ching-Yeh Chen, Yu-Wen Huang, Liang-Gee Chen |
Analysis and Hardware Architecture Design of Global Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(3), pp. 285-300, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MPEG-4 advanced simple profile, Mosaic, Gradient descent, Global motion estimation, Sprites |
10 | Martin Hell, Thomas Johansson 0001, Alexander Maximov, Willi Meier |
The Grain Family of Stream Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
The eSTREAM Finalists ![In: New Stream Cipher Designs - The eSTREAM Finalists, pp. 179-190, 2008, Springer, 978-3-540-68350-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Kavallur Gopi Smitha, A. Prasad Vinod 0001 |
A reconfigurable low complexity architecture for channel adaptation in cognitive radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PIMRC ![In: Proceedings of the IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2008, 15-18 September 2008, Cannes, French Riviera, France, pp. 1-5, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Tejaswi Gowda, Sarma B. K. Vrudhula |
Decomposition based approach for synthesis of multi-level threshold logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 125-130, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Ruchika Verma, Ali Akoglu |
A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Gregor Papa, Tomasz Garbolino, Franc Novak |
Deterministic Test Pattern Generator Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 204-213, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Nicolas T. Courtois, Gregory V. Bard, David A. Wagner 0001 |
Algebraic and Slide Attacks on KeeLoq. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSE ![In: Fast Software Encryption, 15th International Workshop, FSE 2008, Lausanne, Switzerland, February 10-13, 2008, Revised Selected Papers, pp. 97-115, 2008, Springer, 978-3-540-71038-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
unbalanced Feistel ciphers, Gröbner bases, KeeLoq, block ciphers, SAT solvers, algebraic cryptanalysis, slide attacks |
10 | Tsung-Han Tsai 0001, Yu-Nan Pan |
High Efficiency Architecture of Fast Block Motion Estimation with Real-Time QFHD on H.264 Video Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISM ![In: Tenth IEEE International Symposium on Multimedia (ISM2008), December 15-17, 2008, Berkeley, California, USA, pp. 124-129, 2008, IEEE Computer Society, 978-0-7695-3454-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|