Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Fei Hu, Vishwani D. Agrawal |
Input-specific dynamic power optimization for VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 232-237, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic power optimization, glitch reduction, input specific |
86 | Scott Cromar, Jaeho Lee, Deming Chen |
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 838-843, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
glitch power, FPGA, high-level synthesis, power reduction |
86 | Fei Hu, Vishwani D. Agrawal |
Dual-transition glitch filtering in probabilistic waveform power estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 357-360, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-transition probability, dynamic power estimation, glitch filtering, probabilistic waveform simulation |
80 | Quang Dinh, Deming Chen, Martin D. F. Wong |
A routing approach to reduce glitches in low power FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 99-106, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
glitch reduction, path balancing, fpgas, routing, low power |
62 | Yuanlin Lu, Vishwani D. Agrawal |
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 527-532, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
62 | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
A power optimization method considering glitch reduction by gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 221-226, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
52 | David Naccache, Phong Q. Nguyen, Michael Tunstall, Claire Whelan |
Experimenting with Faults, Lattices and the DSA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Public Key Cryptography ![In: Public Key Cryptography - PKC 2005, 8th International Workshop on Theory and Practice in Public Key Cryptography, Les Diablerets, Switzerland, January 23-26, 2005, Proceedings, pp. 16-28, 2005, Springer, 3-540-24454-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
glitch attacks, fault injection, lattice reduction, DSA |
48 | Biwei Liu, Shuming Chen, Hu Xiao |
Analysis of Glitch Reconvergence in Combinational Logic SER Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Second Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, Malaysia, May 13-15, 2008, pp. 1015-1020, 2008, IEEE Computer Society, 978-0-7695-3136-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Reconvergence, SER esitmation, SET |
48 | Yijun Zhou, Jiren Yuan |
An 8-Bit, 100-MHz low glitch interpolation DAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 116-119, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di |
Glitch-free design for multi-threshold CMOS NCL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 215-220, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic |
43 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 |
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 167-172, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling |
42 | Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh |
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings, pp. 189-204, 2009, Springer, 978-3-642-04137-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Benoit Catteau, Pieter Rombouts, Ludo Weyten |
A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1477-1480, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Tao Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault tolerant clockless wave pipeline design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 350-356, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability |
42 | N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das |
Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 518-523, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Daniel Lammers, Nicolai Müller, Amir Moradi 0001 |
Glitch-free is not Enough - Revisiting Glitch-Extended Probing Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 35, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
39 | Bahram Rashidi |
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 85, pp. 20-26, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
39 | Patricia S. Gracia |
Las consecuencias del glitch en el entorno virtual interactivo(The consequences of the glitch in the interactive virtual environment). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoSECivi ![In: Proceedings of the VI Congreso de la Sociedad Española para las Ciencias del Videojuego, On-line, October 7-8, 2020., pp. 36-46, 2020, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
39 | Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad |
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10), pp. 2696-2707, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
39 | Rudolfo Quintas |
Glitch Delighter: Lighter's Flame Base Hyper-Instrument for Glitch Music in Burning The Sound Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NIME ![In: 10th International Conference on New Interfaces for Musical Expression, NIME 2010, Sydney, Australia, June 15-18, 2010, pp. 212-216, 2010, nime.org. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
39 | Daisuke Suzuki, Koichi Shimizu |
The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems, CHES 2010, 12th International Workshop, Santa Barbara, CA, USA, August 17-20, 2010. Proceedings, pp. 366-382, 2010, Springer, 978-3-642-15030-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
38 | Minjin Zhang, Huawei Li 0001, Xiaowei Li 0001 |
Static Crosstalk Noise Analysis with Transition Map. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 462-465, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
static noise analysis, crosstalk, glitch |
34 | Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang |
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 10-15, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Ahmed Sayed, Hussain Al-Asaad |
A New Statistical Approach for Glitch Estimation in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1641-1644, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
42% power savings through glitch-reducing clocking strategy in a hearing aid application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Yuanlin Lu, Vishwani D. Agrawal |
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 217-226, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Glitch-free discretely programmable clock generation on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1839-1842, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Glitch power minimization by selective gate freezing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(3), pp. 287-298, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Glitch Power Minimization by Gate Freezing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 163-167, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Rajesh Garg, Sunil P. Khatri |
Efficient analytical determination of the SEU-induced pulse shape. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 461-467, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas |
Probabilistic gate-level power estimation using a novel waveform set method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 37-42, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
probabilistic power estimation, probability waveform, transition density, combinational logic, gate-level |
28 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 318-323, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier |
Modeling of Crosstalk Fault in Defective Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 340-349, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
defect-based-crosstalk fault model, signal integrity losses, aggres-sor-victim, ABCD-model, crosstalk-hazards |
28 | Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier |
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 336-344, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
defective interconnects, defect’s severity, fault model, crosstalk, bridging fault |
28 | Seong-Min Ha, Tae-Kyu Nam, Kwang S. Yoon |
An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 355-358, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
Variable Input Delay CMOS Logic for Low Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 598-605, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Sarah Thompson, Alan Mycroft |
Abstract Interpretation of Combinational Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 11th International Symposium, SAS 2004, Verona, Italy, August 26-28, 2004, Proceedings, pp. 181-196, 2004, Springer, 3-540-22791-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Hyuen-Hee Bae, Jin-Sik Yoon, Myung-Jin Lee, Eun-Seok Shin, Seung-Hoon Lee |
A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 869-872, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | J. H. Wang |
Event-overlapping processing in current waveform simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 226-229, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu 0001, Byron Krauter |
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 186-189, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
glitch propagation, noise analysis, effective capacitance |
24 | Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim |
Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 61-68, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave |
24 | Joseph N. Kozhaya, Farid N. Najm |
Accurate power estimation for large sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 488-493, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
power vector set, simulation, VLSI, CAD, dynamic, power, correlation, estimation, Monte Carlo, compaction, sequential, glitch |
24 | Daniel Brand, Chandramouli Visweswariah |
Inaccuracies in power estimation during logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 388-394, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
glitch power, simulation, logic synthesis, power estimation, power optimization |
24 | Thomas J. Chaney |
Comments on "A Note on Synchronizer or Interlock Maloperation". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(10), pp. 802-804, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
flip-flop metastability, interrupt failure, Arbiter, glitch, asynchronous interactions, synchronizer failure |
24 | George R. Couranz, Donald F. Wann |
Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(6), pp. 604-616, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Asynchronous fundamental mode input changes, binary switching time, flip-flop metastable region, interrupt failure, probabilistic behavior of flip-flops, glitch, asynchronous interactions, synchronizer failures |
20 | Talal Bonny, Farah AlMutairi, Wafaa Al Nassan |
A novel clock-glitch-attack-proof image encryption algorithm implemented on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 83(7), pp. 18881-18906, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Tom Dooney, Lyana Curier, Daniel Stanley Tan, Melissa Lopez, Chris Van Den Broeck, Stefano Bromuri |
cDVGAN: One Flexible Model for Multi-class Gravitational Wave Signal and Glitch Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.16356, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Amund Askeland, Svetla Nikova, Ventzislav Nikov |
Who Watches the Watchers: Attacking Glitch Detection Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(1), pp. 157-179, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Marc Schink, Alexander Wagner, Felix Oberhansl, Stefan Köckeis, Emanuele Strieder, Sven Freud, Dominik Klein 0001 |
Unlock the Door to my Secrets, but don't Forget to Glitch A comprehensive analysis of flash erase suppression attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2), pp. 88-129, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Amélie Marotta, Ronan Lashermes, Guillaume Bouffard, Olivier Sentieys, Rachid Dafali |
Characterizing and Modeling Synchronous Clock-Glitch Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COSADE ![In: Constructive Side-Channel Analysis and Secure Design - 15th International Workshop, COSADE 2024, Gardanne, France, April 9-10, 2024, Proceedings, pp. 3-21, 2024, Springer, 978-3-031-57542-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Osman Tayfun Biskin, Ismail Kirbas, Ali Çelik |
A fast and time-efficient glitch classification method: A deep learning-based visual feature extractor for machine learning algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Astron. Comput. ![In: Astron. Comput. 42, pp. 100683, January 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Zhixi Cai, Shreya Ghosh 0001, Abhinav Dhall, Tom Gedeon, Kalin Stefanov, Munawar Hayat |
Glitch in the matrix: A large scale benchmark for content driven audio-visual forgery detection and localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Vis. Image Underst. ![In: Comput. Vis. Image Underst. 236, pp. 103818, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Karthikeyan Muthamizh Vithagan, Vignesh Sundaresha, Janakiraman Viraraghavan |
Geometric Programming Approach to Glitch Minimization via Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6), pp. 1988-2001, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Zhixi Cai, Shreya Ghosh 0001, Abhinav Dhall, Tom Gedeon, Kalin Stefanov, Munawar Hayat |
"Glitch in the Matrix!": A Large Scale Benchmark for Content Driven Audio-Visual Forgery Detection and Localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2305.01979, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi |
Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.06932, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Giovanni Monea, Maxime Peyrard, Martin Josifoski, Vishrav Chaudhary, Jason Eisner, Emre Kiciman, Hamid Palangi, Barun Patra, Robert West 0001 |
A Glitch in the Matrix? Locating and Detecting Language Model Grounding with Fakepedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2312.02073, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Jamal Knight, Andrew Johnston, Adam Berry |
Artistic control over the glitch in AI-generated motion capture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.08576, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Nuno Saavedra, João Gonçalves, Miguel Henriques, João F. Ferreira 0001, Alexandra Mendes |
Polyglot Code Smell Detection for Infrastructure as Code with GLITCH. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.09458, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Fu Yao, Hua Chen, Yongzhuang Wei, Enes Pasalic, Feng Zhou, Limin Fan |
Optimizing AES Threshold Implementation under the Glitch-Extended Probing Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 1856, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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20 | Amund Askeland, Svetla Nikova, Ventzislav Nikov |
Who Watches the Watchers: Attacking Glitch Detection Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 1647, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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20 | Weifeng Liu, Tianxiao Zhang, Hanchen Zhang, Hualian Tang, Li Zhang |
A glitch energy reduction method with low complexity dynamic element matching for data converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(5), pp. 20220529, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Mickey Mengting Zhang, Yu Shen, Ihab Salah Ali Mohamed |
Visualizing Ocean Fragility: Glitch Art and Social Media in Marine Conservation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (45) ![In: HCI International 2023 Posters - 25th International Conference on Human-Computer Interaction, HCII 2023, Copenhagen, Denmark, July 23-28, 2023, Proceedings, Part III, pp. 554-561, 2023, Springer, 978-3-031-35997-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri |
Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CARDIS ![In: Smart Card Research and Advanced Applications - 22nd International Conference, CARDIS 2023, Amsterdam, The Netherlands, November 14-16, 2023, Revised Selected Papers, pp. 3-22, 2023, Springer, 978-3-031-54408-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Xhani Marvin Saß, Richard Mitev, Ahmad-Reza Sadeghi |
Oops..! I Glitched It Again! How to Multi-Glitch the Glitching-Protections on ARM TrustZone-M. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Security Symposium ![In: 32nd USENIX Security Symposium, USENIX Security 2023, Anaheim, CA, USA, August 9-11, 2023, pp. 6239-6256, 2023, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
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20 | Xiaoyun Liang 0006, Jiayi Qi, Yongqiang Gao, Chao Peng, Ping Yang |
AG3: Automated Game GUI Text Glitch Detection Based on Computer Vision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESEC/SIGSOFT FSE ![In: Proceedings of the 31st ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering, ESEC/FSE 2023, San Francisco, CA, USA, December 3-9, 2023, pp. 1879-1890, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Noriki Amano |
Glitch Art Generation and Performance Using Musical Live Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ArtsIT (2) ![In: ArtsIT, Interactivity and Game Creation - 12th EAI International Conference, ArtsIT 2023, São Paulo, Brazil, November 27-29, 2023, Proceedings, Part II, pp. 175-185, 2023, Springer, 978-3-031-55311-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Nuno Saavedra, João Gonçalves, Miguel Henriques, João F. Ferreira 0001, Alexandra Mendes |
Polyglot Code Smell Detection for Infrastructure as Code with GLITCH. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: 38th IEEE/ACM International Conference on Automated Software Engineering, ASE 2023, Luxembourg, September 11-15, 2023, pp. 2042-2045, 2023, IEEE, 979-8-3503-2996-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa |
Security Evaluation of Glitch Based Authentication Function for Edge AI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCCE ![In: 12th IEEE Global Conference on Consumer Electronics, GCCE 2023, Nara, Japan, October 10-13, 2023, pp. 790-791, 2023, IEEE, 979-8-3503-4018-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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20 | Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu |
Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(13), pp. 2250231:1-2250231:17, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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20 | Jianqi Yan, Alex P. Leung, David C. Y. Hui |
On Improving the Performance of Glitch Classification for Gravitational Wave Detection by using Generative Adversarial Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.04001, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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20 | Nuno Saavedra, João F. Ferreira 0001 |
GLITCH: an Intermediate-Representation-Based Security Analysis for Infrastructure as Code Scripts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.14371, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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20 | Benedikte Wallace, Charles P. Martin |
Embodying the Glitch: Perspectives on Generative AI in Dance Practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2210.09291, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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20 | Pablo Morales-Álvarez, Pablo Ruiz 0002, Scott Coughlin, Rafael Molina 0001, Aggelos K. Katsaggelos |
Scalable Variational Gaussian Processes for Crowdsourcing: Glitch Detection in LIGO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 44(3), pp. 1534-1551, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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20 | Anuradha Chathuranga Ranasinghe, Sabih H. Gerez |
Gate-Level RTL Description of the Glitch Optimized Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2022 |
DOI RDF |
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20 | Tahmida Islam, Junkyu Kim, Chris H. Kim, David Tipple, Michael Nelson, Robert Jin, Anis Jarrar |
A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 2-1, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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20 | Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray |
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 146-147, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Aaron Juarez |
Glitch Serendipity: Alternative Information Seeking that Leads to Discovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Creativity & Cognition ![In: C&C '22: Creativity and Cognition, Venice, Italy, June 20 - 23, 2022, pp. 684-687, 2022, ACM, 978-1-4503-9327-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Nuno Saavedra, João F. Ferreira 0001 |
GLITCH: Automated Polyglot Security Smell Detection in Infrastructure as Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: 37th IEEE/ACM International Conference on Automated Software Engineering, ASE 2022, Rochester, MI, USA, October 10-14, 2022, pp. 47:1-47:12, 2022, ACM, 978-1-4503-9475-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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20 | Hung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo |
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(10), pp. 3145-3156, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Hossein Ghasemian, Amin Bahrami, Ebrahim Abiri, Mohammad Reza Salehi |
A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(6), pp. 2982-3006, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Xiaoke Tang, Xu Zhao, Ang Hu, Dongsheng Liu, Zirui Jin |
A 433/2400 MHz dual-band frequency synthesizer with glitch-free phase-interpolated frequency divider and hybrid post-synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 116, pp. 105158, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Robert Buhren, Hans Niklas Jacob, Thilo Krachenfels, Jean-Pierre Seifert |
One Glitch to Rule Them All: Fault Injection Attacks Against AMD's Secure Encrypted Virtualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2108.04575, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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20 | Reymond Mesuga, Brian James Bayanay |
On the Efficiency of Various Deep Transfer Learning Models in Glitch Waveform Detection in Gravitational-Wave Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2107.01863, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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20 | Jürgen Maier 0002, Daniel Öhlinger, Ulrich Schmid 0001, Matthias Függer, Thomas Nowak |
A Composable Glitch-Aware Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.10966, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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20 | Wenye Liu, Chip-Hong Chang, Fan Zhang 0010 |
Stealthy and Robust Glitch Injection Attack on Deep Learning Accelerator for Target With Variational Viewpoint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Forensics Secur. ![In: IEEE Trans. Inf. Forensics Secur. 16, pp. 1928-1942, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Gaëtan Cassiers, François-Xavier Standaert |
Provably Secure Hardware Masking in the Transition- and Glitch-Robust Probing Model: Better Safe than Sorry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(2), pp. 136-158, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Robert Buhren, Hans Niklas Jacob, Thilo Krachenfels, Jean-Pierre Seifert |
One Glitch to Rule Them All: Fault Injection Attacks Against AMD's Secure Encrypted Virtualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15 - 19, 2021, pp. 2875-2889, 2021, ACM, 978-1-4503-8454-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Stan Verbeek, Tom Oomen, Arnfinn Aas Eielsen |
Glitch Compensation for a Digital-to-Analogue Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACC ![In: 2021 American Control Conference, ACC 2021, New Orleans, LA, USA, May 25-28, 2021, pp. 751-757, 2021, IEEE, 978-1-6654-4197-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Takumi Hayashi, Hiroshi Fujimoto, Yoshihiro Isaoka, Yuki Terada |
Negative Quadrant Glitch Suppression of Ball-screw-driven Stage by Initial Value Compensation with Additional Input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMC ![In: 17th IEEE International Conference on Advanced Motion Control, AMC 2021, Padova, Italy, February 18-20, 2022, pp. 195-200, 2021, IEEE, 978-1-7281-7711-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa |
Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDCS ![In: 4th International Symposium on Devices, Circuits and Systems, ISDCS 2021, Higashi-Hiroshima, Japan, March 3-5, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1478-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Joseph Gilling |
Haunted by the Glitch: Technological Malfunction - Critiquing the Media of Innovation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARTECH ![In: ARTECH 2021: 10th International Conference on Digital and Interactive Arts, Aveiro, Portugal, October 13 - 15, 2021, pp. 23:1-23:7, 2021, ACM, 978-1-4503-8420-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Jürgen Maier 0002, Daniel Öhlinger, Ulrich Schmid 0001, Matthias Függer, Thomas Nowak |
A Composable Glitch-Aware Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021., pp. 147-154, 2021, ACM, 978-1-4503-8393-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Li Ni, Pengjun Wang, Yuejun Zhang, Jia Chen, Liwei Li 0004, Huihong Zhang |
A Reliable Multi-information Entropy Glitch PUF Using Schmitt Trigger Sampling Method for IoT Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu |
Formal Evaluation and Construction of Glitch-resistant Masked Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021, Tysons Corner, VA, USA, December 12-15, 2021, pp. 304-313, 2021, IEEE, 978-1-6654-1357-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Yusuke Nozaki, Masaya Yoshikawa |
Neural Network Based Glitch Physically Unclonable Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UEMCON ![In: 12th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, UEMCON 2021, New York, NY, USA, December 1-4, 2021, pp. 160-164, 2021, IEEE, 978-1-6654-0690-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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20 | Anuradha Chathuranga Ranasinghe, Sabih H. Gerez |
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(9), pp. 2028-2041, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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20 | Stephanie T. Jones, Natalie Melo |
'Anti-blackness is no glitch': the need for critical conversations within computer science education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
XRDS ![In: XRDS 27(2), pp. 42-46, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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20 | Dorian Amiet, Lukas Leuenberger, Andreas Curiger, Paul Zbinden |
FPGA-based SPHINCS+ Implementations: Mind the Glitch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 23rd Euromicro Conference on Digital System Design, DSD 2020, Kranj, Slovenia, August 26-28, 2020, pp. 229-237, 2020, IEEE, 978-1-7281-9535-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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20 | Steffen Zeidler 0001, Oliver Schrape, Anselm Breitenreiter, Milos Krstic |
A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 23rd Euromicro Conference on Digital System Design, DSD 2020, Kranj, Slovenia, August 26-28, 2020, pp. 11-15, 2020, IEEE, 978-1-7281-9535-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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20 | Yusuke Nozaki, Masaya Yoshikawa |
Unrolled PRINCE Cipher based Glitch Physically Unclonable Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISS ![In: ICISS 2020: The 3rd International Conference on Information Science and System, Cambridge, UK, March 19-22, 2020, pp. 3-7, 2020, ACM, 978-1-4503-7725-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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