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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4224 occurrences of 1958 keywords
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Results
Found 5158 publication records. Showing 5158 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
92 | A. F. R. Brown |
Language Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 5(1), pp. 1-8, 1958. The full citation details ...](Pics/full.jpeg) |
1958 |
DBLP DOI BibTeX RDF |
|
78 | Julie Heiser, Doantam Phan, Maneesh Agrawala, Barbara Tversky, Pat Hanrahan |
Identification and validation of cognitive design principles for automated generation of assembly instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AVI ![In: Proceedings of the working conference on Advanced visual interfaces, AVI 2004, Gallipoli, Italy, May 25-28, 2004, pp. 311-319, 2004, ACM Press, 1-58113-867-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
assembly instructions, visual instructions, diagrams, design principles, spatial ability |
78 | A. P. Wim Böhm, John R. Gurd |
Iterative Instructions in the Manchester Dataflow Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(2), pp. 129-139, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Manchester Dataflow Computer, iterative instructions, program execution times, function unit array, hardware speedup curves, fine-grain instructions, parallel programming, parallel architectures, iterative methods, parallel machines, tokens, instruction sets, instruction sets, hardware configuration |
77 | Shay Gueron |
Intel's New AES Instructions for Enhanced Performance and Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSE ![In: Fast Software Encryption, 16th International Workshop, FSE 2009, Leuven, Belgium, February 22-25, 2009, Revised Selected Papers, pp. 51-66, 2009, Springer, 978-3-642-03316-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
new instructions set, computer architecture, Advanced Encryption Standard |
77 | Sumeet Kumar, Aneesh Aggarwal |
Self-checking instructions: reducing instruction redundancy for concurrent error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 64-73, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures |
74 | Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa |
Pack instruction generation for media pUsing multi-valued decision diagram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 154-159, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-valued decision diagram, SIMD instructions |
67 | Daniel Spelmezan, Mareike Jacobs, Anke Hilgers, Jan O. Borchers |
Tactile motion instructions for physical activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Proceedings of the 27th International Conference on Human Factors in Computing Systems, CHI 2009, Boston, MA, USA, April 4-9, 2009, pp. 2243-2252, 2009, ACM, 978-1-60558-246-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
real-time instructions, sports training, vibrotactile feedack, physical activities, motor skills |
63 | Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder |
Reducing code size with echo instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 84-94, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
code size optimization, echo instructions, compression |
61 | Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis |
Limitations of special-purpose instructions for similarity measurements in media SIMD extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 293-303, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
sub-word parallelism, similarity measurements, SIMD |
58 | Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy |
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 83-94, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy |
57 | Sangho Ha, Sangyong Han, Heunghwan Kim |
Partitioning a lenient parallel language into sequential threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 83-92, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
lenient parallel language, language partitioning, sequential threads, multithreaded architecture performance, large-scale parallel system, split-phase memory operations, fast context switching, multithreaded code quality, enhanced thread formation scheme, Id/sup -/, long latency instructions, multiple switches, generalized switch-and-merge, thread merging, redundant arc elimination, thread precedence relations, control instructions, DAVRID multithreaded architecture, simulation, graph theory, parallel architectures, graph partitioning, switching, merging, parallel languages, large-scale systems, program control structures, branch instructions |
56 | Jared Stark, Paul Racunas, Yale N. Patt |
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 34-43, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
instruction supply, superscalar processors, out-of-order execution |
55 | Sung-Kwan Kim, Sang Lyul Min, Rhan Ha |
Efficient worst case timing analysis of data caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 2nd IEEE Real-Time Technology and Applications Symposium, RTAS '96, Boston, MA, USA, June 10-12, 1996, pp. 230-240, 1996, IEEE Computer Society, 0-8186-7448-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block |
54 | Chia-Lin Yang, Barton Sano, Alvin R. Lebeck |
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(9), pp. 934-946, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
geometry pipeline, paired-single instructions, 3D graphics, superscalar processors, SIMD instructions |
53 | Enric Morancho, José María Llabería, Àngel Olivé |
Recovery Mechanism for Latency Misprediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 118-128, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
53 | Arvind Krishnaswamy, Rajiv Gupta 0001 |
Enhancing the performance of 16-bit code using augmenting instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03). San Diego, California, USA, June 11-13, 2003, pp. 254-264, 2003, ACM, 1-58113-647-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
16-bit thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, embedded processor, code size |
52 | Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou |
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 257-270, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Jingren Zhou, Kenneth A. Ross |
Implementing database operations using SIMD instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the 2002 ACM SIGMOD International Conference on Management of Data, Madison, Wisconsin, USA, June 3-6, 2002, pp. 145-156, 2002, ACM, 1-58113-497-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | David Hovemeyer, William W. Pugh, Jaime Spacco |
Atomic Instructions in Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECOOP ![In: ECOOP 2002 - Object-Oriented Programming, 16th European Conference, Malaga, Spain, June 10-14, 2002, Proceedings, pp. 133-154, 2002, Springer, 3-540-43759-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Hideo Wada, K. Ishil, Masakazu Fukagawa, H. Murayama, Shun Kawabe |
High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 2nd international conference on Supercomputing, ICS 1988, Saint Malo, France, July 4-8, 1988, pp. 196-206, 1988, ACM, 0-89791-272-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
49 | Hui Wang, Rama Sangireddy, Sandeep Baldawa |
Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 20(3), pp. 389-403, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
49 | J. Adam Butts, Gurindar S. Sohi |
Dynamic dead-instruction detection and elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002., pp. 199-210, 2002, ACM Press, 1-58113-574-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Motohiro Kawahito, Hideaki Komatsu, Takao Moriyama, Hiroshi Inoue, Toshio Nakatani |
A new idiom recognition framework for exploiting hardware-assist instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 382-393, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
VMX, hardware-assist instructions, idiom recognition, topological embedding, java, JIT |
48 | Maneesh Agrawala, Doantam Phan, Julie Heiser, John Haymaker, Jeff Klingner, Pat Hanrahan, Barbara Tversky |
Designing effective step-by-step assembly instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Graph. ![In: ACM Trans. Graph. 22(3), pp. 828-837, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
assembly instructions, visualization |
47 | Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan |
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1020-1027, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Vincent J. DiGri, Jane E. King |
The Share 709 System: Input-Output Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 6(2), pp. 141-144, 1959. The full citation details ...](Pics/full.jpeg) |
1959 |
DBLP DOI BibTeX RDF |
|
42 | Aamer Jaleel, Bruce L. Jacob |
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 191-200, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Newton Cheung, Sri Parameswaran, Jörg Henkel |
A quantitative study and estimation models for extensible instructions in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 183-189, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai |
A Code Selection Method for SIMD Processors with PACK Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 66-80, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Ruby B. Lee, A. Murat Fiskiran, Abdulla Bubsha |
Multimedia Instructions In IA-64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, ICME 2001, August 22-25, 2001, Tokyo, Japan, 2001, IEEE Computer Society, 0-7695-1198-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | Norman Ramsey, Mary F. Fernandez |
Specifying Representations of Machine Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(3), pp. 492-524, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
encoding, decoding, compiler generation, relocation, object code, machine description, machine code |
42 | Norman Ramsey |
Relocating Machine Instructions by Currying. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), Philadephia, Pennsylvania, USA, May 21-24, 1996, pp. 226-236, 1996, ACM, 0-89791-795-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
42 | John G. Cleary, Murray Pearson, Husam Kinawi |
The architecture of an optimistic CPU: the WarpEngine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 163-172, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory |
39 | Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería |
On reducing misspeculations in a pipelined scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-12, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Rama Sangireddy, Jatan P. Shah |
Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 19(4), pp. 529-544, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Andrew D. Hilton, Amir Roth |
Ginger: control independence using tag rewriting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 436-447, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
control independence, out-of-order renaming, selective re-dispatch, branch misprediction |
39 | Aamer Jaleel, Bruce L. Jacob |
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 559-574, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts |
39 | Alexei Kudriavtsev, Peter M. Kogge |
Generation of permutations for SIMD processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 147-156, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SIMD, permutations |
39 | Ching-Wen Chen, Chang-Jung Ku, Chih-Hung Chang |
Designing a High Performance and Low Energy-Consuming Embedded System with Considering Code Compressed Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 17-19 August 2005, Hong Kong, China, pp. 317-324, 2005, IEEE Computer Society, 0-7695-2346-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
decompression engine, performance, Embedded system, locality, power consumption, code compress |
39 | Aamer Jaleel, Bruce L. Jacob |
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings, pp. 282-293, 2001, Springer, 3-540-43009-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Jack W. Davidson, David B. Whalley |
Ease: An Environment for Architecture Study and Experimentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, University of Colorado, Boulder, Colorado, USA, May 22-25, 1990, pp. 259-260, 1990, ACM, 0-89791-359-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
38 | Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke |
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 180-189, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection |
38 | Roan Boer Rookhuiszen, Mariët Theune |
Generating Instructions in a 3D Game Environment: Efficiency or Entertainment?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INTETAIN ![In: Intelligent Technologies for Interactive Entertainment, Third International Conference, INTETAIN 2009, Amsterdam, The Netherlands, June 22-24, 2009. Proceedings, pp. 32-43, 2009, Springer, 978-3-642-02314-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
efficiency vs. entertainment, evaluation, game, instructions, Natural Language Generation, 3D environment |
38 | Daniel Spelmezan, Anke Hilgers, Jan O. Borchers |
A language of tactile motion instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mobile HCI ![In: Proceedings of the 11th Conference on Human-Computer Interaction with Mobile Devices and Services, Mobile HCI 2009, Bonn, Germany, September 15-18, 2009, 2009, ACM, 978-1-60558-281-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
motor skill learning, real-time instructions, sports training, tactile language, physical activities, vibrotactile feedback |
38 | Luca Chittaro, Daniele Nadalutti |
Presenting evacuation instructions on mobile devices by means of location-aware 3D virtual environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mobile HCI ![In: Proceedings of the 10th Conference on Human-Computer Interaction with Mobile Devices and Services, Mobile HCI 2008, Amsterdam, the Netherlands, September 2-5, 2008, pp. 395-398, 2008, ACM, 978-1-59593-952-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
navigation instructions, mobile devices, RFID, 3D models, emergencies |
38 | Atsuko K. Yamazaki, Joji Yabutani, Yoko Ebisawa, Satoshi Hori |
A Study of Meaning Comprehensibility of Pictograms for Lathe Procedural Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (3) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 11th International Conference, KES 2007, XVII Italian Workshop on Neural Networks, Vietri sul Mare, Italy, September 12-14, 2007, Proceedings, Part III, pp. 1058-1064, 2007, Springer, 978-3-540-74828-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
manufacturing instructions, communication, comprehensibility, pictogram |
38 | Xuemeng Zhang, Rongcai Zhao, Jianmin Pang |
Semantic Abstraction of IA-64 Multimedia Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SKG ![In: 2006 International Conference on Semantics, Knowledge and Grid (SKG 2006), 1-3 November 2006, Guilin, China, pp. 91, 2006, IEEE Computer Society, 0-7695-2673-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multimedia instructions, semantic abstraction, binary translation, IA-64 |
38 | Arvind Krishnaswamy, Rajiv Gupta 0001 |
Dynamic coalescing for 16-bit instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(1), pp. 3-37, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
16-bit Thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, energy, Embedded processor, code size |
38 | Philip Brisk, Jamie Macbeth 0001, Ani Nahapetian, Majid Sarrafzadeh |
A dictionary construction technique for code compression systems with echo instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 105-114, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
(dictionary) compression, echo instructions, scheduling |
38 | Zhijie Shi, Ruby B. Lee |
Bit Permutation Instructions for Accelerating Software Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 138-148, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bit-level instructions, security, cryptography, permutations, processor architecture, Instruction Set Architecture |
37 | Yedidya Hilewitz, Ruby B. Lee |
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 145-169, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations |
37 | Yuto Kawahara, Kazumaro Aoki, Tsuyoshi Takagi |
Faster Implementation of eta-T Pairing over GF(3m) Using Minimum Number of Logical Instructions for GF(3)-Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Pairing ![In: Pairing-Based Cryptography - Pairing 2008, Second International Conference, Egham, UK, September 1-3, 2008. Proceedings, pp. 282-296, 2008, Springer, 978-3-540-85503-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
GF(3)-addition, logical instruction, ? T pairing |
37 | Kai-Florian Richter, Matt Duckham |
Simplest Instructions: Finding Easy-to-Describe Routes for Navigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GIScience ![In: Geographic Information Science, 5th International Conference, GIScience 2008, Park City, UT, USA, September 23-26, 2008. Proceedings, pp. 274-289, 2008, Springer, 978-3-540-87472-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Pan Yu, Tulika Mitra |
Disjoint Pattern Enumeration for Custom Instructions Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 273-278, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Enric Morancho, José María Llabería, Àngel Olivé |
On reducing energy-consumption by late-inserting instructions into the issue queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 371-374, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
L2 hit-miss prediction, memory-latency tolerant processors, energy consumption |
37 | Yedidya Hilewitz, Ruby B. Lee |
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA, pp. 65-72, 2006, IEEE Computer Society, 0-7695-2682-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Sung Dae Kim, Jung Hoo Lee, J. M. Yang, Myung Hoon Sunwoo, Seung Keun Oh |
Novel instructions and their hardware architecture for video signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3323-3326, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Jinson Koppanalil, Eric Rotenberg |
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(4), pp. 399-413, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
slipstream, preexecution, chip multiprocessor, multithreading, Microarchitecture |
37 | Krishna V. Palem, Barbara B. Simons |
Scheduling Time-Critical Instructions on RISC Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 15(4), pp. 632-658, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor |
37 | Thomas M. Morgan, Lawrence A. Rowe |
Analyzing Exotic Instructions for a Retargetable Code Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGPLAN Symposium on Compiler Construction ![In: Proceedings of the SIGPLAN '82 Symposium on Compiler Construction, Boston, Massachusetts, USA, June 23-25, 1982, pp. 197-204, 1982, ACM, 0-89791-074-5. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
37 | David I. August, Wen-mei W. Hwu, Scott A. Mahlke |
A Framework for Balancing Control Flow and Predication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 92-103, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
conditional instructions, if-conversion, predicated instructions, program control flow, schedule time, scheduling decisions, compiler, parallel architecture, instruction-level parallelism, optimising compilers, predicated execution |
35 | Mike Fournigault, Pierre-Yvan Liardet, Yannick Teglia, Alain Trémeau, Frédérique Robert-Inacio |
Reverse Engineering of Embedded Software Using Syntactic Pattern Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OTM Workshops (1) ![In: On the Move to Meaningful Internet Systems 2006: OTM 2006 Workshops, OTM Confederated International Workshops and Posters, AWeSOMe, CAMS, COMINF, IS, KSinBIT, MIOS-CIAO, MONET, OnToContent, ORM, PerSys, OTM Academy Doctoral Consortium, RDDS, SWWS, and SeBGIS 2006, Montpellier, France, October 29 - November 3, 2006. Proceedings, Part I, pp. 527-536, 2006, Springer, 3-540-48269-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Chip Instructions, Pattern Recognition, Reverse Engineering, Power Analysis, Side Channel |
35 | Ben H. H. Juurlink, Asadollah Shahbahrami, Stamatis Vassiliadis |
Avoiding data conversions in embedded media processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), Santa Fe, New Mexico, USA, March 13-17, 2005, pp. 901-902, 2005, ACM, 1-58113-964-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multimedia applications, SIMD instructions |
35 | Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia |
Micro embedded monitoring for security in application specific instruction-set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 304-314, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring |
35 | Alex Pajuelo, Antonio González 0001, Mateo Valero |
Speculative Dynamic Vectorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 271-280, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Speculative dynamic vectorization, wide buses, speculative data computation, control independence, vector instructions |
34 | Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero |
DIA: A Complexity-Effective Decoding Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(4), pp. 448-462, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 9:1-9:37, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
34 | Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary |
Transparent control independence (TCI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 448-459, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
control independence, selective re-execution, selective recovery, checkpoints, branch prediction, speculation |
34 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Instruction-level test methodology for CPU core self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 673-689, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing |
34 | Jian Huang, David J. Lilja |
Balancing Reuse Opportunities and Performance Gains with Subblock Value Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(8), pp. 1032-1050, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Block reuse, subblock reuse, compiler flow analysis, value reuse, value locality |
34 | Enric Musoll |
Speculating to reduce unnecessary power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 2(4), pp. 509-536, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low-power microarchitectures, Low-power design |
34 | Miroslav N. Velev |
Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 28-35, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Vugranam C. Sreedhar, Roy Dz-Ching Ju, David M. Gillies, Vatsa Santhanam |
Translating Out of Static Single Assignment Form. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 6th International Symposium, SAS '99, Venice, Italy, September 22-24, 1999, Proceedings, pp. 194-210, 1999, Springer, 3-540-66459-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan |
Speculation Techniques for Improving Load Related Instruction Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 42-53, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Jay W. Warfield, Henry R. Bauer III |
An expert system for a retargetable peephole optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 23(10), pp. 123-130, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
34 | E. M. Boehm, Thomas B. Steel Jr. |
The Share 709 System: Machine Implementation of Symbolic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 6(2), pp. 134-140, 1959. The full citation details ...](Pics/full.jpeg) |
1959 |
DBLP DOI BibTeX RDF |
|
33 | Seung-Won Na |
Design and Implementation of Resource Sharing System for Creation of Multiple Instructions In Mobile Internet Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSTST ![In: Soft Computing as Transdisciplinary Science and Technology, Proceedings of the fourth IEEE International Workshop, WSTST'05, Muroran, Japan, pp. 797-807, 2005, Springer, 978-3-540-25055-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Sharing of Mobile Resources, Ubiquitous Computing, Context-Awareness, multiple instructions |
33 | Antonio González 0001, José M. Llabería |
Instruction fetch unit for parallel execution of branch instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989, pp. 417-426, 1989, ACM, 0-89791-309-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
instruction cache memory, zero time cost branches, pipelined processors, control dependencies, branch instructions |
32 | Thomas Gaudy, Stéphane Natkin, Dominique Archambault |
Pyvox 2: An Audio Game Accessible to Visually Impaired People Playable without Visual Nor Verbal Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Edutainment ![In: Transactions on Edutainment II, pp. 176-186, 2009, Springer, 978-3-642-03269-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interactivity, accessibility, usability test, sound design, interactive music, audio games |
32 | Asadollah Shahbahrami, Ben H. H. Juurlink |
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 389-407, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Martino Sykora, Giovanni Agosta, Cristina Silvano |
Dynamic configuration of application-specific implicit instructions for embedded pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 1509-1516, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
implicit issue, reconfiguration, pipelined architecture |
32 | Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis |
A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 283-293, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Joerg C. Wolf, Guido Bugmann |
Understanding Rules in Human-Robot Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RO-MAN ![In: IEEE RO-MAN 2007, 16th IEEE International Symposium on Robot & Human Interactive Communication, August 26-29, 2007, Jeju Island, South Korea, Proceedings, pp. 714-719, 2007, IEEE, 978-1-4244-1634-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Neng-Fa Zhou |
A Register-Free Abstract Prolog Machine with Jumbo Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICLP ![In: Logic Programming, 23rd International Conference, ICLP 2007, Porto, Portugal, September 8-13, 2007, Proceedings, pp. 455-457, 2007, Springer, 978-3-540-74608-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis |
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 130-141, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kablia |
16-bit Floating Point Instructions for Embedded Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 4-6 July 2005, Palermo, Italy, pp. 198-203, 2005, IEEE Computer Society, 0-7695-2255-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Neil Johnson 0002, Alan Mycroft |
Using Multiple Memory Access Instructions for Reducing Code Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 13th International Conference, CC 2004, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2004, Barcelona, Spain, March 29 - April 2, 2004, Proceedings, pp. 265-280, 2004, Springer, 3-540-21297-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh |
Instruction Selection for Compilers that Target Architectures with Echo Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 8th International Workshop, SCOPES 2004, Amsterdam, The Netherlands, September 2-3, 2004, Proceedings, pp. 229-243, 2004, Springer, 3-540-23035-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Adrián Cristal, Oliverio J. Santana, Mateo Valero |
Maintaining Thousands of In-flight Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2004 Parallel Processing, 10th International Euro-Par Conference, Pisa, Italy, August 31-September 3, 2004, Proceedings, pp. 9-20, 2004, Springer, 3-540-22924-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Pan Yu, Tulika Mitra |
Scalable custom instructions identification for instruction-set extensible processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 69-78, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors |
32 | Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh |
Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 148-155, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Martin Raubal, Stephan Winter 0001 |
Enriching Wayfinding Instructions with Local Landmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GIScience ![In: Geographic Information Science, Second International Conference, GIScience 2002, Boulder, CO, USA, September 25-28, 2002, Proceedings, pp. 243-259, 2002, Springer, 3-540-44253-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Zhijie Shi, Ruby B. Lee |
Subword Sorting with Versatile Permutation Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 234-241, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 171-176, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Stamatis Vassiliadis, Ben H. H. Juurlink, Edwin A. Hakkennes |
Complex Streamed Instructions: Introduction and Initial Evaluatio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1400-, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Craig B. Zilles, Gurindar S. Sohi |
Understanding the backward slices of performance degrading instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 172-181, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Francesco Quaglia |
Fast-Software-Checkpointing in Optimistic Simulation: Embedding State Saving into the Event Routine Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Parallel and Distributed Simulation ![In: Proceedings of the Thirteenth Workshop on Parallel and Distributed Simulation, PADS '99, Atlanta, GA, USA, May 1-4, 1999, pp. 118-125, 1999, IEEE Computer Society, 0-7695-0155-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Allen Leung, Krishna V. Palem, Amir Pnueli |
A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 158-, 1998, IEEE Computer Society, 0-8186-8591-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications |
32 | Edward L. Robertson |
Code Generation and Storage Allocation for Machines with Span-Dependent Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 1(1), pp. 71-83, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
|
32 | Amir M. Ben-Amram, Zvi Galil |
When can we sort in o(n log n) time? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 34th Annual Symposium on Foundations of Computer Science, Palo Alto, California, USA, 3-5 November 1993, pp. 538-546, 1993, IEEE Computer Society, 0-8186-4370-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Boolean instructions, arithmetic instructions, nonuniform programs, double-precision multiplication, lower bounds, upper bounds, random access machine |
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