|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 16 occurrences of 15 keywords
|
|
|
Results
Found 66 publication records. Showing 66 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Yi Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, Robert D. Brink |
Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 700-709, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
80 | Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha |
Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 58-66, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
74 | Joe G. Xi, Wayne Wei-Ming Dai |
Jitter-tolerant clock routing in two-phase synchronous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 316-320, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew |
72 | Masashi Shimanouchi |
Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 48-57, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Siu-Ping Chan, Chi-Wah Kok, Albert K. Wong |
Multimedia streaming gateway with jitter detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multim. ![In: IEEE Trans. Multim. 7(3), pp. 585-592, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie |
A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 717-725, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha |
Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 45-48, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Yongquan Fan, Zeljko Zilic |
Accelerating jitter tolerance qualification for high speed serial interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 360-365, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 206-209, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Yen-Long Lee, Yu-Po Cheng, Soon-Jyh Chang, Hsin-Wen Ting |
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 35(1), pp. 63-73, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
33 | Yuki Ozawa, Takuya Arafune, Nobukazu Tsukiji, Haruo Kobayashi 0001, Ryoji Shiota |
Study of jitter generators for high-speed I/O interface jitter tolerance testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: 2017 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2017, Xiamen, China, November 6-9, 2017, pp. 468-473, 2017, IEEE, 978-1-5386-2159-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
33 | Kyung-Sub Son, Jin-Ku Kang |
On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 12(15), pp. 20150570, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Dongwoo Hong, Kwang-Ting (Tim) Cheng |
Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 17-22, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bang-Bang CDR, BER Estimation |
32 | Jan B. Wilstrup |
A method of serial data jitter analysis using one-shot time interval measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 819-823, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai |
A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 77-84, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi |
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1187-1198, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Kwang-Ting Cheng |
New beginnings, continued success. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(1), pp. 5-6, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transistor mismatch, jitter-tolerance testing, design for testability, heterogeneous systems, dependability analysis, design and test, nanometer technology, design debugging |
22 | David C. Keezer, Dany Minier, Patrice Ducharme |
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(1), pp. 46-57, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing |
21 | Yao-Chia Liu, Wei-Zen Chen, Yuan-Sheng Lee, Yu-Hsiang Chen, Shawn Ming, Ying-Hsi Lin |
A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(10), pp. 2801-2811, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Guanrong Hou, Behzad Razavi |
A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(9), pp. 2856-2867, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu |
A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(3), pp. 894-898, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Shun-Chi Chang, Shen-Iuan Liu |
A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(1), pp. 161-165, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu |
A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(6), pp. 1837-1841, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Guanrong Hou, Behzad Razavi |
A 56-Gb/s 8-mW PAM4 CDR/DMUX with High Jitter Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, pp. 1-2, 2021, IEEE, 978-4-86348-780-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Kyungho Ryu, Kil-Hoon Lee, Jung-Pil Lim, Jinho Kim, Han Su Pae, Junho Park, Hyun-Wook Lim, Jae-Youl Lee |
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(11), pp. 2257-2267, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Francisco E. Rangel-Patino, Andres Viveros-Wacher, José Ernesto Rayas-Sánchez, Ismael Duron-Rosales, Edgar-Andrei Vega-Ochoa, Nagib Hakim, Enrique Lopez-Miralrio |
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 8(2), pp. 453-463, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Zhou Shu, Shalin Huang, Zhipeng Li, Peng Yin 0004, Jiandong Zang, Dongbing Fu, Fang Tang, Amine Bermak |
A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-I(10), pp. 3378-3388, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Long Kong, Yikun Chang, Behzad Razavi |
An Inductorless 20-Gb/s CDR With High Jitter Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(10), pp. 2857-2866, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Rui Zhang 0048, Wen-Jr Jiang, Konstantin Kuzmin, Reggie Juluri, Gee-Kung Chang, Winston I. Way |
Laser Frequency Jitter Tolerance and Linewidth Requirement for ≥ 64Gbaud DP-16QAM Coherent Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2019, San Diego, CA, USA, March 3-7, 2019, pp. 1-3, 2019, IEEE, 978-1-943580-53-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi |
Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(9), pp. 2696-2708, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Miguel A. Davalos-Santana, Edgar-Andrei Vega-Ochoa, José Ernesto Rayas-Sánchez |
Jitter tolerance acceleration using the golden section optimization technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 9th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2018, Puerto Vallarta, Mexico, February 25-28, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-2311-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Long Kong, Yikun Chang, Behzad Razavi |
A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, pp. 271-272, 2018, IEEE, 978-1-5386-4214-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Andreas Tsimpos, Andreas Christos Demartinos, Spyridon Vlassis, George Souliotis |
Jitter tolerance calibration for high-speed serial interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 57, pp. 101-107, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi |
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 122-123, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Yen-Long Lee, Soon-Jyh Chang |
A quick jitter tolerance estimation technique for bang-bang CDRs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017, pp. 8-13, 2017, IEEE, 978-1-5386-3051-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee 0002, Chulwoo Kim |
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(3), pp. 1092-1103, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | J. A. Guinea |
Bang-bang cycle-slip detector improves jitter-tolerance in SONET PLL/DLL CDR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 44(10), pp. 1828-1839, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Young-Ju Kim 0001, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Lee-Sup Kim |
A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10), pp. 2495-2503, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang |
On-chip jitter tolerance measurement technique for CDR circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 1602-1605, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Roberto DiCecco, Roman Pahuta, Chris D. Holdenried, Saman Sadr |
Test considerations for jitter tolerance of wireline receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE 27th Canadian Conference on Electrical and Computer Engineering, CCECE 2014, Toronto, ON, Canada, May 4-7, 2014, pp. 1-5, 2014, IEEE, 978-1-4799-3099-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | Myeong-Jae Park, Jaeha Kim |
A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014, pp. 1-6, 2014, IEEE Computer Society, 978-1-4799-4722-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
21 | June-Hee Lee, Sang-Hoon Kim, Jongshin Shin, Dong-Chul Choi, Kee-Won Kwon, Jung-Hoon Chun |
A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 1027-1030, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Yi Cai, Liming Fang, Ivan Chan, Max Olsen, Kevin Richter |
12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2013 IEEE International Test Conference, ITC 2013, Anaheim, CA, USA, September 6-13, 2013, pp. 1-8, 2013, IEEE Computer Society, 978-1-4799-0859-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | Arnoud P. van der Wel, Gerrit den Besten |
A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 47(7), pp. 1768-1775, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu |
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(3), pp. 148-152, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Chao He, Tadeusz Kwasniewski |
Bang-Bang CDR's acquisition, locking, and jitter tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 25th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2012, Montreal, QC, Canada, April 29 - May 2, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-1431-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
21 | Stefan Erb, Wolfgang Pribyl |
A method for fast jitter tolerance analysis of high-speed PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 1107-1112, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Arnoud P. van der Wel, Gerrit den Besten |
A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011, pp. 167-170, 2011, IEEE, 978-1-4577-0703-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
21 | Timothy Daniel Lyons |
Complete testing of receiver jitter tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 9-18, 2010, IEEE Computer Society, 978-1-4244-7206-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
21 | Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu |
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 43(5), pp. 1217-1226, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker |
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(10), pp. 2224-2234, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon |
A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007, pp. 353-356, 2007, IEEE, 978-1-4244-1623-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Stephen K. Sunter, Aubin Roy |
Structural Tests for Jitter Tolerance in SerDes Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-10, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar |
An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-10, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Paul Muller, Yusuf Leblebici |
Jitter Tolerance Analysis of Clock and Data Recovery Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2005, September 27-30, 2005, Lausanne, Switzerland, Proceedings, pp. 143-147, 2005, ECSI. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
21 | Stephen K. Sunter, Aubin Roy |
Structural tests for jitter tolerance in SerDes receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 10, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Hyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar |
A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 101-106, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Grenville J. Armitage, Lawrence Stewart |
Limitations of using real-world, public servers to estimate jitter tolerance of first person shooter games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Advances in Computer Entertainment Technology ![In: Proceedings of the 2004 ACM SIGCHI International Conference on Advances in Computer Entertainment Technology, 2004, Singapore, June 3-5, 2004, pp. 257-262, 2004, ACM, 1-58113-882-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Quake III arena, jitter, network games, first person shooter, internet service provider |
21 | Patrick R. Trischitta, Peddapullaiah Sannuti |
The Jitter Tolerance of Fiber Optic Regenerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 35(12), pp. 1303-1308, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
18 | S. I. Ahmed, Tad A. Kwasniewski |
An all-digital data recovery circuit optimization using Matlab/Simulink. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4485-4488, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Jayasanker Jayabalan, Kiang Goh Chee, Ban-Leong Ooi, Mook Seng Leong, Mahadevan K. Iyer, Andrew A. O. Tay |
PLL Based High Speed Functional Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 116-119, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici |
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici |
A low-power, multichannel gated oscillator-based CDR for short-haul applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 107-110, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Ming-Ta Hsieh, Gerald E. Sobelman |
Modeling and verification of high-speed wired links with Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Dimitris Tsiokos, Efstratios Kehayas, Paraskevas Bakopoulos, Dimitrios Apostolopoulos, Dimitrios Petrantonakis, Nikos Pleros, Hercules Avramopoulos |
All-Optical Signal Processing Using Integrated Mach Zehnder Interferometric Switches for 40 Gb/s All-Optical Label-Swapped Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BROADNETS ![In: 3rd International Conference on Broadband Communications, Networks, and Systems (BROADNETS 2006), 1-5 October 2006, San José, California, USA, 2006, IEEE, 978-1-4244-0425-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Gang Xu, Jiren Yuan |
Performance analysis of general charge sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 745-748, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #66 of 66 (100 per page; Change: )
|
|