Search results for "jitter-tolerance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Yi Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, Robert D. Brink	Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter.	ITC	2002	DBLP DOI BibTeX RDF
80	Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Makoto Kurosawa, Hirobumi Musha	Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements.	ITC	2003	DBLP DOI BibTeX RDF
74	Joe G. Xi, Wayne Wei-Ming Dai	Jitter-tolerant clock routing in two-phase synchronous systems.	ICCAD	1996	DBLP DOI BibTeX RDF	Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
72	Masashi Shimanouchi	Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production.	ITC	2003	DBLP DOI BibTeX RDF
60	Siu-Ping Chan, Chi-Wah Kok, Albert K. Wong	Multimedia streaming gateway with jitter detection.	IEEE Trans. Multim.	2005	DBLP DOI BibTeX RDF
51	Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie	A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter.	ITC	2002	DBLP DOI BibTeX RDF
46	Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha	Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
43	Yongquan Fan, Zeljko Zilic	Accelerating jitter tolerance qualification for high speed serial interfaces.	ISQED	2009	DBLP DOI BibTeX RDF
39	Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.	DDECS	2009	DBLP DOI BibTeX RDF
33	Yen-Long Lee, Yu-Po Cheng, Soon-Jyh Chang, Hsin-Wen Ting	A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs.	IEEE Des. Test	2018	DBLP DOI BibTeX RDF
33	Yuki Ozawa, Takuya Arafune, Nobukazu Tsukiji, Haruo Kobayashi 0001, Ryoji Shiota	Study of jitter generators for high-speed I/O interface jitter tolerance testing.	ISPACS	2017	DBLP DOI BibTeX RDF
33	Kyung-Sub Son, Jin-Ku Kang	On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
32	Dongwoo Hong, Kwang-Ting (Tim) Cheng	Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links.	VTS	2008	DBLP DOI BibTeX RDF	Bang-Bang CDR, BER Estimation
32	Jan B. Wilstrup	A method of serial data jitter analysis using one-shot time interval measurements.	ITC	1998	DBLP DOI BibTeX RDF
25	Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai	A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems.	ITC	2004	DBLP DOI BibTeX RDF
22	Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi	An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
22	Kwang-Ting Cheng	New beginnings, continued success.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	transistor mismatch, jitter-tolerance testing, design for testability, heterogeneous systems, dependability analysis, design and test, nanometer technology, design debugging
22	David C. Keezer, Dany Minier, Patrice Ducharme	Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing
21	Yao-Chia Liu, Wei-Zen Chen, Yuan-Sheng Lee, Yu-Hsiang Chen, Shawn Ming, Ying-Hsi Lin	A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
21	Guanrong Hou, Behzad Razavi	A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
21	Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu	A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
21	Shun-Chi Chang, Shen-Iuan Liu	A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
21	Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu	A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
21	Guanrong Hou, Behzad Razavi	A 56-Gb/s 8-mW PAM4 CDR/DMUX with High Jitter Tolerance.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
21	Kyungho Ryu, Kil-Hoon Lee, Jung-Pil Lim, Jinho Kim, Han Su Pae, Junho Park, Hyun-Wook Lim, Jae-Youl Lee	An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
21	Francisco E. Rangel-Patino, Andres Viveros-Wacher, José Ernesto Rayas-Sánchez, Ismael Duron-Rosales, Edgar-Andrei Vega-Ochoa, Nagib Hakim, Enrique Lopez-Miralrio	A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation.	IEEE Trans. Emerg. Top. Comput.	2020	DBLP DOI BibTeX RDF
21	Zhou Shu, Shalin Huang, Zhipeng Li, Peng Yin 0004, Jiandong Zang, Dongbing Fu, Fang Tang, Amine Bermak	A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
21	Long Kong, Yikun Chang, Behzad Razavi	An Inductorless 20-Gb/s CDR With High Jitter Tolerance.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
21	Rui Zhang 0048, Wen-Jr Jiang, Konstantin Kuzmin, Reggie Juluri, Gee-Kung Chang, Winston I. Way	Laser Frequency Jitter Tolerance and Linewidth Requirement for ≥ 64Gbaud DP-16QAM Coherent Systems.	OFC	2019	DBLP BibTeX RDF
21	Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi	Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
21	Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Miguel A. Davalos-Santana, Edgar-Andrei Vega-Ochoa, José Ernesto Rayas-Sánchez	Jitter tolerance acceleration using the golden section optimization technique.	LASCAS	2018	DBLP DOI BibTeX RDF
21	Long Kong, Yikun Chang, Behzad Razavi	A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
21	Andreas Tsimpos, Andreas Christos Demartinos, Spyridon Vlassis, George Souliotis	Jitter tolerance calibration for high-speed serial interfaces.	Integr.	2017	DBLP DOI BibTeX RDF
21	Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi	6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.	ISSCC	2017	DBLP DOI BibTeX RDF
21	Yen-Long Lee, Soon-Jyh Chang	A quick jitter tolerance estimation technique for bang-bang CDRs.	ITC-Asia	2017	DBLP DOI BibTeX RDF
21	Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee 0002, Chulwoo Kim	An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
21	J. A. Guinea	Bang-bang cycle-slip detector improves jitter-tolerance in SONET PLL/DLL CDR.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
21	Young-Ju Kim 0001, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Lee-Sup Kim	A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
21	Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang	On-chip jitter tolerance measurement technique for CDR circuits.	ISCAS	2015	DBLP DOI BibTeX RDF
21	Roberto DiCecco, Roman Pahuta, Chris D. Holdenried, Saman Sadr	Test considerations for jitter tolerance of wireline receivers.	CCECE	2014	DBLP DOI BibTeX RDF
21	Myeong-Jae Park, Jaeha Kim	A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers.	ITC	2014	DBLP DOI BibTeX RDF
21	June-Hee Lee, Sang-Hoon Kim, Jongshin Shin, Dong-Chul Choi, Kee-Won Kwon, Jung-Hoon Chun	A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance.	MWSCAS	2013	DBLP DOI BibTeX RDF
21	Yi Cai, Liming Fang, Ivan Chan, Max Olsen, Kevin Richter	12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit.	ITC	2013	DBLP DOI BibTeX RDF
21	Arnoud P. van der Wel, Gerrit den Besten	A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
21	Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu	An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
21	Chao He, Tadeusz Kwasniewski	Bang-Bang CDR's acquisition, locking, and jitter tolerance.	CCECE	2012	DBLP DOI BibTeX RDF
21	Stefan Erb, Wolfgang Pribyl	A method for fast jitter tolerance analysis of high-speed PLLs.	DATE	2011	DBLP DOI BibTeX RDF
21	Arnoud P. van der Wel, Gerrit den Besten	A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS.	ESSCIRC	2011	DBLP DOI BibTeX RDF
21	Timothy Daniel Lyons	Complete testing of receiver jitter tolerance.	ITC	2010	DBLP DOI BibTeX RDF
21	Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu	A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
21	Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker	A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon	A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance.	CICC	2007	DBLP DOI BibTeX RDF
21	Stephen K. Sunter, Aubin Roy	Structural Tests for Jitter Tolerance in SerDes Receivers.	ITC	2006	DBLP DOI BibTeX RDF
21	Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar	An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA.	ITC	2006	DBLP DOI BibTeX RDF
21	Paul Muller, Yusuf Leblebici	Jitter Tolerance Analysis of Clock and Data Recovery Circuits.	FDL	2005	DBLP BibTeX RDF
21	Stephen K. Sunter, Aubin Roy	Structural tests for jitter tolerance in SerDes receivers.	ITC	2005	DBLP DOI BibTeX RDF
21	Hyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar	A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling.	IWSOC	2005	DBLP DOI BibTeX RDF
21	Grenville J. Armitage, Lawrence Stewart	Limitations of using real-world, public servers to estimate jitter tolerance of first person shooter games.	Advances in Computer Entertainment Technology	2004	DBLP DOI BibTeX RDF	Quake III arena, jitter, network games, first person shooter, internet service provider
21	Patrick R. Trischitta, Peddapullaiah Sannuti	The Jitter Tolerance of Fiber Optic Regenerators.	IEEE Trans. Commun.	1987	DBLP DOI BibTeX RDF
18	S. I. Ahmed, Tad A. Kwasniewski	An all-digital data recovery circuit optimization using Matlab/Simulink.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	Jayasanker Jayabalan, Kiang Goh Chee, Ban-Leong Ooi, Mook Seng Leong, Mahadevan K. Iyer, Andrew A. O. Tay	PLL Based High Speed Functional Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
15	Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici	Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici	A low-power, multichannel gated oscillator-based CDR for short-haul applications.	ISLPED	2005	DBLP DOI BibTeX RDF
11	Ming-Ta Hsieh, Gerald E. Sobelman	Modeling and verification of high-speed wired links with Verilog-AMS.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Dimitris Tsiokos, Efstratios Kehayas, Paraskevas Bakopoulos, Dimitrios Apostolopoulos, Dimitrios Petrantonakis, Nikos Pleros, Hercules Avramopoulos	All-Optical Signal Processing Using Integrated Mach Zehnder Interferometric Switches for 40 Gb/s All-Optical Label-Swapped Networks.	BROADNETS	2006	DBLP DOI BibTeX RDF
11	Gang Xu, Jiren Yuan	Performance analysis of general charge sampling.	ISCAS (1)	2003	DBLP DOI BibTeX RDF