Search results for "latch-up"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
40	Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev	Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment.	ISQED	2005	DBLP DOI BibTeX RDF	Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, latch-up, burn-in
35	Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto	An Experimental Study on Latch Up Failure of CMOS LSI.	SSIRI	2008	DBLP DOI BibTeX RDF	latch up, CMOS LSI
33	Michael Heer, Krzysztof Domanski, Kai Esmark, Ulrich Glaser, Dionyz Pogany, Erich Gornik, Wolfgang Stadler	Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
29	Octavian-Dumitru Mocanu, Joan Oliver	Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	hamming SEC code, latch-up, memory system, single event upset, built-in current sensor
21	Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami	Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies.	VLSI Design	2001	DBLP DOI BibTeX RDF
16	Jingfei Wang, Guishu Liang, Xiangyu Zhang 0004, Lei Qi 0005	A Refinement Multilevel Turn-off Method for Dynamic Latch-up and Tail Current Suppression in DC Breaker Ultra-High Current Switch Applications.	IEEE Trans. Ind. Electron.	2024	DBLP DOI BibTeX RDF
16	Shao-Chang Huang, Jian-Hsing Lee, Chun-Chih Chen, Ching-Ho Li, Chih-Cherng Liao, Kai-Chieh Hsu, Gong-Kai Lin, Li-Fan Chen, Chien-Wei Wang, Chih-Hsuan Lin, Yeh-Ning Jou, Ke-Horng Chen	Gate Voltages Impacting on Latch-up Measurements.	ICCE-TW	2022	DBLP DOI BibTeX RDF
16	Zhihua Zhu, Songyan Wang, Xiaomei Fan	A Novel Latch-Up-Immune DDSCR Used for 12 V Applications.	IRPS	2022	DBLP DOI BibTeX RDF
16	Songyan Wang, Xiaomei Fan, Zhihua Zhu, Yingtao Zhang, Ruike Chen, Juin Jei Liou	A LVTSCR-Based Compact Structure for Latch-up Immune.	ASICON	2021	DBLP DOI BibTeX RDF
16	Yibo Jiang, Hui Bi 0003, Wei Zhao, Chen Shi, Xiaolei Wang	Latch-Up Immune Bi-Direction ESD Protection Clamp for Push-Pull RF Power Amplifier.	IEICE Trans. Electron.	2020	DBLP DOI BibTeX RDF
16	Chun-Cheng Chen, Ming-Dou Ker	Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process.	IRPS	2019	DBLP DOI BibTeX RDF
16	Milova Paul, Boeila Sampath Kumar, Harald Gossner, Mayank Shrivastava	Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability.	IRPS	2018	DBLP DOI BibTeX RDF
16	Krzysztof Domanski	Latch-up in FinFET technologies.	IRPS	2018	DBLP DOI BibTeX RDF
16	Kyung-Il Do, Byung-Seok Lee, Hee-Guk Chae, Jeong-Ju Seo, Yong-Seo Koo	A New Low Trigger SCR with Latch up Immunity for 5V Application.	EECS	2018	DBLP DOI BibTeX RDF
16	Bodo Selmke, Kilian Zinnecker, Philipp Koppermann, Katja Miller, Johann Heyszl, Georg Sigl	Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors.	FDTC	2018	DBLP DOI BibTeX RDF
16	Joonseop Sim, Mohsen Imani, Woojin Choi, Yeseong Kim, Tajana Rosing	LUPIS: Latch-up based ultra efficient processing in-memory system.	ISQED	2018	DBLP DOI BibTeX RDF
16	Sarah Azimi, Luca Sterpone	Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach.	ISVLSI	2017	DBLP DOI BibTeX RDF
16	Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten	Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
16	Qi Jiang, Huihui Yuan, Yang Wang, Xiangliang Jin	Design and analyze of transient-induced latch-up in RS485 transceiver with on-chip TVS.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
16	Weicheng Qiu, Xiang-Ai Cheng, Rui Wang, Zhongjie Xu, Chao Shen	The transient analysis of latch-up in CMOS transmission gate induced by laser.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
16	Luca Sterpone	SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Jie Chen, Zhengwei Du	Device simulation studies on latch-up effects in CMOS inverters induced by microwave pulse.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Jie Chen, Zhengwei Du	Understanding and modeling of internal transient latch-up susceptibility in CMOS inverters due to microwave pulses.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
16	Haipeng Zhang, Ruisheng Qi, Liang Zhang, Buchun Su, Dejun Wang	Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity.	VLSI Design	2011	DBLP DOI BibTeX RDF
16	Dionyz Pogany, Sergey Bychikhin, Michael Heer, W. Mamanee, Erich Gornik	Application of transient interferometric mapping method for ESD and latch-up analysis.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
16	Roxane Llido, J. Gomez, Vincent Goubier, N. Froidevaux, L. Dufayard, Gérald Haller, Vincent Pouget, Dean Lewis	Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
16	Pan Dong, Long Fan, Suge Yue, Hongchao Zheng, Shougang Du	New Latch-Up Model for Deep Sub-micron Integrated Circuits.	DASC	2011	DBLP DOI BibTeX RDF
16	Augusto Tazzoli, Martina Cordoni, Paolo Colombo, C. Bergonzoni, Gaudenzio Meneghesso	Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65 nm technology platform.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
16	Su-Jin Park, Yonggu Kang, Joung-Yeal Kim, Tae Hee Han, Young-Hyun Jun, Chil-Gee Lee, Bai-Sun Kong	CMOS cross-coupled charge pump with improved latch-up immunity.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
16	Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin	Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration.	APCCAS	2008	DBLP DOI BibTeX RDF
16	Michael Heer, Viktor Dubec, Sergey Bychikhin, Dionyz Pogany, Erich Gornik, M. Frank, A. Konrad, J. Schulz	Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
16	Detlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz	Transient-induced latch-up test setup for wafer-level and package-level.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
16	Krzysztof Domanski, B. Póltorak, S. Bargstädt-Franke, Wolfgang Stadler, Waclaw Bala	Physical fundamentals of external transient latch-up and corrective actions.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
16	S. Bargstädt-Franke, Wolfgang Stadler, Kai Esmark, Martin Streibl, Krzysztof Domanski, Horst A. Gieser, Heinrich Wolf, Waclaw Bala	Transient latch-up: experimental analysis and device simulation.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
16	Gianluca Boselli, Charvaka Duvvury	Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
16	David Trémouilles, Marise Bafleur, Géraldine Bertrand, Nicolas Nolhier, Nicolas Mauran, Lionel Lescouzères	Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	Vladislav A. Vashchenko, Ann Concannon, Marcel ter Beek, P. Hopper	LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
16	Markus P. J. Mergens, Christian C. Russ, Koen G. Verhaege, John Armer, Phillip Jozwiak, Russ Mohn	High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
16	Ey Goo Kang, Seung Hyun Moon, Man Young Sung	A small sized lateral trench electrode IGBT having improved latch-up and breakdown characteristics for power IC system.	ICECS	2001	DBLP DOI BibTeX RDF
16	Young-Hee Kim, Jae-Yoon Sim, Hong June Park, Jae-Ik Doh, Kun-Woo Park, Hyun-Woong Chung, Jong-Hoon Oh, Choon-Sik Oh, Seung-Han Ahn	Analysis and prevention of DRAM latch-up during power-on.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
16	Enrico Sangiorgi	Latch-up in CMOS circuits: A review.	Eur. Trans. Telecommun.	1990	DBLP DOI BibTeX RDF
16	Roberto Menozzi, Massimo Lanzoni, Luca Selmi, Bruno Riccò	An improved procedure to test CMOS ICs for latch-up.	ITC	1990	DBLP DOI BibTeX RDF
16	Donald B. Estreich, Robert W. Dutton	Modeling Latch-Up in CMOS Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1982	DBLP DOI BibTeX RDF
11	Dongsheng Ma	Automatic substrate switching circuit for on-chip adaptive power supply system.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Yasutaka Haga, Richard C. S. Morling, Izzet Kale	A new bulk-driven input stage design for sub 1-volt CMOS op-amps.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Javier A. Salcedo, Juin J. Liou, Muhammad Yaqub Afridi, Allen R. Hefner	Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
11	Ming-Dou Ker, Kuo-Chun Hsu	On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
11	J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak	SOI Implementation of a 64-Bit Adder.	ICCD	1999	DBLP DOI BibTeX RDF
11	R. J. McDonald, Jerry G. Fossum	High-voltage device modeling for SPICE simulation of HVIC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF