Search results for "multi-port"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
116	Yuejian Wu, Sanjay Gupta	Built-In Self-Test for Multi-Port RAMs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST)
85	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
65	Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi	Detection of Inter-Port Faults in Multi-Port Static RAMs.	VTS	2000	DBLP DOI BibTeX RDF
61	Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers	Detecting Unique Faults in Multi-port SRAMs.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
61	Farzin Karimi, Fabrizio Lombardi	Parallel Testing of Multi-port Static Random Access Memories for BIST.	DFT	2001	DBLP DOI BibTeX RDF	Memory testing, embedded memory, multi-port, parallel testing
55	Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers	Realistic Fault Models and Test Procedures for Multi-Port SRAMs.	MTDT	2001	DBLP DOI BibTeX RDF
51	Bo Song, Huaxin Zeng, Liquan Yue	On Concurrent Multi-port Test System for Routers and Its Support Tools.	PDCAT	2004	DBLP DOI BibTeX RDF
49	Balasubramanian Sethuraman, Ranga Vemuri	Power variations of multi-port routers in an application-specific NoC design : A case study.	ICCD	2007	DBLP DOI BibTeX RDF
49	Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams	Defect Analysis and a New Fault Model for Multi-port SRAMs.	DFT	2001	DBLP DOI BibTeX RDF	dual-port, SDDRF, electrical fault model, SRAM, defect analysis, multi-port
48	Christian Mandl, Adolfo Fucci	A fast FPGA based coprocessor supporting hard real-time search.	EUROMICRO	1997	DBLP DOI BibTeX RDF	fast FPGA based coprocessor, hard real time search, dual port memories, programmable message driven multi port memories, sequential requests, data acquisition systems, hard real time requirements, DAC systems, coprocessor architectures, file descriptor table, implementation costs, TI DSP C40, hardware strategy, dual port memory, generic searching coprocessor, field programmable gate arrays, hardware implementation, computer systems, high throughput, searching strategy, design approach, DPMs
47	Farzin Karimi, Fabrizio Lombardi, V. Swamy Irrinki, T. Crosby	A Parallel Approach for Testing Multi-Port Static Random Access Memories.	MTDT	2001	DBLP DOI BibTeX RDF
43	Ying Qian, Ahmad Afsahi	Efficient RDMA-based multi-port collectives on multi-rail QsNetII clusters.	IPDPS	2006	DBLP DOI BibTeX RDF
41	Rohan Mandrekar, Madhavan Swaminathan	Delay extraction from frequency domain data for causal macro-modeling of passive networks.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
38	Caixia Liu, Jiaxin Li, Hongli Zhang, Qi Zuo	HHMA: A Hierarchical Hybrid Memory Architecture Sharing Multi-Port Memory.	ICYCS	2008	DBLP DOI BibTeX RDF
38	Chittaranjan A. Mandal, P. P. Chakrabarti 0001, Sujoy Ghose	Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.	VLSI Design	1996	DBLP DOI BibTeX RDF	Multi-port Memory, Genetic Algorithm, VLSI, Binding, Data Path Synthesis
36	Ying Qian, Ahmad Afsahi	Efficient shared memory and RDMA based collectives on multi-rail QsNetII SMP clusters.	Clust. Comput.	2008	DBLP DOI BibTeX RDF	Multi-rail networks, Clusters, Shared-memory, Collective communications, SMP, RDMA
35	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
35	Ying Qian, Ahmad Afsahi	High Performance RDMA-based Multi-port All-gather on Multi-rail QsNet II.	HPCS	2007	DBLP DOI BibTeX RDF
34	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	Automatic March Tests Generation for Multi-Port SRAMs.	DELTA	2006	DBLP DOI BibTeX RDF
34	Yulin Wang, Guangjun Li, Shuisheng Lin, Xiaojun Wu	A write-prior partitioning LRU algorithm for the multi-port cache in disk arrays.	CIT	2005	DBLP DOI BibTeX RDF
33	Hassan Bajwa, Isaac G. Macwan, Vignesh Veerapandian, Xinghao Chen 0005	VHDL Implementation of High-Performance and Dynamically Configures Multi-port Cache Memory.	ITNG	2010	DBLP DOI BibTeX RDF	Dynamically configured memory, Multi-port Cache Architecture, VHDL, SRAM
33	Ying Qian, Ahmad Afsahi	RDMA-based and SMP-aware Multi-port All-Gather on Multi-rail QsNet^II SMP Clusters.	ICPP	2007	DBLP DOI BibTeX RDF
32	Said Hamdioui, Ad J. van de Goor	March Tests for Word-Oriented Two-Port Memories.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
30	Albert Ko, T. L. Lau, Henry Y. K. Lau	Topological Representation and Analysis Method for Multi-port and Multi-orientation Docking Modular Robots.	ICRA	2004	DBLP DOI BibTeX RDF
29	Hoseok Chang, Junho Cho, Wonyong Sung	Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-bank memory, Vectorizing compiler, Data allocation, On-chip memory, SIMD processor
29	Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala	Parallel Memory Architecture for TTA Processor.	SAMOS	2007	DBLP DOI BibTeX RDF
29	Olivier Beaumont, Nicolas Bonichon, Lionel Eyraud-Dubois	Scheduling divisibleworkloads on heterogeneous platforms under bounded multi-port model.	IPDPS	2008	DBLP DOI BibTeX RDF
29	Tuomas Järvinen, Jarmo Takala, David Akopian, Jukka Saarinen	Register-based multi-port perfect shuffle networks.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
25	Yanyang Zhao, Ligen Wang, Jean-François Frigon, Chahé Nerguizian, Ke Wu, Renato G. Bosisio	A Software Defined Radio Receiver Architecture for UWB Communications and Positioning.	CCECE	2006	DBLP DOI BibTeX RDF
25	Kimish Patel, Enrico Macii, Massimo Poncino	Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.	DATE	2004	DBLP DOI BibTeX RDF
23	Biswarup Mukherjee 0002, Fabrizio Sossan	Optimal Planning of Single-Port and Multi-Port Charging Stations for Electric Vehicles in Medium Voltage Distribution Networks.	IEEE Trans. Smart Grid	2023	DBLP DOI BibTeX RDF
23	Biswarup Mukherjee 0002, Fabrizio Sossan	Optimal Planning of Single-Port and Multi-Port Charging Stations for Electric Vehicles in Medium Voltage Distribution Networks.	CoRR	2021	DBLP BibTeX RDF
23	Hardik B. Jain, Matthew Edwards 0002, Ethan R. Elenberg, Ankit Singh Rawat, Sriram Vishwanath	Achieving Multi-Port Memory Performance on Single-Port Memory with Coding Techniques.	CoRR	2020	DBLP BibTeX RDF
23	Hardik B. Jain, Matthew Edwards 0002, Ethan R. Elenberg, Ankit Singh Rawat, Sriram Vishwanath	Achieving Multi-port Memory Performance on Single-Port Memory with Coding Techniques.	ICICT	2020	DBLP DOI BibTeX RDF
23	Qiaofu Zhang	A fast algorithm for optimal port-combination of multi-port coil in high-field MRI.	BMEI	2014	DBLP DOI BibTeX RDF
23	Farshad Khunjush, David Gong, Nikitas J. Dimopoulos	Single-port and multi-port collective communication operations on single and dual Cell BE processor systems.	Int. J. Commun. Networks Distributed Syst.	2011	DBLP DOI BibTeX RDF
23	Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan	A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.	ISQED	2010	DBLP DOI BibTeX RDF
23	Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu	Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.	DAC	2001	DBLP DOI BibTeX RDF
22	Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan	Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
21	Xiaoji Ye, Peng Li 0001, Min Zhao 0001, Rajendran Panda, Jiang Hu	Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.	ICCAD	2007	DBLP DOI BibTeX RDF
21	Xinping Huang, Mario Caron	Benefit of linearizing power amplifiers in multi-port amplifier subsystems.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	A Flexible Multi-port Caching Scheme for Reconfigurable Platforms.	ARC	2006	DBLP DOI BibTeX RDF
21	Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout	A multi-port current source model for multiple-input switching effects in CMOS library cells.	DAC	2006	DBLP DOI BibTeX RDF	MCSM, cell library characterization, multiple input switching, timing analysis, current source model, cell model
21	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
21	Yang Li, Qian He, Xiumei Fan	Integration of Routing and Switching in Delay-Disruption Tolerance Network.	MSN	2009	DBLP DOI BibTeX RDF	Delay/Disruption Tolerance Network, integration, uncertainty, multi-hop, multi-port
21	Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen 0005, Bruce McGaughy	DeMOR: decentralized model order reduction of linear networks with massive ports.	DAC	2008	DBLP DOI BibTeX RDF	multi-port networks, decentralized, model order reduction
21	Peng Li 0001, Weiping Shi	Model order reduction of linear networks with massive ports via frequency-dependent port packing.	DAC	2006	DBLP DOI BibTeX RDF	multi-port networks, model order reduction
21	Said Hamdioui, Ad J. van de Goor	Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	multi-port memories, single-port memories, address decoder faults, read-only ports, write-only ports, fault models, fault coverage, march tests
21	Kanad Chakraborty, Pinaki Mazumder	New March Tests for Multiport RAM Devices.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	multi-port RAM, simplex and duplex coupling faults, concurrent coupling faults
21	Zheng-Ru Lin, Ming-Syan Chen	An Asymptotically Optimal Multi-Layered Decentralized Consensus Protocol with an Initiator.	ICDCS	2000	DBLP DOI BibTeX RDF	multi-port communication, distributed systems, performance analysis, Consensus protocol
21	Said Hamdioui, Ad J. van de Goor	Consequences of port restrictions on testing two-port memories.	ITC	1998	DBLP DOI BibTeX RDF	Multi-port memories, single-port memories, memory fault models, weak faults, read-only and write-only ports, fault coverage, march tests, test length
21	Allan Borodin, Prabhakar Raghavan, Baruch Schieber, Eli Upfal	How much can hardware help routing?	J. ACM	1997	DBLP DOI BibTeX RDF	randomized routing algorithms, single-port, packet routing, permutation routing, multi-port
16	Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda	Power Reduction in VLIW Processor with Compiler Driven Bypass Network.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Roland W. Freund	SPRIM: structure-preserving reduced-order interconnect macromodeling.	ICCAD	2004	DBLP DOI BibTeX RDF
16	Janet Meiling Wang, Tuyen V. Nguyen	Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources.	DAC	2000	DBLP DOI BibTeX RDF
16	Roland W. Freund, Peter Feldmann	Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation.	DATE	1998	DBLP DOI BibTeX RDF	linear passive multi-terminal circuit, matrix-Pade approximants, Lanczos-type process, interconnect analysis, simulation, synthesis, transfer function
15	Nils L. Johannsen, Jan Mietzner, Peter A. Hoeher	Joint Communication and Sensing Using Compressive Sensing and a Single Multi-Mode Multi-Port Antenna.	IEEE Open J. Commun. Soc.	2024	DBLP DOI BibTeX RDF
15	Yunus Demir	An efficient lexicographic approach to solve multi-objective multi-port fabric dyeing machine planning problem.	Appl. Soft Comput.	2023	DBLP DOI BibTeX RDF
15	Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu 0001, Leibo Liu, Shaojun Wei, Shouyi Yin	RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA.	DAC	2023	DBLP DOI BibTeX RDF
15	Nils L. Johannsen, Lukas Grundmann, Dirk Manteuffel, Peter A. Hoeher	Aircraft Transponder Signaling Concepts Using Multi-Mode Multi -Port Antenna.	ICTC	2022	DBLP DOI BibTeX RDF
15	Gang Zhang 0004, Zhenyao Qian, Xinde Zhang, Jiquan Yang	A General and Effective Design Method of Multi-Way Filtering Power Dividers on a New Multi-Port Topology for Industrial Application.	IEEE Trans. Ind. Electron.	2021	DBLP DOI BibTeX RDF
15	Edwin H.-M. Sha, Mingrui Xu, Shouzhen Gu, Qingfeng Zhuge	Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system.	J. Syst. Archit.	2021	DBLP DOI BibTeX RDF
15	Haojun Qin, Huan Zhang, Ming Liu 0013, Chengbin Ma	Comparison of Different Multi-winding Transformer Models in Multi-port AC-coupled Converter Application.	IECON	2021	DBLP DOI BibTeX RDF
15	Mark T. Wade, Erik Anderson, Shahab Ardalan, Woorham Bae, Behrooz Beheshtian, Sidney Buchbinder, Ken Chang, Paulo Chao, Haritha Eachempatti, John Frey, Eric Jan, Austin Katzin, Anatoly Khilo, Derek Kita, Uma Krishnamoorthy, Chen Li 0044, Haiwei Lu, Fernando Luna, Christopher Madden, Lynne Okada, Mukundrai Patel, Chandru Ramamurthy, Manan Raval, Radek Roucka, Kit Robberson, Michael Rust, Derek Van Orden, Ron Zeng, Mason Zhang, Vladimir Stojanovic, Forrest Sedgwick, Roy Meade, Norman Chan, John Michael Fini, Byungchae Kim, Songtao Liu, Chong Zhang, Daniel Jeong, Pavan Bhargava, Matthew Sysak, Chen Sun 0003	An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi-port Laser.	OFC	2021	DBLP BibTeX RDF
15	Xuyang Lu, ChandraKanth Reddy Chappidi, Xue Wu 0001, Kaushik Sengupta	Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Receivers and Antennas.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
15	ChandraKanth Reddy Chappidi, Xuyang Lu, Xue Wu 0001, Kaushik Sengupta	Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Transmitters and Antennas.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
15	Sergio Luis Brockveld, Caio Guilherme da Silva Moraes, Pedro P. Cavilha, Antonio L. S. Pacheco, Marcelo Lobo Heldwein, Gierri Waltrich	Multi-Port System for Braking Energy Recovery in Diesel-Electric Locomotives - Focus on the Multi-Interphase Transformer Design.	IECON	2019	DBLP DOI BibTeX RDF
15	Zhongxu Wang, Huai Wang, Yi Zhang 0043, Frede Blaabjerg	A multi-port thermal coupling model for multi-chip power modules suitable for circuit simulators.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
15	Shouzhen Gu, Qingfeng Zhuge, Juan Yi, Jingtong Hu, Edwin Hsing-Mean Sha	Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs.	IEEE Trans. Parallel Distributed Syst.	2015	DBLP DOI BibTeX RDF
15	Carlos Crespo-Cadenas, Javier Reina-Tosina, María J. Madero-Ayora, Michel Allegue-Martínez	A closed-form equation approach to multi-port/multi-zone behavioral modeling of GaN FET Amplifiers.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
15	Carlos Crespo-Cadenas, Javier Reina-Tosina, María J. Madero-Ayora, Michel Allegue-Martínez	A Volterra-Based Procedure for Multi-Port and Multi-Zone GaN FET Amplifier CAD Simulation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
15	Hasan Erdem Yantir, Salih Bayar, Arda Yurdakul	Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs.	DSD	2013	DBLP DOI BibTeX RDF
15	Ricardo Martins 0003, Nuno Lourenço 0003, António Canelas, Nuno Horta	Multi-port multi-terminal analog router based on an evolutionary optimization kernel.	IEEE Congress on Evolutionary Computation	2013	DBLP DOI BibTeX RDF
15	Hyun-Wook Jin, Yeon-Ji Yun, Hye-Churn Jang	TCP/IP Performance Near I/O Bus Bandwidth on Multi-Core Systems: 10-Gigabit Ethernet vs. Multi-Port Gigabit Ethernet.	ICPP Workshops	2008	DBLP DOI BibTeX RDF
15	Dan Zhao, Ronghua Huang, Hideo Fujiwara	Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE.	ATS	2007	DBLP DOI BibTeX RDF
15	Wen-Tsong Shiue, Chaitali Chakrabarti	Multi-Module Multi-Port Memory Design for Low Power Embedded Systems.	Des. Autom. Embed. Syst.	2004	DBLP DOI BibTeX RDF
15	San-Yuan Wang, Yu-Chee Tseng, Sze-Yao Ni, Jang-Ping Sheu	Circuit-Switched Broadcasting in Multi-Port Multi-Dimensional Torus Networks.	J. Supercomput.	2001	DBLP DOI BibTeX RDF
15	San-Yuan Wang, Yu-Chee Tseng, Sze-Yao Ni, Jang-Ping Sheu	Circuit-Switched Broadcasting in Multi-port Multi-dimensional Torus Networks.	Euro-Par	1999	DBLP DOI BibTeX RDF
15	Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar	Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
14	Yossi Azar, Uriel Feige, Iftah Gamzu, Thomas Moscibroda, Prasad Raghavendra	Buffer management for colored packets with deadlines.	SPAA	2009	DBLP DOI BibTeX RDF	dram scheduling, online algorithms, buffer management, packets scheduling, earliest deadline first
14	Feng Li, Chunhua Tian, Rongzeng Cao, Wei Ding 0002	An Integer Linear Programming for Container Stowage Problem.	ICCS (1)	2008	DBLP DOI BibTeX RDF	Container Stowage Planning, Integer Programming
14	Preeti Ranjan Panda	Abridged addressing: a low power memory addressing strategy.	ASP-DAC	2006	DBLP DOI BibTeX RDF
14	Rong Jiang 0002, Tsung-Hao Chen, Charlie Chung-Ping Chen	PODEA: Power delivery efficient analysis with realizable model reduction.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
14	Stefano Pastore, Amedeo Premoli	DC analysis of PWL electric networks and sub-networks by means of set theory.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
14	Xuemei Zhao, Yizheng Ye	Design and Realization of a Low Power Register File Using Energy Model.	PATMOS	2002	DBLP DOI BibTeX RDF
14	Chien-Min Wang, Yomin Hou, Lih-Hsing Hsu	Adaptive Path-Based Multicast on Wormhole-Routed Hypercubes.	Euro-Par	2002	DBLP DOI BibTeX RDF
14	Anirudh Devgan, Peter R. O'Brien	Realizable reduction for RC interconnect circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
14	Taewhan Kim, C. L. Liu 0001	An integrated algorithm for incremental data path synthesis.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
14	William Siler, John S. Laughlin	A computer method for radiation treatment planning.	Commun. ACM	1962	DBLP DOI BibTeX RDF
13	Rakesh Sinha	Correction to "Design of Multi-Port With Desired Reference Impedances Using Y-Matrix and Matching Networks".	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
13	Sundar R, Senthil Kumar M	A novel isolated multi-port interleaved flyback converter operated TPSL-DVR for smallscale distribution system.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
13	Oleksandr Nonik, Nadiia Lobanchykova, Tetiana A. Vakaliuk, Viacheslav Osadchyi, Oleksandr Farrakhov	Approaches to Solving Proxy Performance Problems for HTTP and SOCKS5 Protocols for the Case of Multi-Port Passwordless Access.	CPITS	2024	DBLP BibTeX RDF
13	R. Aravind 0002, Bharatiraja Chokkalingam, Lucian Mihet-Popa	A Transformerless Non-Isolated Multi-Port DC-DC Converter for Hybrid Energy Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Shaik Reddi Khasim, Dhanamjayulu Chittathuru, S. M. Muyeen	A Single Inductor Multi-Port Power Converter for Electric Vehicle Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Peng Zhou, Longxin Lin, Tengjiao He, Zhen Zhang 0017	GHDC: a dual-centric data center network architecture by using multi-port servers with greater incremental scalability.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
13	Purevtseren Bayarsaikhan, Ryuji Kuse, Takeshi Fukusako, Kazuma Tomimoto, Masayuki Miyashita, Ryo Yamaguchi	Aperture-Shared Multi-Port Waveguide Antenna with Rectangular Dielectric Resonator for 5G Applications.	IEICE Trans. Commun.	2023	DBLP DOI BibTeX RDF
13	Takumi Kobayashi, Tetsuya Akagi, Shujiro Dohta, Feifei Cho, Takashi Shinohara, Masashi Yokota	Slide-Gate Type Multi-Port Switching Valve.	J. Robotics Mechatronics	2023	DBLP DOI BibTeX RDF
13	Limin Hao, Guoyong Shi	Realizable Reduction of Multi-Port RCL Networks by Block Elimination.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Sina Ahmadian, Siroos Hemmati, Vahid Abbasi	Multi-port single-phase inverter considering battery-alone mode for stand-alone applications.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
13	Muhammad Zeeshan Malik, Shiqing Zhang, Amjad Ali 0005, Ajmal Farooq	Design and implementation of a multi-port bidirectional converter for electric vehicle applications.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF