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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4193 occurrences of 1488 keywords
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Results
Found 3723 publication records. Showing 3723 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
59 | Christopher Connelly, Carla Schlatter Ellis |
A workload characterization for coarse-grain multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 393-397, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
coarse-grain multiprocessors, associated coherency maintenance, memory blocks, cache-coherent multiprocessors, page-based distributed shared memory systems, fine-grain systems, performance evaluation, performance, scalability, replication, multiprocessing systems, workload characterization, granularity, scalable shared memory multiprocessors |
50 | Alberto Ros 0001, Manuel E. Acacio, José M. García 0001 |
An efficient cache design for scalable glueless shared-memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 321-330, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
L2, directory structure, glueless shared-memory multiprocessors, cache, cache coherence, memory wall |
50 | Ravi R. Iyer 0001, Laxmi N. Bhuyan |
Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(8), pp. 779-797, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures |
50 | Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve |
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(2), pp. 218-226, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
performance evaluation, instruction-level parallelism, Shared-memory multiprocessors, software prefetching |
50 | Gyungho Lee |
An assessment of COMA multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 388-392, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate |
47 | Anders Landin, Fredrik Dahlgren |
Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 95-105, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bus-based COMA, standard UMA architecture, program-driven simulation, SPLASH, cache only memory architecture, shared-memory multiprocessors, shared memory systems, memory architecture, cache storage, shared-bus multiprocessors |
47 | Yang Zeng, Santosh G. Abraham |
Partitioning regular grid applications with irregular boundaries for cache-coherent multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 222-228, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
partitioning regular grid applications, irregular boundaries, cache-coherent multiprocessors, regular grid, domain decomposition techniques, message passing multiprocessors, false coherency traffic, cache line, coalescing algorithm, domain decomposition algorithm, Indian Ocean circulation application, KSR1 multiprocessor, coherency traffic, message passing, multiprocessing systems, interprocessor communication |
43 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan |
Compiler directed network-on-chip reliability enhancement for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 85-94, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, compiler, noc, chip multiprocessors |
43 | Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim |
Age based scheduling for asymmetric multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2009, November 14-20, 2009, Portland, Oregon, USA, 2009, ACM, 978-1-60558-744-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
age based scheduling, asymmetric multiprocessors, thread scheduling |
43 | Chris R. Jesshope |
muTC - An Intermediate Language for Programming Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 147-160, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Self-adaptive computing, data-driven com-putation, programming chip multiprocessors, concurrent languages |
43 | Evangelos P. Markatos, Thomas J. LeBlanc |
Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(4), pp. 379-400, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
processoraffinity, kernel programs, Silicon Graphics multiprocessor, BBN Butterfly, SequentSymmetry, KSR-1, scheduling, performance evaluation, synchronization, shared-memory multiprocessors, shared memory systems, iterations, performance improvements, communication overhead, loop scheduling, loop iterations, load imbalance |
43 | Eran Gabber |
VMMP: A Practical Tool for the Development of Portable and Efficient Programs for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(3), pp. 304-317, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
VMMP, practical tool, portable and efficient programs, parallel application programs, message passing multiprocessors, VROMP, parallel algorithms, synchronization, virtual machine, software tools, shared memory, multiprocessing systems, coding, software portability, software package |
41 | Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan |
Heterogeneous Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(11), pp. 32-38, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Multicore microprocessors, Multiprocessors, Chip multiprocessors, CMP, Heterogeneity, System architectures, Power-aware computing |
41 | Jonas Skeppstedt, Michel Dubois 0001 |
Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 298-305, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
hybrid compiler/hardware prefetching, low-overhead cache miss traps, data prefetching technique, cache coherent multiprocessors, cache miss traps, trap handler, simulated multiprocessor, compiler, multiprocessors, multiprocessing systems |
41 | Steven L. Scott, James R. Goodman |
Performance of Pruning-Cache Directories for Large-Scale Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(5), pp. 520-534, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
pruning-cache directories, multilevel inclusion, n-cube topology, bottleneck-free communication, multiprocessor interconnection networks, shared-memory multiprocessors, shared memory systems, storage management, memory architecture, buffer storage, large-scale multiprocessors |
39 | Ravi R. Iyer 0001, Jack Perdue, Lawrence Rauchwerger, Nancy M. Amato, Laxmi N. Bhuyan |
An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(4), pp. 307-350, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance analysis, Parallel architectures, shared memory |
39 | James Laudon, Anoop Gupta, Mark Horowitz |
Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994., pp. 308-318, 1994, ACM Press, 0-89791-660-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin |
Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 87-92, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data compression, chip multiprocessors, optimizing compiler |
36 | Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero |
Evaluating kilo-instruction multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMPI ![In: Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with the 31st International Symposium on Computer Architecture 2004, Munich, Germany, June 20, 2004, pp. 72-79, 2004, ACM, 1-59593-040-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ROB, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, kilo-instruction processors |
36 | Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero |
A first glance at Kilo-instruction based multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 212-221, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors |
36 | Sanjoy K. Baruah, Shelby H. Funk, Joël Goossens |
Robustness Results Concerning EDF Scheduling upon Uniform Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(9), pp. 1185-1195, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Uniform multiprocessors, robustness, earliest deadline first, hard-real-time systems, resource augmentation |
36 | Marcelo H. Cintra, Josep Torrellas |
Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 43-54, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Shared-Memory Multiprocessors, Speculative Parallelization |
36 | Takahiro Koita, Tetsuro Katayama, Keizo Saisho, Akira Fukuda |
Memory Conscious Scheduling for Cluster-based NUMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 16(3), pp. 217-235, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dynamic space-sharing, page placement, cluster-based NUMA multiprocessors, multiprogrammed environments, processor scheduling |
36 | Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta, Eduard Ayguadé |
UPMLIB: A Runtime System for Tuning the Memory Performance of OpenMP Programs on Scalable Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCR ![In: Languages, Compilers, and Run-Time Systems for Scalable Computers, 5th International Workshop, LCR 2000, Rochester, NY, USA, May 25-27, 2000, Selected Papers, pp. 85-99, 2000, Springer, 3-540-41185-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
operating systems, memory management, OpenMP, runtime systems, scalable shared-memory multiprocessors |
36 | David A. Koufaty, Josep Torrellas |
Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 181-191, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
cache hierarchy performance, compiler algorithms to hide memory latency, shared-memory multiprocessors, cache coherence protocols, data forwarding |
36 | Edouard Bugnion, Scott Devine, Kinshuk Govil, Mendel Rosenblum |
Disco: Running Commodity Operating Systems on Scalable Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 15(4), pp. 412-447, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
virtual machines, scalable multiprocessors |
36 | James H. Anderson, Rohit Jain, Srikanth Ramamurthy |
Wait-free object-sharing schemes for real-time uniprocessors and multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), December 3-5, 1997, San Francisco, CA, USA, pp. 111-122, 1997, IEEE Computer Society, 0-8186-8268-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
wait-free object-sharing schemes, real-time uniprocessors, real-time multiprocessors, priority inheritance protocol, breakdown utilization experiments, lock-based schemes, multiprocessing systems, nonblocking, user level, priority ceiling protocol |
36 | Naraig Manjikian |
Combining Loop Fusion with Prefetching on Shared-memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 78-83, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Cache locality enhancement, Compilers, Prefetching, Shared-memory multiprocessors, Loop transformations |
36 | David A. Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas |
Data Forwarding in Scalable Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(12), pp. 1250-1264, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Memory latency hiding, forwarding and prefetching, multiprocessor caches, address trace analysis, scalable shared-memory multiprocessors |
36 | Anant Agarwal, David A. Kranz, Venkat Natarajan |
Automatic Partitioning of Parallel Loops and Data Arrays for Distributed Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(9), pp. 943-962, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Automatic loop partitioning, minimizing communication, compilers, shared-memory multiprocessors, tiling |
36 | Sandhya Dwarkadas, J. Robert Jump, James B. Sinclair |
Execution-Driven Simulation of Multiprocessors: Address and Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Model. Comput. Simul. ![In: ACM Trans. Model. Comput. Simul. 4(4), pp. 314-338, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
parallel tracing, distributed systems, shared-memory multiprocessors, execution-driven simulation |
36 | Oscar G. Plata, Francisco F. Rivera |
Combining static and dynamic scheduling on distributed-memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 8th international conference on Supercomputing, ICS 1994, Manchester, UK, July 11-15, 1994, pp. 186-195, 1994, ACM, 0-89791-665-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
dynamic and static scheduling, load balancing, message-passing, distributed-memory multiprocessors, loop scheduling |
36 | Montse Peiron, Mateo Valero, Eduard Ayguadé |
Synchronized access to streams in SIMD vector multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 8th international conference on Supercomputing, ICS 1994, Manchester, UK, July 11-15, 1994, pp. 23-32, 1994, ACM, 0-89791-665-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
SIMD vector multiprocessors, multi-module memories, vectors with constant stride, interconnection networks, conflict-free access |
36 | Peter F. Corbett, Isaac D. Scherson |
Sorting in Mesh Connected Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(5), pp. 626-632, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
MeshSort, multidimensional mesh-connected multiprocessors, ShearSort, orthogonal vectors, reduced architecture, multidimensional memory structure, FastMeshSort, parallel algorithms, multiprocessor interconnection networks, sorting, routing algorithm, parallel sorting, sorting algorithm, Bitonic Sort |
34 | Nian-Feng Tzeng, Shiwa S. Fu |
Efficient implementation of mutual exclusion locks in large multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 270-275, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
mutual exclusion locks, large multiprocessors, hot-spot contention, tree of locks, data structures, distributed algorithms, synchronization, concurrency control, multiprocessors, mutual exclusion, multistage interconnection networks, contention, rings, critical sections |
34 | Thomas E. Anderson |
The Performance of Spin Lock Alternatives for Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(1), pp. 6-16, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
software queueing, CSMA network protocols, Ethernet backoff, Symmetry Model B, spinlock alternatives, shared-money multiprocessors, atomic instructions, softwarespin-waiting algorithms, dynamic arbitration, parallelprocessing, performance evaluation, distributed system, delays, storage management, multistage interconnection network, shared data structures, shared bus multiprocessors |
34 | Rhys S. Francis, Ian D. Mathieson |
A Benchmark Parallel Sort for Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(12), pp. 1619-1626, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
Sequent Balance 21000 System, parallel algorithms, benchmark, multiprocessors, sorting, shared memory multiprocessors, MIMD, computer testing, parallel sort, sort algorithm |
34 | David A. Padua, David J. Kuck, Duncan H. Lawrie |
High-Speed Multiprocessors and Compilation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(9), pp. 763-776, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
high-speed multiprocessors, parallel processing, compilers, interconnection networks, multiprocessors, pipelining, vectorizers, Automatic translation |
34 | Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve |
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 72-83, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | John L. Gustafson |
Reevaluating Amdahl's Law. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 31(5), pp. 532-533, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
32 | Yu Zhang, Alex K. Jones |
Non-uniform fat-meshes for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Jinpeng Wei, Calton Pu |
Multiprocessors May Reduce System Dependability under File-Based Race Condition Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, 25-28 June 2007, Edinburgh, UK, Proceedings, pp. 358-367, 2007, IEEE Computer Society, 0-7695-2855-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Probabilistic Modeling, Race Condition |
32 | Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé |
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 5(1), pp. 14-17, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Shih-Wei Liao |
Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 189-202, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reduction recognition, implicit reductions, user-defined reductions, parallelization, multiprocessor, multicore, Reduction, data flow analysis, interprocedural analysis |
32 | Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen |
An Optimal Real-Time Scheduling Algorithm for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 5-8 December 2006, Rio de Janeiro, Brazil, pp. 101-110, 2006, IEEE Computer Society, 0-7695-2761-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Shelby H. Funk, Sanjoy K. Baruah |
Task Assignment on Uniform Heterogeneous Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 17th Euromicro Conference on Real-Time Systems (ECRTS 2005), 6-8 July 2005, Palma de Mallorca, Spain, Proceedings, pp. 219-226, 2005, IEEE Computer Society, 0-7695-2400-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Ravi R. Iyer 0001, Laxmi N. Bhuyan |
Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 152-160, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Dimitris Dimitrelos, Constantine Halatsis |
Improving the Performance of Distributed Shared Memory Environments on Grid Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, pp. 159-162, 1999, Springer, 3-540-66443-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | David R. Helman, Joseph F. JáJá |
Designing Practical Efficient Algorithms for Symmetric Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ALENEX ![In: Algorithm Engineering and Experimentation, International Workshop ALENEX '99, Baltimore, MD, USA, January 15-16, 1999, Selected Papers, pp. 37-56, 1999, Springer, 3-540-66227-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Tao Li, Ben-Wei Rong |
A Versatile Directory Scheme(Dir2NB+L) and Its Implementation on BY91-1 Multiprocessors System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APDC ![In: Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), March 19-21, 1997, Shanghai, China, pp. 180-185, 1997, IEEE Computer Society, 0-8186-7876-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Bryan S. Rosenburg |
Low-Synchronization Translation Lookaside Buffer Consistency in Large-Scale Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOSP ![In: Proceedings of the Twelfth ACM Symposium on Operating System Principles, SOSP 1989, The Wigwam, Litchfield Park, Arizona, USA, December 3-6, 1989, pp. 137-146, 1989, ACM, 0-89791-338-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Christoph Scheurich, Michel Dubois 0001 |
The design of a lockup-free cache for high-performance multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, pp. 352-359, 1988, IEEE Computer Society, 0-8186-0882-X. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
31 | Guy E. Blelloch, Phillip B. Gibbons, Harsha Vardhan Simhadri |
Brief announcement: low depth cache-oblivious sorting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2009: Proceedings of the 21st Annual ACM Symposium on Parallelism in Algorithms and Architectures, Calgary, Alberta, Canada, August 11-13, 2009, pp. 121-123, 2009, ACM, 978-1-60558-606-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
schedulers, parallel algorithms, multiprocessors, sorting, merging, cache-oblivious algorithms |
31 | Tao Li 0006, Lizy Kurian John |
ADir_pNB: A Cost-Effective Way to Implement Full Map Directory-Based Cache Coherence Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(9), pp. 921-934, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
directory protocols, computer architecture, shared memory multiprocessors, Cache coherence |
31 | Donald Yeung, John Kubiatowicz, Anant Agarwal |
Multigrain shared memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 18(2), pp. 154-196, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
symmetric multiprocessors, distributed memory, system of systems |
31 | S. Muthukrishnan 0001, Rajmohan Rajaraman, Anthony Shaheen, Johannes Gehrke |
Online Scheduling to Minimize Average Stretch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 40th Annual Symposium on Foundations of Computer Science, FOCS '99, 17-18 October, 1999, New York, NY, USA, pp. 433-442, 1999, IEEE Computer Society, 0-7695-0409-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
scheduling, multiprocessors, online algorithms, competitive analysis |
31 | Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen |
Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 15(3), pp. 322-354, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference |
31 | Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen |
Tuning Compiler Optimizations for Simultaneous Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 114-124, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cyclic algorithm, fine-grained sharing, inter-thread instruction-level parallelism, loop-iteration scheduling, memory system resources, software speculative execution, performance, parallel programs, parallel architecture, compiler optimizations, shared-memory multiprocessors, processor architecture, instructions, simultaneous multithreading, latency hiding, loop tiling, optimising compilers, inter-processor communication, cache size |
30 | Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001 |
Replication-aware leakage management in chip multiprocessors with private L2 cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 135-140, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
leakage power management, chip multiprocessors, L2 caches |
30 | Ayse K. Coskun, Richard D. Strong, Dean M. Tullsen, Tajana Simunic Rosing |
Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS/Performance ![In: Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems, SIGMETRICS/Performance 2009, Seattle, WA, USA, June 15-19, 2009, pp. 169-180, 2009, ACM, 978-1-60558-511-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reliability, chip multiprocessors, thermal management, simulation methodology |
30 | Jinglei Wang, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001 |
An Efficient Lightweight Shared Cache Design for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 28-40, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Directory-based Cache Coherence Protocol, Lightweight Shared Cache, Chip Multiprocessors (CMP) |
30 | Hongyang Sun 0001, Yangjie Cao, Wen-Jing Hsu |
Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 99-108, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
batched parallel jobs, non-clairvoyant, power budget, simulations, scheduling, multiprocessors, energy consumption, flow time, speed scaling |
30 | Seung Woo Son 0001, Mahmut T. Kandemir, Mustafa Karaköy, Dhruva R. Chakrabarti |
A compiler-directed data prefetching scheme for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 209-218, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compiler, chip multiprocessors, prefetching, helper thread |
30 | Xiangrong Zhou, Chenjie Yu, Alokika Dash, Peter Petrov |
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 16:1-16:25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
snoop filtering, Cache coherence, low-power embedded systems, embedded multiprocessors |
30 | Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang 0001 |
Improving support for locality and fine-grain sharing in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 155-165, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ARMCO, L1-to-L1 direct access, fine-grain sharing, chip multiprocessors, cache coherence |
30 | Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni |
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 31-40, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics |
30 | Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser |
Utilizing shared data in chip multiprocessors with the nahalal architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June 14-16, 2008, pp. 1-10, 2008, ACM, 978-1-59593-973-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
chip multiprocessors, cache memories |
30 | Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee |
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 60-69, 2008, ACM, 978-1-59593-958-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors |
30 | Lisa Higham, LillAnne Jackson, Jalal Kawash |
Specifying memory consistency of write buffer multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 25(1), pp. 1, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Memory consistency framework, partial store order, relaxed memory order, sparc multiprocessors, total store order, write-buffer architectures, coherence, sequential consistency, alpha |
30 | Yu Murata, Wataru Kanda, Kensuke Hanaoka, Hiroo Ishikawa, Tatsuo Nakajima |
A Study on Asymmetric Operating Systems on Symmetric Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 182-195, 2007, Springer, 978-3-540-77091-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Multiple OSes Environment, InterProcessor Interrupts, InterOS Communications, Operating Systems, Symmetric Multiprocessors |
30 | David K. Tam, Reza Azimi, Michael Stumm |
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, pp. 47-58, 2007, ACM, 978-1-59593-636-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cache behavior, detecting sharing, performance monitoring unit, single-chip multiprocessors, thread placement, resource allocation, CMP, multithreading, sharing, SMP, simultaneous multithreading, SMT, shared caches, cache locality, thread scheduling, thread migration, hardware performance monitors, hardware performance counters, affinity scheduling |
30 | Rakesh Kumar 0002, Dean M. Tullsen, Norman P. Jouppi |
Core architecture optimization for heterogeneous chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 23-32, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
computer architecture, multi-core architectures, heterogeneous chip multiprocessors |
30 | Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk 0001 |
An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCIS ![In: Computer and Information Sciences - ISCIS 2006, 21th International Symposium, Istanbul, Turkey, November 1-3, 2006, Proceedings, pp. 267-276, 2006, Springer, 3-540-47242-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Reliability, DVS, energy minimization, duplication, heterogeneous chip multiprocessors |
30 | Xiaogang Qiu, Michel Dubois 0001 |
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(7), pp. 612-623, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory |
30 | María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas |
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 2(3), pp. 247-279, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Caching and buffering support, memory hierarchies, shared-memory multiprocessors, thread-level speculation, coherence protocol |
30 | Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir |
Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 12th Euromicro Workshop on Parallel, Distributed and Network-Based Processing (PDP 2004), 11-13 February 2004, A Coruna, Spain, pp. 340-, 2004, IEEE Computer Society, 0-7695-2083-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
On-chip Multiprocessors, Power Optimization, Value Locality |
30 | Valentin Puente, José A. Gregorio, Ramón Beivide, Cruz Izu |
On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(5), pp. 487-501, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hardware router design, Interconnection networks, shared memory multiprocessors, adaptive routing |
30 | Masaru Takesue |
Software Queue-Based Algorithms for Pipelined Synchronization on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 32nd International Conference on Parallel Processing Workshops (ICPP 2003 Workshops), 6-9 October 2003, Kaohsiung, Taiwan, pp. 115-122, 2003, IEEE Computer Society, 0-7695-2018-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
queue-based locks, algorithms, synchronization, Multiprocessors, pipelining |
30 | Géraud Krawezik |
Performance comparison of MPI and three openMP programming styles on shared memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 7-9, 2003, San Diego, California, USA (part of FCRC 2003), pp. 118-127, 2003, ACM, 1-58113-661-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
performance evaluation, MPI, multiprocessors, shared memory, openMP |
30 | JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas |
Schedulers as model-based design elements in programmable heterogeneous multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 408-411, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
schedulers, computer-aided design, performance modeling, system modeling, heterogeneous multiprocessors |
30 | Yunheung Paek, Angeles G. Navarro, Emilio L. Zapata, Jay P. Hoeflinger, David A. Padua |
An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(3), pp. 241-259, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
array privatization, noncoherent caches, Put/Get, compiler, multiprocessors, dependence analysis, shared-memory programming |
30 | Milos Prvulovic, Josep Torrellas, Zheng Zhang 0001 |
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 111-122, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fault tolerance, availability, checkpointing, shared-memory multiprocessors, recovery, logging, BER, rollback recovery, parity |
30 | Naraig Manjikian, Tarek S. Abdelrahman |
Exploiting Wavefront Parallelism on Large-Scale Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(3), pp. 259-271, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
High-performance compilers, wavefront parallelism, locality-enhancing loop transformations, large-scale shared-memory multiprocessors, tiling, cache locality |
30 | Kinshuk Govil, Dan Teodosiu 0002, Yongqiang Huang 0002, Mendel Rosenblum |
Cellular disco: resource management using virtual clusters on shared-memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 18(3), pp. 229-262, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
virtual machines, resource managment, fault containment, scalable multiprocessors |
30 | Lynn Choi, Pen-Chung Yew |
Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(4), pp. 375-394, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
performance evaluation, compiler, Computer architecture, shared-memory multiprocessors, cache coherence, memory systems |
30 | Stefanos Kaxiras, Cliff Young |
Coherence Communication Prediction in Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 156-167, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
sharing prediction, screening tests, shared memory multiprocessors |
30 | Oh-Han Kang, Dharma P. Agrawal |
S3MP: A Task Duplication Based Scalable Scheduling Algorithm for Symmetric Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 451-456, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
heuristic, Task scheduling, directed acyclic graph, symmetric multiprocessors, task duplication |
30 | Mukul Khandelia, Shuvra S. Bhattacharyya |
Contention-Conscious Transaction Ordering in Embedded Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 276-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
self-timed scheduling, multiprocessor synchronization, interprocessor communication, dataflow programming, embedded multiprocessors |
30 | Thomas H. Cormen, James C. Clippinger |
Performing BMMC Permutations Efficiently on Distributed-Memory Multiprocessors with MPI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 24(3-4), pp. 349-370, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
BMMC permutations, MPI, Affine transformations, Distributed-memory multiprocessors |
30 | Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee |
On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 203-211, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
loop and memory layout transformations, shared-memory multiprocessors, data reuse, cache locality, false sharing |
30 | Dongho Yoo, Inbum Jung, Seung Ryoul Maeng, Hyunglae Roh |
Multistage Ring Network: A New Multiple Ring Network for Large Scale Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: Proceedings of the 1999 International Conference on Parallel Processing Workshops, ICPPW 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 290-294, 1999, IEEE Computer Society, 0-7695-0353-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Multiple ring network, Interconnection network, Multiprocessors, Ring network |
30 | Kelvin K. Yue, David J. Lilja |
An Effective Processor Allocation Strategy for Multiprogrammed Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(12), pp. 1246-1258, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Parallel loop scheduling, operating system, shared-memory multiprocessors, multiprogramming, processor allocation |
30 | Shiwa S. Fu, Nian-Feng Tzeng |
A Circular List-Based Mutual Exclusion Scheme for Large Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(6), pp. 628-639, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Circular lists, hot-spot contention, tree of locks, multiprocessors, mutual exclusion, critical sections, linked lists |
30 | Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias, Marco Zagha |
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(9), pp. 943-958, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Memory bank contention, memory delays, parallel machine models, parallel algorithms, performance analysis, multiprocessors, shared memory |
30 | Maged M. Michael, Michael L. Scott |
Relative Performance of Preemption-Safe Locking and Non-Blocking Synchronization on Multiprogrammed Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 267-273, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
relative performance, preemption safe locking, non blocking synchronization, multiprogrammed shared memory multiprocessors, inopportune preemption, synchronized parallel applications, concurrent atomic update, non blocking lock free algorithms, kernel support, universal atomic primitive, 12 processor SGI Challenge multiprocessor, multiprogrammed machines, priority queues, multiprogramming, stacks, concurrent data structures, counters, FIFO queues, shared data structures |
30 | Sudarsan Tandri, Tarek S. Abdelrahman |
Automatic Partitioning of Data and Computations on Scalable Shared Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 64-73, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
computation partitioning, scalable, shared memory multiprocessors, automatic parallelization, data distribution, compiler analysis |
30 | Myoung Kwon Tcheun, Hyunsoo Yoon, Seung Ryoul Maeng |
An adaptive sequential prefetching scheme in shared-memory multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 306-313, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
adaptive sequential prefetching scheme, hardware controlled scheme, high sequentiality, shared-memory multiprocessors, shared memory systems, application programs, sequentiality, memory accesses |
30 | Edward D. Moreno, Sergio Takeo Kofuji |
Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 190-197, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness |
30 | Fredrik Dahlgren, Per Stenström |
Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(4), pp. 385-398, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Hardware-controlled prefetching, relaxed memory consistency, performance evaluation, shared-memory multiprocessors, latency tolerance |
30 | Yu-Kwong Kwok, Ishfaq Ahmad |
Dynamic Critical-Path Scheduling: An Effective Technique for Allocating Task Graphs to Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(5), pp. 506-521, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
clustering, Algorithms, multiprocessors, processor allocation, task graphs, list scheduling, parallel scheduling |
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