Search results for "nanoscale"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
110	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
95	Ruojie Sha, Xiaoping Zhang, Shiping Liao, Pamela E. Constantinou, Baoquan Ding, Tong Wang, Alejandra V. Garibotti, Hong Zhong, Lisa B. Israel, Xing Wang, Gang Wu, Banani Chakraborty, Junghuei Chen, Yuwen Zhang, Hao Yan, Zhiyong Shen, Wanqiu Shen, Phiset Sa-Ardyen, Jens Kopatsch, Jiwen Zheng, Philip S. Lukeman, William B. Sherman, Chengde Mao, Natasa Jonoska, Nadrian C. Seeman	Structural DNA Nanotechnology: Molecular Construction and Computation.	UC	2005	DBLP DOI BibTeX RDF	Unusual DNA Motifs, Bottom-Up Nanoscale Construction, Nanoscale DNA Objects, Nanorobotics, Nanoscale Pattern Design, DNA Sequence Design
78	D. Dutta Majumder, Christian Ulrichs, Debosmita Majumder, Inga Mewis, Ashoke Ranjan Thakur, R. L. Brahmachary, Rajat Banerjee, Ayesha Rahman, Nitai Debnath, Dipankar Seth, Sumistha Das, Indrani Roy, Amrita Ghosh, Prity Sagar, Carsten Schulz, Nguyen Quang Linh, Arunava Goswami	Current Status and Future Trends of Nanoscale Technology and Its Impact on Modern Computing, Biology, Medicine and Agricultural Biotechnology.	ICCTA	2007	DBLP DOI BibTeX RDF	hydrophobic nanosilica, lipophilic nanosilica, Nanoscience, nanosilica, machine learning, pervasive computing, computational biology, genomics, reversible computing, Agriculture, cancer, HIV, cybernetics, quantum mechanics, consciousness, Alzheimer's disease, neuronal network, biotechnology, metabolomics, malaria
78	Siva G. Narendra	Challenges and design choices in nanoscale CMOS.	ACM J. Emerg. Technol. Comput. Syst.	2005	DBLP DOI BibTeX RDF	nanoscale, process variation, CMOS, leakage power
75	Nicholas Allec, Zyad Hassan, Li Shang, Robert P. Dick, Ronggui Yang	ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
67	Conor F. Madigan, Vladimir Bulovic	Organic electronic device modeling at the nanoscale.	ICCAD	2006	DBLP DOI BibTeX RDF	molecular, nanoscale, organic, device modeling
57	Theodore W. Manikas, Dale Teeters	Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells.	ISMVL	2008	DBLP DOI BibTeX RDF	electrochemical cells, memory, nanotechnology, multiple-valued logic
57	Mohamad Issa, Adam W. Skorek	Nanoscale Thermal Analysis of Electronic Devices.	CCECE	2006	DBLP DOI BibTeX RDF
57	Reza M. Rad, Mohammad Tehranipoor	A new hybrid FPGA with nanoscale clusters and CMOS routing.	DAC	2006	DBLP DOI BibTeX RDF	reconfigurable nanoscale devices, FPGA, molecular electronics
57	R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi	Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	nanoscale design, defect rates, reliability, verification, redundancy, Moore's Law
53	Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha	A hybrid nano-CMOS architecture for defect and fault tolerance.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	nanotechnology, Defect tolerance, nanowires
53	Bao Liu 0001	Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution.	ISQED	2009	DBLP DOI BibTeX RDF
53	Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha	Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture.	VLSI Design	2008	DBLP DOI BibTeX RDF
49	Duncan M. Hank Walker	K Longest Paths.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Sudhakar M. Reddy, Peter Maxwell	Fundamentals of Small-Delay Defect Testing.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Mahmut Yilmaz	Output Deviations-Based SDD Testing.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Sandeep Kumar Goel, Krishnendu Chakrabarty	Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Sandeep Kumar Goel, Narendra Devta-Prasanna	Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Narendra Devta-Prasanna, Sandeep Kumar Goel	Small-Delay Defect Coverage Metrics.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor	Circuit Path Grading Considering Layout, Process Variations, and Cross Talk.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Nisar Ahmed, Mohammad Tehranipoor	Faster-than-at-Speed Test for Screening Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
49	Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin	Timing-Aware ATPG.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
46	Nader Engheta	Circuits with light at the nanoscale: meta-nanocircuits and metactronics.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nanocircuits, circuits, optics, nanophotonics
46	Rajat Subhra Chakraborty, Swarup Bhunia	Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar.	ISQED	2008	DBLP DOI BibTeX RDF	Diode-resistor logic, CMOSNano, Asynchronous design
46	Reza M. Rad, Mohammad Tehranipoor	Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	performance, FPGA, reliability, CMOS, Nanotechnology
46	Anastassios Pouris	Nanoscale research in South Africa: A mapping exercise based on scientometrics.	Scientometrics	2007	DBLP DOI BibTeX RDF
46	Fabrizio Lombardi, Cecilia Metra	Guest Editors' Introduction: The State of the Art in Nanoscale CAD.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	feature size, nanostructures, VLSI, CAD, nanotechnology
46	Huifei Rao, Jie Chen 0002, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao	Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design.	ISCAS	2007	DBLP DOI BibTeX RDF
46	Eraldo Ribeiro, Mubarak Shah	Computer Vision for Nanoscale Imaging.	Mach. Vis. Appl.	2006	DBLP DOI BibTeX RDF
46	Richard A. Kiehl	Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures.	ICCAD	2006	DBLP DOI BibTeX RDF	molecular devices, nanoarchitecture, self-assembly, nanoelectronics
46	Jie Chen 0002, Hua Li	Design methodology for hardware-efficient fault-tolerant nanoscale circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
46	Diana Marculescu	Energy Bounds for Fault-Tolerant Nanoscale Designs.	DATE	2005	DBLP DOI BibTeX RDF
46	Weixuan Yang, Shaoping Xiao	The Applications of Meshfree Particle Methods at the Nanoscale.	International Conference on Computational Science (3)	2005	DBLP DOI BibTeX RDF
46	Mustafa Altun, Marc D. Riedel, Claudia Neuhauser	Nanoscale digital computation through percolation.	DAC	2009	DBLP DOI BibTeX RDF	nanoscale digital computation, logic synthesis, percolation
46	Reza M. Rad, Mohammad Tehranipoor	SCT: A novel approach for testing and configuring nanoscale devices.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Configuration and testing, reconfigurable nanoscale devices, fault tolerance, crossbar, nanowire
46	Mary Mehrnoosh Eshaghian-Wilner, Alexander Khitun, Shiva Navab, Kang L. Wang	The spin-wave nanoscale reconfigurable mesh and the labeling problem.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	nanoscale architectures, image processing, reconfigurable mesh, Spin waves
46	Reza M. Rad, Mohammad Tehranipoor	A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices.	DFT	2006	DBLP DOI BibTeX RDF	Nanoscale Devices, Fault Tolerance, Test, Reconfiguration, Redundancy, Crossbar
43	Tatsuya Suda, Tadashi Nakano, Michael J. Moore, Akihiro Enomoto, Keita Fujii	Biologically Inspired Approaches to Networks: The Bio-Networking Architecture and the Molecular Communication.	BIOWIRE	2007	DBLP DOI BibTeX RDF	nano-scale biological networks, bio-networking architecture, computer networks, molecular communication, biological inspiration
43	Mohammad Tehranipoor, Reza M. Rad	Fine-grained island style architecture for molecular electronic devices.	FPGA	2006	DBLP DOI BibTeX RDF
36	Zhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen 0002	Emerging nanodevice paradigm: Graphene-based electronics for nanoscale computing.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Graphene device, negative differential resistance, tight-binding model, memory structure
36	Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini	Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	link design techniques, network-on-chip
36	Markus Eisenbach 0002, C.-G. Zhou, Donald M. C. Nicholson, G. Brown, Jeffrey M. Larkin, Thomas C. Schulthess	A scalable method for ab initio computation of free energies in nanoscale systems.	SC	2009	DBLP DOI BibTeX RDF
36	Somnath Paul, Swarup Bhunia	MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices.	ASP-DAC	2008	DBLP DOI BibTeX RDF
36	Huifei Rao, Jie Chen 0002, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu	An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation.	ISCAS	2008	DBLP DOI BibTeX RDF
36	John E. Savage	Computing at the Nanoscale.	DFT	2008	DBLP DOI BibTeX RDF
36	Yoonjae Huh, Yoon-Hwa Choi	Module Grouping for Defect Tolerance in Nanoscale Memory.	DFT	2008	DBLP DOI BibTeX RDF
36	Andrey V. Zykov, Gustavo de Veciana	Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?.	DFT	2008	DBLP DOI BibTeX RDF
36	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy 0001	Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
36	Susmit Biswas, Gang Wang 0015, Tzvetan S. Metodi, Ryan Kastner, Frederic T. Chong	Combining static and dynamic defect-tolerance techniques for nanoscale memory systems.	ICCAD	2007	DBLP DOI BibTeX RDF
36	Jean Arlat	Nanoscale Technologies: Prospect or Hazard to Dependable and Secure Computing?	LADC	2007	DBLP DOI BibTeX RDF
36	Mamidala Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal	Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation.	VLSI Design	2007	DBLP DOI BibTeX RDF
36	Mohammad Tehranipoor, Reza M. Rad	Test and recovery for fine-grained nanoscale architectures.	FPGA	2006	DBLP DOI BibTeX RDF
36	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy 0001	Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.	DATE	2006	DBLP DOI BibTeX RDF
36	Sean X. Shi, David Z. Pan	Wire sizing with scattering effect for nanoscale interconnection.	ASP-DAC	2006	DBLP DOI BibTeX RDF
36	H.-S. Philip Wong	Device and Technology Challenges for Nanoscale CMOS.	ISQED	2006	DBLP DOI BibTeX RDF
36	Reza M. Rad, Mohammad Tehranipoor	SCT: An Approach For Testing and Configuring Nanoscale Devices.	VTS	2006	DBLP DOI BibTeX RDF
36	Srikanth Sundaram, Praveen Elakkumanan, Ramalingam Sridhar	High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach.	VLSI Design	2006	DBLP DOI BibTeX RDF
36	Jia Di, Parag K. Lala, Dilip P. Vasudevan	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.	DFT	2005	DBLP DOI BibTeX RDF
36	Andrey V. Mezhiba, Eby G. Friedman	Impedance characteristics of power distribution grids in nanoscale integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
36	Amrinder S. Nain, Daniel H. Goldman, Metin Sitti	Three-dimensional Nanoscale Manipulation and Manufacturing using Proximal Probes: Controlled Pulling of Polymer Micro/nanofibers.	ICRA	2004	DBLP DOI BibTeX RDF
36	R. Iris Bahar, Joseph L. Mundy, Jie Chen 0002	A Probabilistic-Based Design Methodology for Nanoscale Computation.	ICCAD	2003	DBLP DOI BibTeX RDF
35	Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra	Low power nanoscale buffer management for network on chip routers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nanoscale technology noc, soc, noc, router, dynamic power management
35	Amit Agarwal 0001, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001, Chris H. Kim	Leakage Power Analysis and Reduction for Nanoscale Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	nanoscale circuits, CMOS, technology scaling, leakage power reduction
32	Saroj K. Nayak	Carbon nanotube, graphene and atomic wires as next generation interconnects: current status and future promise.	SLIP	2009	DBLP DOI BibTeX RDF	quantum simulation, performance, design, reliability
32	Harika Manem, Peter C. Paliwoda, Garrett S. Rose	A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	PMLA, FPGA, hybrid
32	Tibor Braun, Sándor Zsindely, Ildikó Dióspatonyi, Erika Zádor	Gatekeeping patterns in nano-titled journals.	Scientometrics	2007	DBLP DOI BibTeX RDF
32	Jia Wang 0003, Ming-Yang Kao, Hai Zhou 0001	Address generation for nanowire decoders.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	testing, decoder, nanowire
32	Jinwen Xi, Peixin Zhong	A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	network-on-chip, SystemC, energy model
32	Minsu Choi, Nohpill Park	Teaching Nanotechnology by Introducing Crossbar-Based Architecture and Quantum-Dot Cellular Automata.	MSE	2005	DBLP DOI BibTeX RDF
32	William R. Smith, Martin Lísal	Molecular Simulation of Reaction and Adsorption in Nanochemical Devices: Increase of Reaction Conversion by Separation of a Product from the Reaction Mixture.	ICCSA (2)	2004	DBLP DOI BibTeX RDF
32	Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee	A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array.	ISQED	2004	DBLP DOI BibTeX RDF
32	Shuo Wang, Lei Wang 0003, Faquir C. Jain	Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Nanoscale architecture, hardware reliability, redundancy allocation, performance, redundant design
32	Kwang-Ting (Tim) Cheng	Supporting cost-effective innovation.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	nanoscale, variability, IR drop, power supply noise
32		Small Robots Team Up to Tackle Large Tasks.	IEEE Distributed Syst. Online	2005	DBLP DOI BibTeX RDF	nanoscale robots, swarm robotics
29	Amit Sangwan, Josep Miquel Jornet	Joint Nanoscale Communication and Sensing Enabled by Plasmonic Nano-antennas.	NANOCOM	2021	DBLP DOI BibTeX RDF
29	Sinem Nimet Solak, Menguc Oner	RNN based abnormality detection with nanoscale sensor networks using molecular communications.	NANOCOM	2020	DBLP DOI BibTeX RDF
29	Philipp Bende, Florian-Lennert Adrian Lau, Stefan Fischer 0001	Error-Resistant Scaling of Three-Dimensional Nanoscale Shapes on the Basis of DNA-Tiles.	NANOCOM	2019	DBLP DOI BibTeX RDF
29	Marc Stelzner, Kim Scharringhausen, Sebastian Ebers	Nanoscale diagnostic procedures: sensing inside the human body.	NANOCOM	2018	DBLP DOI BibTeX RDF
29	Hadeel Elayan, Cesare Stefanini, Raed M. Shubair, Josep Miquel Jornet	Stochastic noise model for intra-body terahertz nanoscale communication.	NANOCOM	2018	DBLP DOI BibTeX RDF
29	Shree M. Prasad, Trilochan Panigrahi, Mahbub Hassan	Direction of arrival estimation for nanoscale sensor networks.	NANOCOM	2018	DBLP DOI BibTeX RDF
29	Alvaro Velasquez, Sumit Kumar Jha 0001	Automated synthesis of crossbars for nanoscale computing using formal methods.	NANOARCH	2015	DBLP DOI BibTeX RDF
29	Eisa Zarepour, Mahbub Hassan, Chun Tung Chou, Adesoji A. Adesina	Remote Detection of Chemical Reactions using Nanoscale Terahertz Communication Powered by Pyroelectric Energy Harvesting.	NANOCOM	2015	DBLP DOI BibTeX RDF
29	Andrew Katumba, Peter Bienstman, Joni Dambre	Photonic reservoir computing approaches to nanoscale computation.	NANOCOM	2015	DBLP DOI BibTeX RDF
29	Paolo Marconcini	Effect of potential disorder on shot noise suppression in nanoscale devices.	NANOARCH	2013	DBLP DOI BibTeX RDF
29	Stas M. Avdoshenko, Claudia Gomes da Rocha, Gianaurelio Cuniberti	Nanoscale ear drum: Graphene based nanoscale sensors	CoRR	2012	DBLP BibTeX RDF
29	Damien Querlioz, Weisheng Zhao, Philippe Dollfus, Jacques-Olivier Klein, Olivier Bichler, Christian Gamrat	Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches.	NANOARCH	2012	DBLP DOI BibTeX RDF
29	Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.	NANOARCH	2011	DBLP DOI BibTeX RDF
29	Paul M. Riechers, Richard A. Kiehl	A scheme for computation in nanoscale dynamical systems: Gated discrete phase-shift interactions.	NANOARCH	2011	DBLP DOI BibTeX RDF
29	Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, Kyeong-Sik Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui, Csaba Andras Moritz	Nanoscale Application Specific Integrated Circuits.	NANOARCH	2011	DBLP DOI BibTeX RDF
29	Yao Wang 0002, Sorin Cotofana, Liang Fang	A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits.	NANOARCH	2011	DBLP DOI BibTeX RDF
29	Ilia Polian, Bernd Becker 0001	Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien).	it Inf. Technol.	2010	DBLP DOI BibTeX RDF
29	Eric Rachlin, John E. Savage	Stochastic nanoscale addressing for logic.	NANOARCH	2010	DBLP DOI BibTeX RDF
29	Yehua Su, Wenjing Rao	Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures.	NANOARCH	2009	DBLP DOI BibTeX RDF
29	Somnath Paul, Swarup Bhunia	Computing with nanoscale memory: Model and architecture.	NANOARCH	2009	DBLP DOI BibTeX RDF
29	Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu	Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices.	NANOARCH	2009	DBLP DOI BibTeX RDF
29	Susmit Biswas, Frederic T. Chong, Tzvetan S. Metodi, Ryan Kastner	A pageable, defect-tolerant nanoscale memory system.	NANOARCH	2007	DBLP DOI BibTeX RDF
29	Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar	Thermally-induced soft errors in nanoscale CMOS circuits.	NANOARCH	2007	DBLP DOI BibTeX RDF
29	Teng Wang, Pritish Narayanan, Csaba Andras Moritz	Combining 2-level logic families in grid-based nanoscale fabrics.	NANOARCH	2007	DBLP DOI BibTeX RDF
29	Zhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen 0002	Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computing.	NANOARCH	2007	DBLP DOI BibTeX RDF
29	Girish Venkatasubramanian, P. Oscar Boykin, Renato J. O. Figueiredo	Design of high-yield defect-tolerant self-assembled nanoscale memories.	NANOARCH	2007	DBLP DOI BibTeX RDF