Search results for "netlists"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
68	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation.	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
63	Benjamin Carrión Schäfer, Taewhan Kim	Hotspots Elimination and Temperature Flattening in VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
63	Andrew B. Kahng, Sherief Reda	Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
63	Sungwoo Park, Jinha Kim, Hyeonseung Im	Functional netlists.	ICFP	2008	DBLP DOI BibTeX RDF	linear type system, functional language, hardware description language
51	Joachim Pistorius, Edmée Legai, Michel Minoux	PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
50	Per Bjesse	A Practical Approach to Word Level Model Checking of Industrial Netlists.	CAV	2008	DBLP DOI BibTeX RDF
50	Kenneth Eguro, Scott Hauck	Simultaneous Retiming and Placement for Pipelined Netlists.	FCCM	2008	DBLP DOI BibTeX RDF
50	Kenneth Eguro, Scott Hauck	Enhancing timing-driven FPGA placement for pipelined netlists.	DAC	2008	DBLP DOI BibTeX RDF	timing-driven, FPGA, simulated annealing, pipelined, placement
50	Jason Baumgartner, Hari Mony	Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies.	CHARME	2005	DBLP DOI BibTeX RDF
43	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
43	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
38	Qinghua Liu, Malgorzata Marek-Sadowska	Semi-Individual Wire-Length Prediction With Application to Logic Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
38	Phillip Christie	A differential equation for placement analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
38	Tai-Hung Liu, Adnan Aziz, Vigyan Singhal	Optimizing designs containing black boxes.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	IP-based design, hierarchical logic synthesis, Don't cares
38	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
37	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	phase abstraction, automatic abstraction, CTL model checking, level-sensitive latch, bisimulation, model reduction
37	Rolf Drechsler, Mitchell A. Thornton	Computation of Spectral Information from Logic Netlists.	ISMVL	2000	DBLP DOI BibTeX RDF
37	C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora	Estimation of Power from Module-level Netlists.	VLSI Design	1996	DBLP DOI BibTeX RDF
37	Roman Kuznar, Franc Brglez	PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	optimization, FPGA, partitioning, resynthesis, critical path delay
25	Ajay Kumar Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
25	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for reconfigurable architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
25	Andrew B. Kahng, Sherief Reda	Evaluation of placer suboptimality via zero-change netlist transformations.	ISPD	2005	DBLP DOI BibTeX RDF	placer suboptimality, benchmarking, wirelength
25	Michael D. Hutton, Jonathan Rose, Derek G. Corneil	Automatic generation of synthetic sequential benchmark circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
25	Srihari Cadambi, Seth Copen Goldstein	Static Profile-Driven Compilation for FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
25	Daniel R. Brasen, Gabriele Saucier	Using cone structures for circuit partitioning into FPGA packages.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
25	Paolo Ienne, Alexander Grießing	Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?	DAC	1998	DBLP DOI BibTeX RDF	migration, timing optimazation, custom sizing
25	Scott W. Hadley, Brian L. Mark, Anthony Vannelli	An efficient eigenvector approach for finding netlist partitions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
24	Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa	Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2024	DBLP DOI BibTeX RDF
24	Wenxing Hu, Xianke Zhan, Minglei Tong	Parsing Netlists of Integrated Circuits from Images via Graph Attention Network.	Sensors	2024	DBLP DOI BibTeX RDF
24	Ryotaro Negishi, Nozomu Togawa	Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists.	ICCE	2024	DBLP DOI BibTeX RDF
24	Jonathan Cruz 0001, Christopher Posada, Naren Vikram Raj Masna, Prabuddha Chakraborty, Pravin Gaikwad, Swarup Bhunia	A Framework for Automated Exploration of Trojan Attack Space in FPGA Netlists.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
24	Sergio Vinagrero Gutierrez, Giorgio Di Natale, Elena Ioana Vatajelu	Python Framework for Modular and Parametric SPICE Netlists Generation.	CoRR	2023	DBLP DOI BibTeX RDF
24	Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri	Reverse Engineering Word-Level Models from Look-Up Table Netlists.	CoRR	2023	DBLP DOI BibTeX RDF
24	Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert	RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks.	MWSCAS	2023	DBLP DOI BibTeX RDF
24	Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert	Reverse Engineering of RTL Controllers from Look-Up Table Netlists.	ISVLSI	2023	DBLP DOI BibTeX RDF
24	Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche	Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning.	LATS	2023	DBLP DOI BibTeX RDF
24	Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri	Reverse Engineering Word-Level Models from Look-Up Table Netlists.	ISQED	2023	DBLP DOI BibTeX RDF
24	Ying Zhang, Sen Li, Xin Chen, Jiaqi Yao, Zhiming Mao, Jizhong Yang, Yifeng Hua	Hybrid multi-level hardware Trojan detection platform for gate-level netlists based on XGBoost.	IET Comput. Digit. Tech.	2022	DBLP DOI BibTeX RDF
24	Zhao Huang, Changjian Xie, Zeyu Li, Maofan Du, Quan Wang 0006	A Hardware Trojan Detection and Diagnosis Method for Gate-Level Netlists Based on Different Machine Learning Algorithms.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
24	Lilas Alrahis, Abhrajit Sengupta, Johann Knechtel, Satwik Patnaik, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu	GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
24	Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa	Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models.	ICCE-Berlin	2022	DBLP DOI BibTeX RDF
24	Seyed Alireza Damghani, Kenneth B. Kent	Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR.	FPGA	2022	DBLP DOI BibTeX RDF
24	Seyed Alireza Damghani, Kenneth B. Kent	Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTR.	FCCM	2022	DBLP DOI BibTeX RDF
24	Kazuki Yamashita, Tomohiro Kato, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa	Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists.	IOLTS	2022	DBLP DOI BibTeX RDF
24	Aditi Singh	Equivalence Checking of Non-Binary Combinational Netlists.	VLSID	2022	DBLP DOI BibTeX RDF
24	Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa	Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists.	J. Inf. Process.	2021	DBLP DOI BibTeX RDF
24	Nicholas V. Giamblanco, Andrew Schmidt	vlang: Mapping Verilog Netlists to Modern Technologies.	CoRR	2021	DBLP BibTeX RDF
24	Konstantinos G. Liakos, Georgios K. Georgakilas, Fotis C. Plessas	Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis.	ISVLSI	2021	DBLP DOI BibTeX RDF
24	Tong Lu, Fang Zhou 0001, Ning Wu, Fen Ge, Benjun Zhang	Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning.	ICCT	2021	DBLP DOI BibTeX RDF
24	Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa	Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists.	IOLTS	2021	DBLP DOI BibTeX RDF
24	Carina Wiesen	How do engineers analyze netlists?: Human problem-solving processes in hardware reverse engineering.		2021	RDF
24	Michael A. Turi	Scripts for Easier Use of Spice (SEUS): A Perl script package for simulating and creating batches of circuit netlists for Monte Carlo simulations when using Ngspice or Ngspice-based simulators.	J. Open Source Softw.	2020	DBLP DOI BibTeX RDF
24	Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi	Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.	IPSJ Trans. Syst. LSI Des. Methodol.	2019	DBLP DOI BibTeX RDF
24	Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa	Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists.	CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS	2019	DBLP DOI BibTeX RDF
24	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2018	DBLP DOI BibTeX RDF
24	Stelios N. Neophytou, Maria K. Michael	Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering.	J. Electron. Test.	2018	DBLP DOI BibTeX RDF
24	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
24	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
24	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier.	ISCAS	2017	DBLP DOI BibTeX RDF
24	Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa	Hardware Trojans classification for gate-level netlists using multi-layer neural networks.	IOLTS	2017	DBLP DOI BibTeX RDF
24	Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa	Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
24	Thorben Casper, Herbert De Gersem, Sebastian Schöps	Automatic Generation of Equivalent Electrothermal SPICE Netlists from 3D Electrothermal Field Models.	CoRR	2016	DBLP BibTeX RDF
24	Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa	Hardware Trojans classification for gate-level netlists based on machine learning.	IOLTS	2016	DBLP DOI BibTeX RDF
24	Masaru Oya, Masao Yanagisawa, Nozomu Togawa	Redesign for untrusted gate-level netlists.	IOLTS	2016	DBLP DOI BibTeX RDF
24	Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa	A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2015	DBLP DOI BibTeX RDF
24	Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa	A score-based classification method for identifying hardware-trojans at gate-level netlists.	DATE	2015	DBLP BibTeX RDF
24	Magne Voernes, Trond Ytterdal, Snorre Aunet	Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout.	NORCHIP	2014	DBLP DOI BibTeX RDF
24	Grigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou, Dimitrios Soudris	Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems.	DATE	2013	DBLP DOI BibTeX RDF
24	Mitchell A. Thornton, Theodore W. Manikas	Spectral Response of Ternary Logic Netlists.	ISMVL	2013	DBLP DOI BibTeX RDF
24	Matthias Brettschneider, Tobias Häberlein	From Arrows to Netlists Describing Hardware.	ICCSA (3)	2013	DBLP DOI BibTeX RDF
24	John Lee 0002, Puneet Gupta 0001, Fedor Pikus	Parametric Hierarchy Recovery in Layout Extracted Netlists.	ISVLSI	2012	DBLP DOI BibTeX RDF
24	Sho Nishida, Katsumi Wasaki	Retargetable Netlists Generation and Structural Synthesis Based on a Meta Hardware Description Language: Melasy+.	ITNG	2012	DBLP DOI BibTeX RDF
24	Niccolò Battezzati, Davide Serrone, Massimo Violante	A new framework for the automatic insertion of mitigation structures in circuits netlists.	IOLTS	2010	DBLP DOI BibTeX RDF
24	Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li 0001, Gi-Joon Nam, Charles B. Winn	Detecting tangled logic structures in VLSI netlists.	DAC	2010	DBLP DOI BibTeX RDF	congestion prediction, rent rule, tangled logic, clustering
24	Jarrod A. Roy, David A. Papa, Igor L. Markov	Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability.	Modern Circuit Placement	2007	DBLP DOI BibTeX RDF
24	Yoichi Tomioka, Atsushi Takahashi 0001	Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
24	M. Moiz Khan, Spyros Tragoudas	Rewiring for watermarking digital circuit netlists.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Rolf Drechsler, Wolfgang Günther 0001, Thomas Eschbach, Lothar Linhard, Gerhard Angst	Recursive bi-partitioning of netlists for large number of partitions.	J. Syst. Archit.	2003	DBLP DOI BibTeX RDF
24	Rolf Drechsler, Wolfgang Günther 0001, Thomas Eschbach, Lothar Linhard, Gerhard Angst	Recursive Bi-Partitioning of Netlists for Large Number of Partitions.	DSD	2002	DBLP DOI BibTeX RDF
24	Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang	Aggressive crunching of extracted RC netlists.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	RC reduction, TICER, crunching, node elimination, resistor shorting, time constants, interconnect modeling, elmore delay
24	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists.	CAV	1999	DBLP DOI BibTeX RDF
24	Avinash K. Gautam, V. Visvanathan, S. K. Nandy 0001	Automatic Generation of Tree Multipliers Using Placement-Driven Netlists.	ICCD	1999	DBLP DOI BibTeX RDF
24	C. P. Ravikumar, Hemant Joshi	SCOAP-based Testability Analysis from Hierarchical Netlists.	VLSI Design	1998	DBLP DOI BibTeX RDF
24	Paul Tafertshofer, Andreas Ganz, Manfred Henftling	A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists.	ICCAD	1997	DBLP DOI BibTeX RDF	SAT-based implication engine, circuit clause description, efficient ATPG, implication evaluation, indirect implications, netlist optimization, structure based methods, graph algorithms, automatic testing, logic circuits, graph model, equivalence checking, implication graph
24	Peter Marwedel, Steven Bashford, Rainer Dömer, Birger Landwehr, Ingolf Markhof	A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis.	ED&TC	1996	DBLP DOI BibTeX RDF
24	K. J. Singh, P. A. Subrahmanyam	Extracting RTL models from transistor netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	Switch-level simulation, Formal verification, Extraction, RTL model
24	David B. Bernstein, Werner van Almsick, Wilfried Daehn	Distributed simulation for structural VHDL netlists.	EURO-DAC	1994	DBLP DOI BibTeX RDF	VHDL
24	Allen C.-H. Wu, Daniel D. Gajski	Partitioning algorithms for layout synthesis from register-transfer netlists.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
24	John T. O'Donnell	Generating Netlists from Executable Circuit Specifications.	Functional Programming	1992	DBLP DOI BibTeX RDF
24	Allen C.-H. Wu, Daniel Gajski	Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists.	ICCAD	1990	DBLP DOI BibTeX RDF
24	J. Y. Murzin	FAON: a functional abstractor of netlists.	SPLT	1986	DBLP BibTeX RDF
13	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
13	Satnam Singh	Declarative data-parallel programming with the accelerator system.	DAMP	2010	DBLP DOI BibTeX RDF	data-parallelsim
13	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
13	Neeraj Kaul	Design planning trends and challenges.	ISPD	2010	DBLP DOI BibTeX RDF	clock planning, feedthrough generation, macro placement, power domains, power planning, time budgeting, voltage areas, prototyping, partitioning, floorplanning, feasibility, hierarchical design, constraints generation, pin assignment
13	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
13	Feng Wang 0004, Yuan Xie 0001, Andrés Takach	Variation-aware resource sharing and binding in behavioral synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
13	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A faster approximation scheme for timing driven minimum cost layer assignment.	ISPD	2009	DBLP DOI BibTeX RDF	dynamic programming, np-complete, oracle, fully polynomial time approximation scheme, layer assignment
13	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
13	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Timing-driven N-way decomposition.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	logic design, decomposition, timing optimization