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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 191 occurrences of 150 keywords
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Results
Found 217 publication records. Showing 217 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
68 | Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain |
Extraction of finite state machines from transistor netlists by symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 596-601, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams |
63 | Benjamin Carrión Schäfer, Taewhan Kim |
Hotspots Elimination and Temperature Flattening in VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1475-1487, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
63 | Andrew B. Kahng, Sherief Reda |
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2806-2819, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
63 | Sungwoo Park, Jinha Kim, Hyeonseung Im |
Functional netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFP ![In: Proceeding of the 13th ACM SIGPLAN international conference on Functional programming, ICFP 2008, Victoria, BC, Canada, September 20-28, 2008, pp. 353-366, 2008, ACM, 978-1-59593-919-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
linear type system, functional language, hardware description language |
51 | Joachim Pistorius, Edmée Legai, Michel Minoux |
PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1314-1321, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
50 | Per Bjesse |
A Practical Approach to Word Level Model Checking of Industrial Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings, pp. 446-458, 2008, Springer, 978-3-540-70543-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
50 | Kenneth Eguro, Scott Hauck |
Simultaneous Retiming and Placement for Pipelined Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 139-148, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
50 | Kenneth Eguro, Scott Hauck |
Enhancing timing-driven FPGA placement for pipelined netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 34-37, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
timing-driven, FPGA, simulated annealing, pipelined, placement |
50 | Jason Baumgartner, Hari Mony |
Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 222-237, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury |
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 361-366, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates |
43 | Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska |
Design and performance of CMOS TSPC cells for high speed pseudo random testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 368-373, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists |
38 | Qinghua Liu, Malgorzata Marek-Sadowska |
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4), pp. 611-624, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Phillip Christie |
A differential equation for placement analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 913-921, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Tai-Hung Liu, Adnan Aziz, Vigyan Singhal |
Optimizing designs containing black boxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(4), pp. 591-601, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
IP-based design, hierarchical logic synthesis, Don't cares |
38 | Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri |
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 547-563, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model |
37 | Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz |
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 23(1), pp. 39-65, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
phase abstraction, automatic abstraction, CTL model checking, level-sensitive latch, bisimulation, model reduction |
37 | Rolf Drechsler, Mitchell A. Thornton |
Computation of Spectral Information from Logic Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 53-58, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora |
Estimation of Power from Module-level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 324-325, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
37 | Roman Kuznar, Franc Brglez |
PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 644-649, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimization, FPGA, partitioning, resynthesis, critical path delay |
25 | Ajay Kumar Verma, Paolo Ienne |
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 601-608, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers |
25 | Akshay Sharma, Carl Ebeling, Scott Hauck |
PipeRoute: a pipelining-aware router for reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 518-532, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Andrew B. Kahng, Sherief Reda |
Evaluation of placer suboptimality via zero-change netlist transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 208-215, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
placer suboptimality, benchmarking, wirelength |
25 | Michael D. Hutton, Jonathan Rose, Derek G. Corneil |
Automatic generation of synthetic sequential benchmark circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), pp. 928-940, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Srihari Cadambi, Seth Copen Goldstein |
Static Profile-Driven Compilation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 112-122, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Daniel R. Brasen, Gabriele Saucier |
Using cone structures for circuit partitioning into FPGA packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(7), pp. 592-600, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Paolo Ienne, Alexander Grießing |
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 396-401, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
migration, timing optimazation, custom sizing |
25 | Scott W. Hadley, Brian L. Mark, Anthony Vannelli |
An efficient eigenvector approach for finding netlist partitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7), pp. 885-892, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
24 | Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa |
Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1), pp. 63-74, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Wenxing Hu, Xianke Zhan, Minglei Tong |
Parsing Netlists of Integrated Circuits from Images via Graph Attention Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 24(1), pp. 227, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Ryotaro Negishi, Nozomu Togawa |
Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2024, Las Vegas, NV, USA, January 6-8, 2024, pp. 1-6, 2024, IEEE, 979-8-3503-2413-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Jonathan Cruz 0001, Christopher Posada, Naren Vikram Raj Masna, Prabuddha Chakraborty, Pravin Gaikwad, Swarup Bhunia |
A Framework for Automated Exploration of Trojan Attack Space in FPGA Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 72(10), pp. 2740-2751, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Sergio Vinagrero Gutierrez, Giorgio Di Natale, Elena Ioana Vatajelu |
Python Framework for Modular and Parametric SPICE Netlists Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2306.12224, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri |
Reverse Engineering Word-Level Models from Look-Up Table Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2303.02762, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert |
RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 511-515, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert |
Reverse Engineering of RTL Controllers from Look-Up Table Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023, Foz do Iguacu, Brazil, June 20-23, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2769-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche |
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 24th IEEE Latin American Test Symposium, LATS 2023, Veracruz, Mexico, March 21-24, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2597-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri |
Reverse Engineering Word-Level Models from Look-Up Table Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, CA, USA, April 5-7, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-3475-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Ying Zhang, Sen Li, Xin Chen, Jiaqi Yao, Zhiming Mao, Jizhong Yang, Yifeng Hua |
Hybrid multi-level hardware Trojan detection platform for gate-level netlists based on XGBoost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 16(2-3), pp. 54-70, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Zhao Huang, Changjian Xie, Zeyu Li, Maofan Du, Quan Wang 0006 |
A Hardware Trojan Detection and Diagnosis Method for Gate-Level Netlists Based on Different Machine Learning Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(7), pp. 2250135:1-2250135:25, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Lilas Alrahis, Abhrajit Sengupta, Johann Knechtel, Satwik Patnaik, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu |
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8), pp. 2435-2448, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa |
Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-Berlin ![In: 12th IEEE International Conference on Consumer Electronics, ICCE-Berlin 2022, Berlin, Germany, September 2-6, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5676-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Seyed Alireza Damghani, Kenneth B. Kent |
Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022, pp. 157, 2022, ACM, 978-1-4503-9149-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Seyed Alireza Damghani, Kenneth B. Kent |
Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2022, New York City, NY, USA, May 15-18, 2022, pp. 1, 2022, IEEE, 978-1-6654-8332-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Kazuki Yamashita, Tomohiro Kato, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa |
Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 28th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2022, Torino, Italy, September 12-14, 2022, pp. 1-7, 2022, IEEE, 978-1-6654-7355-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Aditi Singh |
Equivalence Checking of Non-Binary Combinational Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022, pp. 22-27, 2022, IEEE, 978-1-6654-8505-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa |
Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Process. ![In: J. Inf. Process. 29, pp. 236-246, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Nicholas V. Giamblanco, Andrew Schmidt |
vlang: Mapping Verilog Netlists to Modern Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2111.04913, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
24 | Konstantinos G. Liakos, Georgios K. Georgakilas, Fotis C. Plessas |
Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021, pp. 412-417, 2021, IEEE, 978-1-6654-3946-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Tong Lu, Fang Zhou 0001, Ning Wu, Fen Ge, Benjun Zhang |
Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCT ![In: 21st International Conference on Communication Technology, ICCT 2021, Tianjin, China, October 13-16, 2021, pp. 301-305, 2021, IEEE, 978-1-6654-3206-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa |
Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 27th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2021, Torino, Italy, June 28-30, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3370-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Carina Wiesen |
How do engineers analyze netlists?: Human problem-solving processes in hardware reverse engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
RDF |
|
24 | Michael A. Turi |
Scripts for Easier Use of Spice (SEUS): A Perl script package for simulating and creating batches of circuit netlists for Monte Carlo simulations when using Ngspice or Ngspice-based simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Open Source Softw. ![In: J. Open Source Softw. 5(53), pp. 2183, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi |
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 12, pp. 78-80, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa |
Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS ![In: Computer Security - ESORICS 2019 International Workshops, CyberICPS, SECPRE, SPOSE, and ADIoT, Luxembourg City, Luxembourg, September 26-27, 2019 Revised Selected Papers, pp. 341-359, 2019, Springer, 978-3-030-42047-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12), pp. 2320-2326, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Stelios N. Neophytou, Maria K. Michael |
Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 34(6), pp. 667-683, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12), pp. 2857-2868, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7), pp. 1427-1438, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa |
Hardware Trojans classification for gate-level netlists using multi-layer neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017, pp. 227-232, 2017, IEEE, 978-1-5386-0352-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa |
Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12), pp. 2335-2347, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Thorben Casper, Herbert De Gersem, Sebastian Schöps |
Automatic Generation of Equivalent Electrothermal SPICE Netlists from 3D Electrothermal Field Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1610.04304, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
24 | Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
Hardware Trojans classification for gate-level netlists based on machine learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, Sant Feliu de Guixols, Spain, July 4-6, 2016, pp. 203-206, 2016, IEEE, 978-1-5090-1507-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Masaru Oya, Masao Yanagisawa, Nozomu Togawa |
Redesign for untrusted gate-level netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, Sant Feliu de Guixols, Spain, July 4-6, 2016, pp. 219-220, 2016, IEEE, 978-1-5090-1507-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa |
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12), pp. 2537-2546, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa |
A score-based classification method for identifying hardware-trojans at gate-level netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 465-470, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
24 | Magne Voernes, Trond Ytterdal, Snorre Aunet |
Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, pp. 1-6, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Grigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou, Dimitrios Soudris |
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 655-658, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Mitchell A. Thornton, Theodore W. Manikas |
Spectral Response of Ternary Logic Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 43rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2013, Toyama, Japan, May 22-24, 2013, pp. 109-116, 2013, IEEE Computer Society, 978-1-4673-6067-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Matthias Brettschneider, Tobias Häberlein |
From Arrows to Netlists Describing Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (3) ![In: Computational Science and Its Applications - ICCSA 2013 - 13th International Conference, Ho Chi Minh City, Vietnam, June 24-27, 2013, Proceedings, Part III, pp. 128-143, 2013, Springer, 978-3-642-39645-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | John Lee 0002, Puneet Gupta 0001, Fedor Pikus |
Parametric Hierarchy Recovery in Layout Extracted Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012, pp. 332-337, 2012, IEEE Computer Society, 978-1-4673-2234-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Sho Nishida, Katsumi Wasaki |
Retargetable Netlists Generation and Structural Synthesis Based on a Meta Hardware Description Language: Melasy+. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Ninth International Conference on Information Technology: New Generations, ITNG 2012, Las Vegas, Nevada, USA, 16-18 April, 2012, pp. 827-830, 2012, IEEE Computer Society, 978-0-7695-4654-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Niccolò Battezzati, Davide Serrone, Massimo Violante |
A new framework for the automatic insertion of mitigation structures in circuits netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 5-7 July, 2010, Corfu, Greece, pp. 190-191, 2010, IEEE Computer Society, 978-1-4244-7724-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li 0001, Gi-Joon Nam, Charles B. Winn |
Detecting tangled logic structures in VLSI netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 603-608, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
congestion prediction, rent rule, tangled logic, clustering |
24 | Jarrod A. Roy, David A. Papa, Igor L. Markov |
Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Modern Circuit Placement ![In: Modern Circuit Placement, Best Practices and Results, pp. 97-133, 2007, Springer, 978-0-387-36837-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Yoichi Tomioka, Atsushi Takahashi 0001 |
Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12), pp. 3551-3559, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | M. Moiz Khan, Spyros Tragoudas |
Rewiring for watermarking digital circuit netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1132-1137, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Rolf Drechsler, Wolfgang Günther 0001, Thomas Eschbach, Lothar Linhard, Gerhard Angst |
Recursive bi-partitioning of netlists for large number of partitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 49(12-15), pp. 521-528, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Rolf Drechsler, Wolfgang Günther 0001, Thomas Eschbach, Lothar Linhard, Gerhard Angst |
Recursive Bi-Partitioning of Netlists for Large Number of Partitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 38-44, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang |
Aggressive crunching of extracted RC netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 70-77, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
RC reduction, TICER, crunching, node elimination, resistor shorting, time constants, interconnect modeling, elmore delay |
24 | Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz |
Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings, pp. 72-83, 1999, Springer, 3-540-66202-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Avinash K. Gautam, V. Visvanathan, S. K. Nandy 0001 |
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 285-288, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | C. P. Ravikumar, Hemant Joshi |
SCOAP-based Testability Analysis from Hierarchical Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 7(2), pp. 131-141, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Paul Tafertshofer, Andreas Ganz, Manfred Henftling |
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 648-655, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
SAT-based implication engine, circuit clause description, efficient ATPG, implication evaluation, indirect implications, netlist optimization, structure based methods, graph algorithms, automatic testing, logic circuits, graph model, equivalence checking, implication graph |
24 | Peter Marwedel, Steven Bashford, Rainer Dömer, Birger Landwehr, Ingolf Markhof |
A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996, pp. 600, 1996, IEEE Computer Society, 0-8186-7423-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | K. J. Singh, P. A. Subrahmanyam |
Extracting RTL models from transistor netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 11-17, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Switch-level simulation, Formal verification, Extraction, RTL model |
24 | David B. Bernstein, Werner van Almsick, Wilfried Daehn |
Distributed simulation for structural VHDL netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994, pp. 598-603, 1994, IEEE Computer Society, 0-89791-685-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
VHDL |
24 | Allen C.-H. Wu, Daniel D. Gajski |
Partitioning algorithms for layout synthesis from register-transfer netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4), pp. 453-463, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
24 | John T. O'Donnell |
Generating Netlists from Executable Circuit Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Functional Programming ![In: Functional Programming, Glasgow 1992, Proceedings of the 1992 Glasgow Workshop on Functional Programming, Ayr, Scotland, UK, 6-8 July 1992, pp. 178-194, 1992, Springer, 3-540-19820-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
24 | Allen C.-H. Wu, Daniel Gajski |
Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 144-147, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | J. Y. Murzin |
FAON: a functional abstractor of netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPLT ![In: SPLT'86, Séminaire Programmation en Logique, 21-23 mai 1986, Trégastel, France, pp. 521-536, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP BibTeX RDF |
|
13 | Peter A. Jamieson, Kenneth B. Kent |
Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 288, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, verilog hdl |
13 | Satnam Singh |
Declarative data-parallel programming with the accelerator system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAMP ![In: Proceedings of the POPL 2010 Workshop on Declarative Aspects of Multicore Programming, DAMP 2010, Madrid, Spain, January 19, 2010, pp. 1-2, 2010, ACM, 978-1-60558-859-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
data-parallelsim |
13 | Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li 0001, Charles J. Alpert, Shyam Ramji, Chris Chu |
ITOP: integrating timing optimization within placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 83-90, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
placement, timing optimization, physical synthesis |
13 | Neeraj Kaul |
Design planning trends and challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 5, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clock planning, feedthrough generation, macro placement, power domains, power planning, time budgeting, voltage areas, prototyping, partitioning, floorplanning, feasibility, hierarchical design, constraints generation, pin assignment |
13 | Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko |
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 14:1-14:24, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
area flow, cut enumeration, edge flow, FPGA, technology mapping |
13 | Feng Wang 0004, Yuan Xie 0001, Andrés Takach |
Variation-aware resource sharing and binding in behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 79-84, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | Shiyan Hu, Zhuo Li 0001, Charles J. Alpert |
A faster approximation scheme for timing driven minimum cost layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 167-174, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic programming, np-complete, oracle, fully polynomial time approximation scheme, layer assignment |
13 | Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001 |
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 62-73, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools |
13 | David Bañeres, Jordi Cortadella, Michael Kishinevsky |
Timing-driven N-way decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 363-368, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logic design, decomposition, timing optimization |
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