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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 716 occurrences of 435 keywords
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Results
Found 890 publication records. Showing 890 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
45 | Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har |
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 152-155, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous on-chip bus, in-order completion, multiple issue, out-of-order completion, SoC, GALS |
43 | Kiyeon Lee, Sangyeun Cho |
In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 2011, 19th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Singapore, 25-27 July, 2011, pp. 126-135, 2011, IEEE Computer Society, 978-1-4577-0468-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Superscalar out-of-order processor, performance modeling, trace-driven simulation |
43 | Graham Cormode, Flip Korn, Srikanta Tirthapura |
Time-decaying aggregates in out-of-order streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODS ![In: Proceedings of the Twenty-Seventh ACM SIGMOD-SIGACT-SIGART Symposium on Principles of Database Systems, PODS 2008, June 9-11, 2008, Vancouver, BC, Canada, pp. 89-98, 2008, ACM, 978-1-60558-108-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
asynchronous data streams, out-of-order arrivals |
43 | Roger Espasa, Mateo Valero, James E. Smith 0001 |
Out-of-Order Vector Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 160-170, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
memory traffic elimination, microarchitecture, out-of-order execution, memory latency, register renaming, vector architecture, precise interrupts |
42 | Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat |
By-passing the out-of-order execution pipeline to increase energy-efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 97-104, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
instruction wake-up, energy-efficiency, instruction scheduling, out-of-order execution |
42 | Jared Stark, Paul Racunas, Yale N. Patt |
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 34-43, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
instruction supply, superscalar processors, out-of-order execution |
39 | Wade Walker, Harvey G. Cragon |
Interrupt Processing in Concurrent Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 28(6), pp. 36-46, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Interrupt processing, imprecise interrupts, concurrent processors, checkpointing, taxonomy, superscalar processors, pipelined processors, out- of-order execution, out-of-order issue, precise interrupts |
39 | Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001 |
A mechanistic performance model for superscalar out-of-order processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 27(2), pp. 3:1-3:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling |
39 | Mingzhu Wei, Mo Liu 0001, Ming Li 0008, Denis Golovnya, Elke A. Rundensteiner, Kajal T. Claypool |
Supporting a spectrum of out-of-order event processing technologies: from aggressive to conservative methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2009, Providence, Rhode Island, USA, June 29 - July 2, 2009, pp. 1031-1034, 2009, ACM, 978-1-60558-551-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
out-of-order data, stream processing, complex event processing |
39 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra |
Modeling out-of-order processors for WCET analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 34(3), pp. 195-227, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache |
37 | Madhavi Gopal Valluri, R. Govindarajan |
Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 78-83, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods |
36 | David Tarjan, Michael Boyer, Kevin Skadron |
Federation: repurposing scalar cores for out-of-order instruction issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 772-775, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMP, multicore, federation, out-of-order |
36 | Ernie Chan, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn |
Supermatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Diego, California, USA, June 9-11, 2007, pp. 116-125, 2007, ACM, 978-1-59593-667-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
data affinity, data-flow parallelism, dense linear algebra libraries, dynamic scheduling, out-of-order execution |
35 | Eric Schnarr, James R. Larus |
Fast Out-Of-Order Processor Simulation Using Memoization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 283-294, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
out-of-order processor simulation, memoization, direct-execution |
34 | Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har |
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 46(2-3), pp. 133-151, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS |
34 | Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu |
Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(1), pp. 1-14, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
superscalar pipeline, non-blocking cache, synthesis flow, bit-sliced placement, crafted cell, performance evaluation, physical design, out-of-order execution, general-purpose processor |
34 | Feng Wang, Yongguang Zhang |
Improving TCP performance over mobile ad-hoc networks with out-of-order detection and response. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiHoc ![In: Proceedings of the 3rd ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, MobiHoc 2002, June 9-11, 2002, Lausanne, Switzerland, pp. 217-225, 2002, ACM, 1-58113-501-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MANET, mobile ad hoc networks, TCP, out-of-order |
31 | Sudarshan K. Srinivasan |
Automatic Refinement Checking of Pipelines with Out-of-Order Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(8), pp. 1138-1144, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Pipelined machine verification, refinement, out-of-order execution |
31 | Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski |
Out-of-order issue logic using sorting networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 385-388, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
out-of-order processing, ILP, micro-architecture, issue queue, high speed circuits |
31 | Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 71-78, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
energy-delay, out-of-order embedded processor, resource resizing, performance, architecture |
31 | Julian Satran, Dafna Sheinwald, Ilan Shimony |
Out of Order Incremental CRC Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(9), pp. 1178-1181, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cyclic redundancy codes, out-of-order computation, RDMA, CRC |
31 | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere |
Solving Out-of-Order Communication in Kahn Process Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(1), pp. 7-18, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
producer/consumer pair, in-order, reordering memory, lower bound, rank function, Kahn Process Network, out-of-order |
31 | Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero |
A Case for Resource-conscious Out-of-order Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 2, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
checkpointing, instruction-level parallelism, resource utilization, memory latency, Out-of-order processor |
31 | Hwa C. Torng, Martin Day |
Interrupt Handling for Out-of-Order Execution Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(1), pp. 122-127, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
out-of-order execution processors, low-level execution concurrency, vexing problem, hardware mechanism, concurrency control, latency, exception handling, exception handling, interrupts, superscalars, performance degradation, performance enhancement, instruction window, multiple instructions, interrupt handling |
28 | Andrew D. Hilton, Amir Roth |
Ginger: control independence using tag rewriting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 436-447, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
control independence, out-of-order renaming, selective re-dispatch, branch misprediction |
28 | Milad Mohammadi, Tor M. Aamodt, William J. Dally |
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 14(4), pp. 39:1-39:26, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Pavan Balaji, Wu-chun Feng, Sitha Bhagvat, Dhabaleswar K. Panda 0001, Rajeev Thakur, William Gropp |
Analyzing the impact of supporting out-of-order communication on in-order performance with iWARP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, SC 2007, November 10-16, 2007, Reno, Nevada, USA, pp. 35, 2007, ACM Press, 978-1-59593-764-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Mo Liu 0001, Ming Li 0008, Denis Golovnya, Elke A. Rundensteiner, Kajal T. Claypool |
Sequence Pattern Query Processing over Out-of-Order Event Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: Proceedings of the 25th International Conference on Data Engineering, ICDE 2009, March 29 2009 - April 2 2009, Shanghai, China, pp. 784-795, 2009, IEEE Computer Society, 978-0-7695-3545-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Soner Önder, Rajiv Gupta 0001 |
Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 170-176, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(1), pp. 18-33, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cache-miss tolerance, prefetching, out-of-order execution, Runahead execution |
25 | Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere |
Efficient design space exploration of high performance embedded out-of-order processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 351-356, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Ramon Canal, Antonio González 0001 |
A low-complexity issue logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 327-335, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
in-order issue, instruction issue logic, wide-issue superscalar, out-of-order issue |
24 | Sibin Mohan, Frank Mueller 0001 |
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2008, April 22-24, 2008, St. Louis, Missouri, USA, pp. 285-294, 2008, IEEE Computer Society, 978-0-7695-3146-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hybrid timing anlalysis, hardware/software interactions, real-time systems, embedded systems, computer architecture, timing analysis, worst-case execution time, out-of-order execution |
24 | Weiwu Hu, Fuxin Zhang, Zusong Li |
Microarchitecture of the Godson-2 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 243-249, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming |
24 | Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte |
A Fast Interrupt Handling Scheme for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 136-141, 1998, IEEE Computer Society, 0-8186-8591-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue |
24 | Jiani Guo, Laxmi N. Bhuyan |
Load Balancing in a Cluster-Based Web Server for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(11), pp. 1321-1334, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Online prediction, partial predictor, global predictor, adaptive partioning, prediction-based load balancing, out-of-order rate |
24 | Suchitra Raman, Hari Balakrishnan, Murari Srinivasan |
An Image Transport Protocol for the Internet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: Eighth Annual International Conference on Network Protocols, ICNP 2000, 14-17 November, 2000, Osaka, Japan, pp. 209-219, 2000, IEEE Computer Society, 0-7695-0921-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
image transport protocol, Web downloads, in-order byte-stream abstraction, loss-prone congested networks, user-perceived latency, application level framing, out-of-order application data unit, receiver-driven selective reliability, image formats, receiver post-processing algorithms, Internet, Internet, image processing, image processing, wireless networks, transport protocols, image quality, JPEG, JPEG2000, visual communication, UDP, error concealment, PSNR, receiver, network congestion, image transmission, image data, peak signal-to-noise ratio, image rendering, reconstructed images, congestion manager, interactive performance |
22 | Miquel Pericàs, Adrián Cristal, Rubén González 0001, Daniel A. Jiménez |
Chained In-Order/Out-of-Order DoubleCore Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 24-27 October 2005, Rio de Janeiro, Brazil, pp. 209-217, 2005, IEEE Computer Society, 0-7695-2446-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Jose Renau, James Tuck 0001, Wei Liu 0014, Luis Ceze, Karin Strauss, Josep Torrellas |
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, pp. 179-188, 2005, ACM, 1-59593-167-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | J. P. Grossman |
Cheap Out-of-Order Execution Using Delayed Issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 549-551, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Jens U. Skakkebæk, Robert B. Jones, David L. Dill |
Formal Verification of Out-of-Order Execution Using Incremental Flushing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 10th International Conference, CAV '98, Vancouver, BC, Canada, June 28 - July 2, 1998, Proceedings, pp. 98-109, 1998, Springer, 3-540-64608-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Amit Golander, Shlomo Weiss |
Checkpoint allocation and release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(3), pp. 10:1-10:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
early register release, misprediction, Checkpoint, leakage, out-of-order execution, rollback |
22 | Amit Golander, Shlomo Weiss |
Hiding the misprediction penalty of a resource-efficient high-performance processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(4), pp. 6:1-6:32, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
misprediction, Checkpoints, out-of-order execution, scalable architecture, rollback |
22 | Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Ernie Chan, Robert A. van de Geijn, Field G. Van Zee |
Scheduling of QR Factorization Algorithms on SMP and Multi-Core Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 301-310, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
linear algebra libraries, high-performance, dynamic scheduling, out-of-order execution, QR factorization |
22 | Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Alfredo Remón, Robert A. van de Geijn |
An Algorithm-by-Blocks for SuperMatrix Band Cholesky Factorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2008, 8th International Conference, Toulouse, France, June 24-27, 2008. Revised Selected Papers, pp. 228-239, 2008, Springer, 978-3-540-92858-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
linear algebra libraries, high-performance, dynamic scheduling, out-of-order execution, Cholesky factorization, band matrices |
22 | Ernie Chan, Field G. Van Zee, Paolo Bientinesi, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn |
SuperMatrix: a multithreaded runtime scheduling system for algorithms-by-blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2008, Salt Lake City, UT, USA, February 20-23, 2008, pp. 123-132, 2008, ACM, 978-1-59593-795-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
algorithms-by-blocks, dynamic scheduling, dependency analysis, out-of-order execution |
22 | Kyu-Han Kim, Kang G. Shin |
PRISM: Improving the Performance of Inverse-Multiplexed TCP in Wireless Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 6(12), pp. 1297-1312, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Mobile collaborative community, out-of-order packet delivery, TCP, multi-homing, bandwidth aggregation |
22 | Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita |
Protocol Transducer Synthesis using Divide and Conquer approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 280-285, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
out-of-order transactions, large scale system on a chip, IP-based design, automatic protocol transducer synthesis, nonblocking transactions, design methodologies, communication protocols, protocol conversion, divide and conquer approach |
22 | Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck 0001, Josep Torrellas |
Energy-Efficient Thread-Level Speculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(1), pp. 80-91, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
out-of-order task spawning, chip multiprocessors, Thread-level speculation |
22 | Oleg Bessonov, Dominique Fougère, Bernard Roux |
Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 7th International Conference, PaCT 2003, Novosibirsk, Russia, September 15-19, 2003, Proceedings, pp. 345-353, 2003, Springer, 3-540-40673-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors |
22 | Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero |
A Simple Low-Energy Instruction Wakeup Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings, pp. 99-112, 2003, Springer, 3-540-20359-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Instruction wake up, Low power, Superscalar processors, Out of order execution, CAM, Instruction window |
22 | Andreas Moshovos |
Checkpointing alternatives for high performance, power-aware processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 318-321, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
checkpointing, power-aware, out-of-order execution, renaming, power density |
22 | Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark |
Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(11), pp. 1260-1281, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
instruction window size, register-update unit, simulation, cache, sampling, branch prediction, Microarchitecture, trade-offs, out-of-order execution |
22 | Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao |
A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 78-89, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Scheduling, register renaming, out-of-order issue, Register Pressure |
22 | Graham P. Jones, Nigel P. Topham |
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 65-70, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Access Decoupling, Superscalar, out of order execution, latency hiding |
22 | Dileep Bhandarkar, Jianxun Jason Ding |
Performance Characterization of the Pentium(r) Pro Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 288-299, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Pentium® Pro processor, SPEC CPU95, SYSmark/NT, performance evaluation, computer architecture, workload characterization, speculative execution, out of order execution |
22 | Mayan Moudgill, Stamatis Vassiliadis |
Precise Interrupts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 16(1), pp. 58-67, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
interrupt handlers, out-of-order issue processors, instruction level parallel processors, pipelining, exceptions, superscalar processors, traps, precise interrupts |
22 | Manu Gulati, Nader Bagherzadeh |
Performance Study of a Multithreaded Superscalar Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 291-301, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multithreading, instruction-level parallelism, Superscalars, out-of-order execution |
22 | Steven Wallace, Nirav Dagli, Nader Bagherzadeh |
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 96-101, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz |
22 | William F. Richardson, Erik Brunvand |
Precise exception handling for a self-timed processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 32-37, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems |
21 | Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López 0001, José Duato |
The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-11, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Ming Li 0008, Mo Liu 0001, Luping Ding, Elke A. Rundensteiner, Murali Mani |
Event Stream Processing with Out-of-Order Data Arrival. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 27th International Conference on Distributed Computing Systems Workshops (ICDCS 2007 Workshops), June 25-29, 2007, Toronto, Ontario, Canada, pp. 67, 2007, IEEE Computer Society, 0-7695-2881-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi |
Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 177-180, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Sailesh Krishnamurthy, Michael J. Franklin, Jeffrey Davis, Daniel Farina, Pasha Golovko, Alan Li, Neil Thombre |
Continuous analytics over discontinuous streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2010, Indianapolis, Indiana, USA, June 6-10, 2010, pp. 1081-1092, 2010, ACM, 978-1-4503-0032-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
streams, continuous queries, order, out-of-order |
20 | Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras |
Interval-based models for run-time DVFS orchestration in superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 287-296, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling |
20 | Gregorio Quintana-Ortí, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn |
Solving dense linear systems on platforms with multiple hardware accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 121-130, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
algorithms-by-blocks, depencency analysis, dynamic scheduling, out-of-order execution, gpus |
20 | Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa |
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 647-653, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Instruction Wakeup, Low Power, CAM, Issue Queue, Out-of-Order Processors |
20 | Allon Adir, Hagit Attiya, Gil Shurek |
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(5), pp. 502-515, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
PowerPC architecture, synchronization instructions, models, specification, consistency, Shared memory, multiprocessor systems, out-of-order execution |
20 | Nam Sung Kim, Trevor N. Mudge |
Reducing register ports using delayed write-back queues and operand pre-fetch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 172-182, 2003, ACM, 1-58113-733-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
write queue, low power, instruction level parallelism, register file, out-of-order processor |
20 | Nam Sung Kim, Trevor N. Mudge |
The microarchitecture of a low power register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 384-389, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
write queue, low power, instruction level parallelism, register file, out-of-order processor |
20 | Huamin Chen, Prasant Mohapatra |
CATP: A Context-Aware Transportation Protocol for HTTP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 23rd International Conference on Distributed Computing Systems Workshops (ICDCS 2003 Workshops), 19-22 May 2003, Providence, RI, USA, pp. 922-927, 2003, IEEE Computer Society, 0-7695-1921-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
out-of-order rendering, Transportation protocol, HTTP, UDP, head-of-line blocking |
20 | Sébastien Nussbaum, James E. Smith 0001 |
Statistical Simulation of Symmetric Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 35th Annual Simulation Symposium (ANSS-35 2002), San Diego, California, USA, 14-18 April 2002, pp. 89-97, 2002, IEEE Computer Society, 0-7695-1552-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SimpleMP, Simulation, Performance, Architecture, multiprocessor, Statistical, Memory Hierarchy, systems, SMP, superscalar, Fast, shared bus, out-of-order |
20 | Eric Schnarr, Mark D. Hill, James R. Larus |
Facile: A Language and Compiler for High-Performance Processor Simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Snowbird, Utah, USA, June 20-22, 2001, pp. 321-331, 2001, ACM, 1-58113-414-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
micro-architecture simulation, out-of-order processor simulation, partial evaluation, memoization |
20 | Ramon Canal, Antonio González 0001 |
Reducing the complexity of the issue logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 15th international conference on Supercomputing, ICS 2001, Sorrento, Napoli, Italy, June 16-21, 2001, pp. 312-320, 2001, ACM, 1-58113-410-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
complexity-effective design, instruction issue logic, wide-issue superscalar, out-of-order issue |
20 | Jiannong Cao 0001, Y. Liu, Li Xie 0001, Kang Zhang 0001 |
Portable Runtime Support for Graph-oriented Parallel and Distributed Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 5th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2000), 7-10 December 2000, Dallas / Richardson, TX, USA, pp. 72-77, 2000, IEEE Computer Society, 0-7695-0936-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dynamic speculation of data dependence, instruction reissue, register update unit, Instruction level parallelism, out-of-order execution |
20 | Thomas Lundqvist, Per Stenström |
Timing Anomalies in Dynamically Scheduled Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 20th IEEE Real-Time Systems Symposium, Phoenix, AZ, USA, December 1-3, 1999, pp. 12-21, 1999, IEEE Computer Society, 0-7695-0475-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
timing anomaly, Real-time systems, resource allocation, timing analysis, worst-case execution time, out-of-order execution, dynamically scheduled processor |
20 | Toshinori Sato |
Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10285-10292, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
dynamic speculation of data dependence, instruction reissue, instruction level parallelism, out-of-order execution, address prediction |
20 | Mateo Valero, Tomás Lang, Montse Peiron, Eduard Ayguadé |
Conflict-Free Access for Streams in Multimodule Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(5), pp. 634-646, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
decoupled access, multimodule memories, out-of-order access, streams with constant strides, vector processors, Conflict-free access, storage schemes |
20 | Eric Hao, Po-Yung Chang, Yale N. Patt |
The effect of speculatively updating branch history on branch prediction accuracy, revisited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 228-232, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
two-level adaptive branch prediction, speculative execution, superscalar processors, out-of-order execution, dynamic branch prediction |
20 | Eric Sprangle, Yale N. Patt |
Facilitating superscalar processing via a combined static/dynamic register renaming scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 143-147, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
superscalar processors, out-of-order execution, register renaming, predicated execution |
20 | B. Ramakrishna Rau |
Dynamically scheduled VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 80-92, 1993, ACM / IEEE Computer Society, 0-8186-5280-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors |
20 | Mateo Valero, Tomás Lang, Eduard Ayguadé |
Conflict-free access of vectors with power-of-two strides. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 6th international conference on Supercomputing, ICS 1992, Washington, DC, USA, July 19-24, 1992, pp. 149-156, 1992, ACM, 0-89791-485-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
multi-module memories, out-of-order access, power-of-two strides, vector processors, conflict-free access, storage schemes |
19 | Perry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen |
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 187-196, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Weihaw Chuang, Brad Calder |
Predicate prediction for efficient out-of-order execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 183-192, 2003, ACM, 1-58113-733-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
predicate prediction, predicated execution |
18 | Yu Bai 0001, R. Iris Bahar |
A low-power in-order/out-of-order issue queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(2), pp. 152-179, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
instruction issue logic, low power, High-performance |
18 | Yu Bai 0001, R. Iris Bahar |
A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 139-148, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim |
In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 195-, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Miroslav N. Velev |
Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 28-35, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Alok Garg, Fernando Castro, Michael C. Huang 0001, Daniel Chaver, Luis Piñuel, Manuel Prieto 0001 |
Substituting associative load queue with simple hash tables in out-of-order microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 268-273, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
LSQ, scalability, hash table, memory disambiguation |
17 | Christian Jacobi 0002 |
Formal Verification of Complex Out-of-Order Pipelines by Combining Model-Checking and Theorem-Proving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 14th International Conference, CAV 2002,Copenhagen, Denmark, July 27-31, 2002, Proceedings, pp. 309-323, 2002, Springer, 3-540-43997-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Shuvendu K. Lahiri, Sanjit A. Seshia, Randal E. Bryant |
Modeling and Verification of Out-of-Order Microprocessors in UCLID. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings, pp. 142-159, 2002, Springer, 3-540-00116-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Daniel Tate, Gordon B. Steven, Fleur L. Steven |
Static Scheduling for Out-of-order Instruction Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACAC ![In: 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January - 3 February 2000, Canberra, Australia, pp. 90-96, 2000, IEEE Computer Society, 0-7695-0512-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Parthasarathy Ranganathan, Kourosh Gharachorloo, Sarita V. Adve, Luiz André Barroso |
Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 307-318, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Stéphan Jourdan, Pascal Sainrat, Daniel Litaize |
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 117-125, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001 |
Early Register Release for Out-of-Order Processors with RegisterWindows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 225-234, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001 |
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 75-84, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Joseph J. Sharkey, Dmitry Ponomarev 0001 |
Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2006 International Conference on Parallel Processing (ICPP 2006), 14-18 August 2006, Columbus, Ohio, USA, pp. 329-336, 2006, IEEE Computer Society, 0-7695-2636-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt |
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(12), pp. 1556-1571, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
processor performance modeling, speculative execution, runahead execution, Single data stream architectures |
17 | Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero |
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 32(3), pp. 3-10, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra |
Modeling Out-of-Order Processors for Software Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 5-8 December 2004, Lisbon, Portugal, pp. 92-103, 2004, IEEE Computer Society, 0-7695-2247-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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