Search results for "peak-power"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang	RT-level vector selection for realistic peak power simulation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	peak power estimation, vector selection, power modeling
87	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
79	Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi 0001	A fast clock scheduling for peak power reduction in LSI.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	general-synchronous framework, peak power reduction, power consumption estimation, clock scheduling
76	Kambiz Rahimi	Minimizing peak power in synchronous logic circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power optimization, peak power, clock scheduling
75	Kuen-Jong Lee, Tsung-Chu Huang	An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	multiple scan chains, interleaving scan, test power reduction, peak power reduction
74	Praveen Bhojwani, Jason D. Lee, Rabi N. Mahapatra	SAPP: scalable and adaptable peak power management in nocs.	ISLPED	2007	DBLP DOI BibTeX RDF	network-on-chip, NoC, peak power
68	Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar 0002	Reducing peak power with a table-driven adaptive processor core.	MICRO	2009	DBLP DOI BibTeX RDF	resource resizing, voltage variation, peak power, adaptive architectures, decoupling capacitance
68	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
68	Xiaodong Zhang 0010, Kaushik Roy 0001	Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction.	DFT	1999	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Low Power BIST, Testing, Low Power, Cellular Automata, Peak Power
67	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Simultaneous peak and average power minimization during datapath scheduling for DSP processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
65	David Meisner, Thomas F. Wenisch	Peak power modeling for data center servers with switched-mode power supplies.	ISLPED	2010	DBLP DOI BibTeX RDF	switched-mode power supplies, peak power
63	Yuho Jin, Eun Jung Kim 0001, Ki Hwan Yum	Peak Power Control for a QoS Capable On-Chip Network.	ICPP	2005	DBLP DOI BibTeX RDF
62	Ranganathan Sankaralingam, Nur A. Touba	Controlling Peak Power During Scan Testing.	VTS	2002	DBLP DOI BibTeX RDF
58	Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham	Functionally valid gate-level peak power estimation for processors.	ISQED	2009	DBLP DOI BibTeX RDF
58	Ranganathan Sankaralingam, Nur A. Touba	Inserting Test Points to Control Peak Power During Scan Testing.	DFT	2002	DBLP DOI BibTeX RDF
58	Asad Mahmood, Emmanuel Jaffrot	Computationally Efficient Algorithm for Optimal Power Allocation in Multicarrier Systems with Peak-Power Constraint.	VTC Spring	2007	DBLP DOI BibTeX RDF
57	Wen-Tsong Shiue	High Level Synthesis for Peak Power Minimization Using ILP.	ASAP	2000	DBLP DOI BibTeX RDF	Peak power minimization, latency-constrained scheduling, High-level synthesis, low power design, integer linear programming, force-directed scheduling
57	Xiaodong Zhang 0010, Kaushik Roy 0001	Peak Power Reduction in Low Power BIST.	ISQED	2000	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Testing, Low Power
55	Li Shang, Li-Shiuan Peh, Niraj K. Jha	PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
54	Wesley M. Felter, Karthick Rajamani, Tom W. Keller, Cosmin Rusu	A performance-conserving approach for reducing peak power consumption in server systems.	ICS	2005	DBLP DOI BibTeX RDF	power management, power modeling, processor simulation
53	Jaehwan Kim, SungHwan Park, Jong-Wha Chong	Peak power control algorithm for multi-processor SoC.	ICUIMC	2009	DBLP DOI BibTeX RDF	peak power control, low power, multi-core, task scheduling
51	Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba	Static Compaction Techniques to Control Scan Vector Power Dissipation.	VTS	2000	DBLP DOI BibTeX RDF	Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing
50	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Peak Power Minimization Through Datapath Scheduling.	ISVLSI	2003	DBLP DOI BibTeX RDF
50	Lars K. Rasmussen, Albert Guillen i Fabregas, Khoa D. Nguyen	Power allocation for block-fading channels with arbitrary input constellations.	IEEE Trans. Wirel. Commun.	2009	DBLP DOI BibTeX RDF
49	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara	Graph theoretic approach for scan cell reordering to minimize peak shift power.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power droop, scan chain reordering, peak power
49	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
48	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Effects of delay models on peak power estimation of VLSI sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	variable delay, sustainable power, n-cycle power, peak power, genetic optimization
43	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	BIST Design, Test, Low-power Design, Energy Consumption
43	Saraju P. Mohanty, N. Ranganathan	A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
42	Li Shang, Li-Shiuan Peh, Niraj K. Jha	PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks.	ICS	2003	DBLP DOI BibTeX RDF	low-power, interconnection networks, thermal management
42	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Peak power estimation of VLSI circuits: new peak power measures.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
42	Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang 0002	Peak Power Minimization through Power Management Scheduling.	APCCAS	2006	DBLP DOI BibTeX RDF
42	Saraju P. Mohanty, Nagarajan Ranganathan	A framework for energy and transient power reduction during behavioral synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
41	Ki-Bog Kim, Chi-Ho Lin	An Optimal ILP Model for Delay Time to Minimize Peak Power and Area.	IWSOC	2005	DBLP DOI BibTeX RDF	B&B, scheduling, Pipelined, ILP, area, peak-power, datapath
41	Nabil Badereddine, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
40	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
39	Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang	A novel ACO-based pattern generation for peak power estimation in VLSI circuits.	ISQED	2009	DBLP DOI BibTeX RDF
39	Zhen Zhao, Jinian Bian, Zhipeng Liu, Yunfeng Wang, Kang Zhao	High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization.	APCCAS	2006	DBLP DOI BibTeX RDF
38	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	low power, BIST, scan, pseudo-random, peak power
37	Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Ricardo Bianchini	Limiting the power consumption of main memory.	ISCA	2007	DBLP DOI BibTeX RDF	power and energy management, performance, main memory
37	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
36	Michael S. Hsiao	Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits.	DATE	1999	DBLP DOI BibTeX RDF
35	Noureddine Chabini, Wayne H. Wolf	An approach for integrating basic retiming and software pipelining.	EMSOFT	2004	DBLP DOI BibTeX RDF	embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
35	Shivratna Giri Srinivasan, Mahesh K. Varanasi	Optimal Constellations for the Low-SNR Noncoherent MIMO Block Rayleigh-Fading Channel.	IEEE Trans. Inf. Theory	2009	DBLP DOI BibTeX RDF
35	Nabil Badereddine, Patrick Girard 0001, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
35	Fadel F. Digham, Mohamed-Slim Alouini, Sant Arora	Variable-rate variable-power non-coherent M-FSK scheme for power limited systems.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
34	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal	On Minimization of Peak Power for Scan Circuit during Test.	ETS	2009	DBLP DOI BibTeX RDF	Power droop, Test vector re-ordering, Low power test, Peak Power
34	Mackenzie R. Scott, Rajeevan Amirtharajah	Pulse width modulation for reduced peak power full-swing on-chip interconnect.	ISLPED	2009	DBLP DOI BibTeX RDF	low power interconnect, peak power, pulse width modulation
34	Diganchal Chakraborty, P. P. Chakrabarti 0001, Arijit Mondal, Pallab Dasgupta	A Framework for Estimating Peak Power in Gate-Level Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
34	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
33	Nabil Badereddine, Patrick Girard 0001, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.	PATMOS	2005	DBLP DOI BibTeX RDF
32	F. Boccardi, Giuseppe Caire	The p-Sphere Encoder: Peak-Power Reduction by Lattice Precoding for the MIMO Gaussian Broadcast Channel.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
32	F. Boccardi, Giuseppe Caire	The p-Sphere Encoder: Peak-Power Reduction by Lattice Precoding for the MIMO Gaussian Broadcast Channel.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
30	Weiwei Kang, Steve Hranilovic	Power reduction techniques for multiple-subcarrier modulated diffuse wireless optical channels.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
30	Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura	A High Performance Cluster System Design by Adaptie Power Control.	IPDPS	2007	DBLP DOI BibTeX RDF
29	Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	ALPS: A Peak Power Estimation Tool for Sequential Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
28	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
27	Mustafa Cenk Gursoy	On the Capacity of Training-Based Transmissions with Input Peak Power Constraints.	ICC	2008	DBLP DOI BibTeX RDF
27	Jun Chen 0005, Venugopal V. Veeravalli	Capacity Results for Block-Stationary Gaussian Fading Channels With a Peak Power Constraint.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
27	M. Julia Fernández-Getino García, Ove Edfors, José Manuel Páez-Borrallo	Peak power reduction for OFDM systems with orthogonal pilot sequences.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
27	Osamu Muta, Yoshihiko Akaiwa	A Weighting Factor Estimation Scheme for Phase-Control based Peak Power Reduction of Turbo-coded OFDM signal.	VTC Spring	2006	DBLP DOI BibTeX RDF
27	K. Najeeb, Vishal Gupta, V. Kamakoti 0001, Madhu Mutyam	Delay and peak power minimization for on-chip buses using temporal redundancy.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	low-power, coding, crosstalk
27	Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz	On test generation for transition faults with minimized peak power dissipation.	DAC	2004	DBLP DOI BibTeX RDF	test generation, power dissipation, transition faults
27	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
27	Sudhakar Bobba	Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits		2000	RDF
27	Raviv Raich, Hua Qian, Guo Tong Zhou	Optimization of SNDR for amplitude-limited nonlinearities.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
26	Qing Wu 0002, Qinru Qiu, Massoud Pedram	Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
26	Xiaobo Fan, Wolf-Dietrich Weber, Luiz André Barroso	Power provisioning for a warehouse-sized computer.	ISCA	2007	DBLP DOI BibTeX RDF	power provisioning, energy efficiency, power modeling
26	Haris Gacanin, Fumiyuki Adachi	A Comprehensive Performance Comparison of OFDM/TDM Using MMSE-FDE and Conventional OFDM.	VTC Spring	2008	DBLP DOI BibTeX RDF
24	Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
23	Alessandro Novello, Gabriele Atzeni, Tim Keller, Taekwang Jang	A 4.1W/mm² Peak Power Density and 77% Peak Efficiency Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators and a Resonant LC Flying Impedance in 22nm FDSOI CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
23	Yuan Li, Zhihong Lin, Tao Xia, Jiqing Xu, Yuxiang Tang, Shenglong Zhuo, Xuefeng Chen 0004, Xudong Zhang, Hengwei Yu, Huanli Jiang, Patrick Yin Chiang	A 2GHz On-Chip-Oscilloscope with High Accuracy Pulse Width Detection for Auto-Peak-Power Controller & Peak-Current Detector in Voltage-Mode DToF Driver.	ISCAS	2023	DBLP DOI BibTeX RDF
23	Nghia Tang, Wookpyo Hong, Bai Nguyen 0001, Zhiyuan Zhou, Jong-Hoon Kim, Deukhyoun Heo	Fully Integrated Switched-Inductor-Capacitor Voltage Regulator With 0.82-A/mm2 Peak Current Density and 78% Peak Power Efficiency.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
23	Mengmeng Du, Hoi Lee, Jin Liu 0004	A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
23	Mengmeng Du, Hoi Lee	A 5-MHz 91% peak-power-efficiency buck regulator with auto-selectable peak- and valley-current control.	CICC	2010	DBLP DOI BibTeX RDF
23	Shigeru Tomisato, Masaharu Hata	Peak Power Reduction Method Using Adaptive Peak Reduction Signal Level Control for OFDM Transmission Systems.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
23	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Statistical power profile correlation for realistic thermal estimation.	ASP-DAC	2008	DBLP DOI BibTeX RDF
23	Charles Lefurgy, Xiaorui Wang, Malcolm Allen-Ware	Server-Level Power Control.	ICAC	2007	DBLP DOI BibTeX RDF
23	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
22	Mohammad Mehdi Hassani, Reza Berangi	Improving the COWLS algorithm for hardware software co-synthesis of wireless client-server systems using preference vectors and peak power information.	CompSysTech	2007	DBLP DOI BibTeX RDF	embedded systems, client server systems, wireless systems, low power consumption, hardware-software co-synthesis
22	Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim 0001, Thomas Chen	A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
22	Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti 0001	A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
22	Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi	ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis.	VLSI Design	2004	DBLP DOI BibTeX RDF
21	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Variation-Tolerant, Power-Safe Pattern Generation.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	low-power ATPG, process variation, IR drop, peak power, power profiling
21	Chusit Pradabpet, K. Eupree, Sorawat Chivapreecha, Kobchai Dejhan	A New PAPR Reduction Technique for OFDM-WLAN in 802.11a Systems.	SNPD	2008	DBLP DOI BibTeX RDF	SLM, APPR, OFDM, PAPR, Wlan
21	Ali Manzak, Chaitali Chakrabarti	Variable voltage task scheduling algorithms for minimizing energy/power.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
21	David Meisner, Brian T. Gold, Thomas F. Wenisch	PowerNap: eliminating server idle power.	ASPLOS	2009	DBLP DOI BibTeX RDF	power management, servers
21	Mircea R. Stan, Wayne P. Burleson	Bus-invert coding for low-power I/O.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
20	Osamu Muta, Yoshihiko Akaiwa	Peak Power Reduction Method Based on Structure of Parity-Check Matrix for LDPC Coded OFDM Transmission.	VTC Spring	2007	DBLP DOI BibTeX RDF
20	A. Dhammika S. Jayalath, Chintha Tellambura	SLM and PTS peak-power reduction of OFDM signals without side information.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
20	Dominic A. Antonelli, Alan Jay Smith, Jan-Willem van de Waerdt	Power consumption and reduction in a real, commercial multimedia core.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	tm3270, multimedia, power, energy, compiler optimization, cache memory, embedded processor
20	Lan Zhang 0007, Ying-Chang Liang, Yan Xin 0001	Joint Beamforming and Power Allocation for Multiple Access Channels in Cognitive Radio Networks.	IEEE J. Sel. Areas Commun.	2008	DBLP DOI BibTeX RDF
20	Myung-Hoon Yang, YongJoon Kim, Sunghoon Chun, Sungho Kang 0001	An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Built-in self-test, Power consumption, Linear feedback shift register, Reseeding
20	Charles Lefurgy, Xiaorui Wang, Malcolm Allen-Ware	Power capping: a prelude to power shifting.	Clust. Comput.	2008	DBLP DOI BibTeX RDF	Power capping, Power shifting, Power budget, Power supplies, Power management, Feedback control, Servers, Provisioning
20	Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li	Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling.	ISCAS	2007	DBLP DOI BibTeX RDF
20	Thomas L. Martin, Daniel P. Siewiorek, Asim Smailagic, Matthew Bosworth, Matthew Ettus, Jolin M. Warren	A case study of a system-level approach to power-aware computing.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	battery properties, Power-aware, handheld computers, energy-aware, dynamic power management, multihop wireless network
19	Travis Deyle, Matthew S. Reynolds	Surface based wireless power transmission and bidirectional communication for autonomous robot swarms.	ICRA	2008	DBLP DOI BibTeX RDF
19	K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti 0001, Vivekananda M. Vedula	Power Virus Generation Using Behavioral Models of Circuits.	VTS	2007	DBLP DOI BibTeX RDF	Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models
19	Enric Musoll	Speculating to reduce unnecessary power consumption.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	low-power microarchitectures, Low-power design
19	Enric Musoll	Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors.	MICRO	1999	DBLP DOI BibTeX RDF