Search results for "pin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	Cliff Chiung-Yu Lin, Yao-Wen Chang	ILP-based pin-count aware design methodology for microfluidic biochips.	DAC	2009	DBLP DOI BibTeX RDF	microfludics, design methodology, integer linear programming, biochip
97	Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish Patil, Artur Klauser, P. Geoffrey Lowney, Steven Wallace, Vijay Janapa Reddi, Kim M. Hazelwood	Pin: building customized program analysis tools with dynamic instrumentation.	PLDI	2005	DBLP DOI BibTeX RDF	program analysis tools, instrumentation, dynamic compilation
97	Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong	Min-cost flow-based algorithm for simultaneous pin assignment and routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
80	Mohammad Mannan, Paul C. van Oorschot	Weighing Down "The Unbearable Lightness of PIN Cracking".	Financial Cryptography	2008	DBLP DOI BibTeX RDF
80	Jurjen Westra, Patrick Groeneveld	Post-Placement Pin Optimiztion.	ISVLSI	2005	DBLP DOI BibTeX RDF
78	Tilo Meister, Jens Lienig, Gisbert Thomke	Novel Pin Assignment Algorithms for Components with Very High Pin Counts.	DATE	2008	DBLP DOI BibTeX RDF
65	Volker Roth 0002, Kai Richter 0002, Rene Freidinger	A PIN-entry method resilient against shoulder surfing.	CCS	2004	DBLP DOI BibTeX RDF	cognitive trapdoor games, ATM, password, PIN, shoulder surfing
65	Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai	Interchangeable pin routing with application to package layout.	ICCAD	1996	DBLP DOI BibTeX RDF	BGA, all-angle wiring, interchangeable pin routing, min-cost max-flow heuristic, multiple layers, octilinear wiring, package layout, pin redistribution, prerouted nets, rectilinear wiring, test fixture routing, triangulated routing network, CAD, NP-complete, ASIC, circuit layout CAD, speed, PGA, input output, routing problems
65	Ines Peters, Paul Molitor	Priority driven channel pin assignment.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	polynomial time improvement, linear channel pin assignment, LCPA algorithms, minimum channel density, vertical constraints, priority driven channel pin assignment, channel height, computational complexity, VLSI, VLSI, network routing, circuit layout CAD, running time, integrated circuit layout, priority schedule, channel routing
65	Charles M. Fiduccia	Bused Hypercubes and Other Pin-Optimal Networks.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	pin minimisation, simultaneous data exchange, pin-optimal networks, massively parallelarchitectures, chassis, bused hypercubeinterconnection network, clock tick, hypercube networks, processing elements, ports, chip, board
64	Ryo Oguchi, Yasuaki Kakehi, Keita Takahashi 0001, Takeshi Naemura	Photonastic surface: pin matrix type display controlled with light.	Advances in Computer Entertainment Technology	2008	DBLP DOI BibTeX RDF	PVLC projector, pin matrix type 3D form display
64	Yong Sin Kim, Sangho Shin, Sung-Mo Kang	A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration.	ISCAS	2006	DBLP DOI BibTeX RDF
64	Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida	Pin assignment with global routing for VLSI building block layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
64	Jason Cong	Pin assignment with global routing for general cell designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
61	Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen	Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign.	ASP-DAC	2007	DBLP DOI BibTeX RDF
58	Matthew Canton	The presence table: a reactive surface for ambient connection.	TEI	2011	DBLP DOI BibTeX RDF
56	Tao Xu 0002, Krishnendu Chakrabarty	Automated design of digital microfluidic lab-on-chip under pin-count constraints.	ISPD	2008	DBLP DOI BibTeX RDF	array partition, cross-referencing, lab-on-chip, pin-count constraints, microfluidics
56	Thorsten Völkel, Gerhard Weber 0002, Ulrich Baumann	Tactile Graphics Revised: The Novel BrailleDis 9000 Pin-Matrix Device with Multitouch Input.	ICCHP	2008	DBLP DOI BibTeX RDF	pin-matrix device, assistive technology, visually impaired, Tactile graphics
56	Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong	An algorithm for integrated pin assignment and buffer planning.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	min-cost maximum flow, Buffer insertion, pin assignment
56	Dianne Brotherson	Turning the titanic: changing a PIN to a password.	SIGUCCS	2004	DBLP DOI BibTeX RDF	PIN numbers, strong passwords, passwords, conversion, password security, login
56	Hua Xiang 0001, D. F. Wong 0001, Xiaoping Tang	An algorithm for integrated pin assignment and buffer planning.	DAC	2002	DBLP DOI BibTeX RDF	min-cost maximum flow, buffer insertion, pin assignment
55	Shashank Prasad	Fast Congestion Aware Routing for Pin Assignment.	VLSI Design	2008	DBLP DOI BibTeX RDF
55	Wei-Kei Mak, C.-L. Lai	On Constrained Pin-Mapping for FPGA-PCB Codesign.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
55	Le-Chin Eugene Liu, Carl Sechen	Multilayer pin assignment for macro cell circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
54	Kostas Daniilidis, Reinhard Klette, Ales Leonardis (eds.)	Imaging Beyond the Pin-hole Camera. 12th Seminar on Theoretical Foundations of Computer Vision, 13.06. - 18.06.2004	Imaging Beyond the Pin-hole Camera. 12th Seminar on Theoretical Foundations of Computer Vision	2004	DBLP BibTeX RDF
54	Ralf Reulke, Aloysius Wehr, Denis Griesbach	Mobile Panoramic Mapping using CCD-Line Camera and Laser Scanner.	Imaging Beyond the Pin-hole Camera. 12th Seminar on Theoretical Foundations of Computer Vision	2004	DBLP BibTeX RDF
54	Kostas Daniilidis, Reinhard Klette, Ales Leonardis	04251 - Imaging Beyond the Pinhole Camera.	Imaging Beyond the Pin-hole Camera. 12th Seminar on Theoretical Foundations of Computer Vision	2004	DBLP BibTeX RDF
51	Saar Drimer, Steven J. Murdoch, Ross J. Anderson	Thinking Inside the Box: System-Level Failures of Tamper Proofing.	SP	2008	DBLP DOI BibTeX RDF	Chip and PIN, PIN entry devices, certification, incentives, smartcard, banking, tamper resistance, common criteria, EMV
50	Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen	Printed circuit board routing and package layout codesign.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
48	Yuichi Komano, Kazuo Ohta, Hideyuki Miyake, Atsushi Shimbo	Algorithmic Tamper Proof (ATP) Counter Units for Authentication Devices Using PIN.	ACNS	2009	DBLP DOI BibTeX RDF	algorithmic tamper proof (ATP), counter unit, PIN authentication
48	Alexander De Luca, Bernhard Frauendienst, Sebastian Boring, Heinrich Hussmann	My phone is my keypad: privacy-enhanced PIN-entry on public terminals.	OZCHI	2009	DBLP DOI BibTeX RDF	PIN entry, security, privacy, mobile devices
48	Riccardo Focardi, Flaminia L. Luccio, Graham Steel	Blunting Differential Attacks on PIN Processing APIs.	NordSec	2009	DBLP DOI BibTeX RDF	Financial Cryptography, PIN Verification, Security APIs
48	Omer Berkman, Odelia Moshe Ostrovsky	The Unbearable Lightness of PIN Cracking.	Financial Cryptography	2007	DBLP DOI BibTeX RDF	API attack, Financial PIN Processing API, Phantom Withdrawal, VISA PVV, IBM 3624, Insider attack, HSM, EMV, Security API
48	Alexander De Luca, Roman Weiss, Heiko Drewes	Evaluation of eye-gaze interaction methods for security enhanced PIN-entry.	OZCHI	2007	DBLP DOI BibTeX RDF	PIN entry, cash machine, look & shoot, security, privacy, dwell time, gaze gestures, eye gaze interaction
48	Tao Xu 0002, Krishnendu Chakrabarty	Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	connect-5 algorithm, droplet trace, droplet-based microfluidics, pin-constrained biochip design, synthesis
47	Alexander De Luca, Katja Hertzschuch, Heinrich Hussmann	ColorPIN: securing PIN entry through indirect input.	CHI	2010	DBLP DOI BibTeX RDF	atm, colorpin, security, authentication
47	Cliff Chiung-Yu Lin, Yao-Wen Chang	Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips.	DAC	2010	DBLP DOI BibTeX RDF	cross-contamination, microfludics, design methodology, biochip
47	Matthew G. Stout, Kenneth P. Tumin	Innovative Test Solutions for Pin-Limited Microcontrollers.	ISQED	2008	DBLP DOI BibTeX RDF	Freescale, Stout, Tumin, test, testing, DFT, scan, microcontroller, design-for-test, pins
47	Gi-Hun Yang, Ki-Uk Kyung, Mandayam A. Srinivasan, Dong-Soo Kwon	Development of Quantitative Tactile Display Device to Provide Both Pin- Array-Type Tactile Feedback and Thermal Feedback.	WHC	2007	DBLP DOI BibTeX RDF
47	Jurjen Westra, Patrick Groeneveld	Towards Integration of Quadratic Placement and Pin Assignment.	ISVLSI	2005	DBLP DOI BibTeX RDF
47	Scott Hauck, Gaetano Borriello	Pin assignment for multi-FPGA systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
47	Hannah Honghua Yang, Martin D. F. Wong	Circuit clustering for delay minimization under area and pin constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
44	Bill Jackson, Tibor Jordán	Pin-Collinear Body-and-Pin Frameworks and the Molecular Conjecture.	Discret. Comput. Geom.	2008	DBLP DOI BibTeX RDF	Rigidity of frameworks, Body-and-hinge frameworks, Bar-and-joint frameworks, Molecular Conjecture
44	Rohini Gupta, John Willis, Lawrence T. Pileggi	Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
43	Vashek Matyas, Daniel Cvrcek, Jan Krhovjak, Marek Kumpost	Authorizing Card Payments with PINs.	Computer	2008	DBLP DOI BibTeX RDF	Chip and PIN technology, PIN pads, e-commerce
42	Piotr Bródka, Katarzyna Musial, Przemyslaw Kazienko	Efficiency of Node Position Calculation in Social Networks.	KES (2)	2009	DBLP DOI BibTeX RDF	node position, PIN algorithm, calculation efficiency, social network analysis
42	Christopher R. Wagner, Susan J. Lederman, Robert D. Howe	A Tactile Shape Display Using RC Servomotors.	Symposium on Haptic Interfaces for Virtual Environment and Teleoperator Systems	2002	DBLP DOI BibTeX RDF	tactile shape display, spatially distributed forces, taction, teletaction, mechanical pin, fingertip, servo, rc servo, servomotor, tactile array, haptics, tactile display
42	Hector Ouilhet	Google Sky Map: using your phone as an interface.	Mobile HCI	2010	DBLP DOI BibTeX RDF
42	Alexander De Luca, Marc Langheinrich, Heinrich Hussmann	Towards understanding ATM security: a field study of real world ATM use.	SOUPS	2010	DBLP DOI BibTeX RDF	design implications, security, authentication, ATM, field study, lessons learned
42	Prosenjit Bose, Godfried T. Toussaint	Computing the Constrained Euclidean Geodesic and Link Center of a Simple Polygon with Application.	Computer Graphics International	1996	DBLP DOI BibTeX RDF
42	Doug Burger, James R. Goodman, Alain Kägi	Memory Bandwidth Limitations of Future Microprocessors.	ISCA	1996	DBLP DOI BibTeX RDF
39	Bella Dubrov, Haggai Eran, Ari Freund 0001, Edward F. Mark, Shyam Ramji, Timothy A. Schell	Pin Assignment Using Stochastic Local Search Constraint Programming.	CP	2009	DBLP DOI BibTeX RDF	ASIC, Constraint Programming, EDA, Stochastic Local Search, Chip Design, Pin Assignment
39	Zhicai Ou, Hong Qiao	Analysis of Stable Grasping for One-Parameter Four-Pin Gripper.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Four-Pin Gripper, Form Closure, Attractive Region, Grasp
39	Marcel Jacomet, Josef Goette, Andreas Eicher	On Using Fingerprint-Sensors for PIN-Pad Entry.	DELTA	2008	DBLP DOI BibTeX RDF	fingerprint sensors, PIN-pad entry, security, smart-cards, exception handling, pressure sensing
39	Sara Ljungblad, Maria Håkansson, Lars Erik Holmquist	Ubicomp challenges in collaborative scheduling: Pin&Play at the Göteborg film festival.	Pers. Ubiquitous Comput.	2007	DBLP DOI BibTeX RDF	Pin? Ubiquitous computing, Paper-based interaction, Large-scale surfaces, Tangible interfaces, Collaborative scheduling
39	William L. Hwang, Fei Su, Krishnendu Chakrabarty	Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*.	DAC	2006	DBLP DOI BibTeX RDF	microfluidic biochips, pin-constrained design, virtual partitioning
39	Masashi Nakatani, Hiroyuki Kajimoto, Naoki Kawakami, Susumu Tachi	Tactile sensation with high-density pin-matrix.	APGV	2005	DBLP DOI BibTeX RDF	pin-matrix, tactile sensation enhancement, tactile sensation
39	Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier	Enhanced Reduced Pin-Count Test for Full-Scan Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
39	Wuudiann Ke	Hybrid Pin Control Using Boundary-Scan And Its Applications.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Boundary-Scan (B-S), Hybrid Pin Control, Fault Injection, Delay Test
39	Tsung-Wei Huang, Tsung-Yi Ho	A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips.	ISPD	2010	DBLP DOI BibTeX RDF	routing, ilp, microfluidic, biochip
39	Kirsten A. Peters	Influence of Real-World Ten-Pin Bowling Experience on Performance during First-Time Nintendo Wii Bowling Practice.	HCI (4)	2009	DBLP DOI BibTeX RDF	Motor program, transfer of skill, real-world vs. simulation, motion capture, video games, gesture-based interaction, motor learning
39	Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto	Integrated interlayer via planning and pin assignment for 3D ICs.	SLIP	2009	DBLP DOI BibTeX RDF
39	Umapada Pal 0001, Rami Kumar Roy, Kaushik Roy 0004, Fumitaka Kimura	Indian Multi-Script Full Pin-code String Recognition for Postal Automation.	ICDAR	2009	DBLP DOI BibTeX RDF
39	Kher Hui Ng, Boriana Koleva, Steve Benford	The iterative development of a tangible pin-board to symmetrically link physical and digital documents.	Pers. Ubiquitous Comput.	2007	DBLP DOI BibTeX RDF	Prototyping, Tangible user interfaces, Actuation, Interactive surfaces
39	Daniel Garcia-Romero, Joaquin Gonzalez-Rodriguez, Julian Fiérrez-Aguilar, Javier Ortega-Garcia	U-NORM Likelihood Normalization in PIN-Based Speaker Verification Systems.	AVBPA	2003	DBLP DOI BibTeX RDF
39	Dongsheng Wang 0012, Ping Zhang 0001, Chung-Kuan Cheng, Arunabha Sen	A Performance-Driven I/O Pin Routing Algorithm.	ASP-DAC	1999	DBLP DOI BibTeX RDF
35	Kim M. Hazelwood, Artur Klauser	A dynamic binary instrumentation engine for the ARM architecture.	CASES	2006	DBLP DOI BibTeX RDF	binary instrumentation, pin, dynamic translation, embedded architectures
34	Ines Viskic, Samar Abdi, Daniel D. Gajski	Automatic generation of embedded communication SW for heterogeneous MPSoC platforms.	LCTES	2007	DBLP DOI BibTeX RDF	custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication
33	Guanyang Liu, Yuru Zhang, William T. Townsend	Force modeling for tooth preparation in a dental training system.	Virtual Real.	2008	DBLP DOI BibTeX RDF	Force model, Contact geometry, Force measure, Human’s operating tracking, Haptic interaction
33	David A. Bader, Kamesh Madduri	A Graph-Theoretic Analysis of the Human Protein-Interaction Network Using Multicore Parallel Algorithms.	IPDPS	2007	DBLP DOI BibTeX RDF
33	Michael A. Taylor, Aaron R. Ferber, J. Edward Colgate	Assessing the Efficacy of Variable Compliance Tactile Displays.	WHC	2007	DBLP DOI BibTeX RDF
33	David C. Keezer, Q. Zhou	Alternative interface methods for testing high speed bidirectional signals.	ITC	1998	DBLP DOI BibTeX RDF
31	Seong-I Lei, Wai-Kei Mak	Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign.	FPL	2011	DBLP DOI BibTeX RDF	Constrained Pin Assignment, Escape Routing
31	Valerie Pezzullo, Steven Voinier	Experimental and Numerical Study of the Effect of Geometric Parameters on Liquid Single-Phase Pressure Drop in Micro-Scale Pin-Fin Arrays.	CLUSTER	2011	DBLP DOI BibTeX RDF	Friction factor, Reynolds number, pin-fin, Mesh
31	Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen	Ordered escape routing via routability-driven pin assignment.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	pcb design, routability, escape routing, pin assignment
31	Steven J. Murdoch, Saar Drimer, Ross J. Anderson, Mike Bond	Chip and PIN is Broken.	IEEE Symposium on Security and Privacy	2010	DBLP DOI BibTeX RDF	Chip and PIN, card fraud, bank security, protocol failure, authentication, EMV, security economics
31	Yang Zhao 0001, Ryan Sturmer, Krishnendu Chakrabarty, Vamsee K. Pamula	Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.	VLSI Design	2010	DBLP DOI BibTeX RDF	Digital Microfluidic Biochips, Pin-Constrained Design, Synchronization
31	Peipei Shi, Bo Zhu, Amr M. Youssef	A PIN Entry Scheme Resistant to Recording-Based Shoulder-Surfing.	SECURWARE	2009	DBLP DOI BibTeX RDF	Secure PIN entry, shoulder surfing
31	I-Horng Jeng, Dwen-Ren Tsai, Hou-An Chen, Yi-Chun Yen, Chien-Kang Cheng	Touch-sensitive Alphanumeric Encrypting PIN Pad Design Based on Hamilton-connected Subgraph Recognition.	IIH-MSP	2009	DBLP DOI BibTeX RDF	Touch-sensitive, encrypting PIN pad, personal identification number, Hamilton-connected Subgraph
31	Mark A. Franklin, Donald F. Wann, William J. Thomas	Pin Limitations and Partitioning of VLSI Interconnection Networks.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Banyan, pin limitations, synchronization, interconnection networks, multiprocessors, crossbar
30	Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger	Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	multi-chip modules, network flow, Escape routing
30	Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou	Verification of Pin-Accurate Port Connections.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
30	Ang Jin, Jianhui Jiang, Jiawei Hu, Jungang Lou	A PIN-Based Dynamic Software Fault Injection System.	ICYCS	2008	DBLP DOI BibTeX RDF
30	Tao Xu 0002, William L. Hwang, Fei Su, Krishnendu Chakrabarty	Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Physical design automation, droplets, microfluidics, biochips
30	Tao Xu 0002, Krishnendu Chakrabarty	A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays.	DATE	2007	DBLP DOI BibTeX RDF
30	Fan Mo, Robert K. Brayton	A simultaneous bus orientation and bused pin flipping algorithm.	ICCAD	2007	DBLP DOI BibTeX RDF
30	Yuzheng Ding, Peter Suaris, Nan-Chi Chou	The effect of post-layout pin permutation on timing.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, placement, logic synthesis, timing optimization
30	Jay Jahangiri, Nilanjan Mukherjee 0001, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press	Achieving High Test Quality with Reduced Pin Count Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
30	Daniel Cvrcek, Jan Krhovjak, Vashek Matyas	PIN (and Chip) or Signature: Beating the Cheating?	Security Protocols Workshop	2005	DBLP DOI BibTeX RDF
30	Vashek Matyas	PIN (and Chip) or Signature: Beating the Cheating?	Security Protocols Workshop	2005	DBLP DOI BibTeX RDF
30	Yaniv Shaked, Avishai Wool	Cracking the Bluetooth PIN.	MobiSys	2005	DBLP DOI BibTeX RDF
30	Jacob R. Minz, Mohit Pathak, Sung Kyu Lim	Net and Pin Distribution for 3D Package Global Routing.	DATE	2004	DBLP DOI BibTeX RDF
30	Dong Xiang, Hideo Fujiwara	Handling the pin overhead problem of DFTs for high-quality and at-speed tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
30	Kristof Van Laerhoven, Albrecht Schmidt 0001, Hans-Werner Gellersen	Pin&Play: Networking Objects through Pins.	UbiComp	2002	DBLP DOI BibTeX RDF
30	Tianpei Zhang, Sachin S. Sapatnekar	Optimized pin assignment for lower routing congestion after floorplanning phase.	SLIP	2002	DBLP DOI BibTeX RDF
30	Y. Cheng, Krzysztof Czuba, G. Kompa	K-band phase locked hair-pin oscillator.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
30	Sara Blanc, Joaquin Gracia, Pedro J. Gil	A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques.	DFT	2002	DBLP DOI BibTeX RDF
30	Rodger Schuttert, Frans G. M. de Jong, Ben Kup	Improved Test Monitor Circuit in Power Pin DfT.	VTS	2002	DBLP DOI BibTeX RDF
30	Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai	An Automatic Router for the Pin Grid Array Package.	ASP-DAC	1999	DBLP DOI BibTeX RDF
30	Robert H. Caverly, N. Quinn	A SPICE model for simulating the impedance-frequency characteristics of high frequency PIN switching diodes.	ISCAS (6)	1999	DBLP DOI BibTeX RDF