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Searching for phrase pre-charge (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1999-2006 (18) 2007-2012 (16) 2013-2018 (17) 2019-2024 (14)
Publication types (Num. hits)
article(20) inproceedings(45)
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Found 65 publication records. Showing 65 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
95Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults
65Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone Charge Sharing Fault Detection for CMOS Domino Logic Circuits. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit
65Thomas Popp, Stefan Mangard Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Hardware Countermeasures, MDPL, Masking Logic, Dual-Rail Pre-Charge Logic, DPA, Side-Channel Analysis
58Zhimin Chen, Yujie Zhou Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
49Ching-Hwa Cheng Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
48Toru Akishita, Masanobu Katagi, Yoshikazu Miyato, Asami Mizuno, Kyoji Shibutani A Practical DPA Countermeasure with BDD Architecture. Search on Bibsonomy CARDIS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF dual-rail pre-charge logic, DPA, Binary Decision Diagram, countermeasure
48Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF pre-charge, sense amplifier, 6T-cell, 8T-cell, low power, CAM
46Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard 0001 Minimizing test power in SRAM through reduction of pre-charge activity. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti Three-Phase Dual-Rail Pre-charge Logic. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF dual-rail logic, SABL, security, DPA
29Benedikt Gierlichs DPA-Resistance Without Routing Constraints? Search on Bibsonomy CHES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Differential Side Channel Analysis, DSCA, Masked Dual-rail Pre-charge Logic, MDPL, Gate-level masking, DRP
26H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler A rail to rail, slew-boosted pre-charge buffer. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Daisuke Suzuki, Minoru Saeki Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Naeem Maroof, Bai-Sun Kong Charge sharing write driver and half- V DD pre-charge 8T SRAM with virtual ground for low-power write and read operation. Search on Bibsonomy IET Circuits Devices Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
26Youngil Kim, Sangsun Lee Soft pre-charge H/V switch for charge pump with NAND flash memory using external power. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
23Nitin Kumar, Manoj Kumar 0005 Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz-6.1 GHz Applications in 0.18 μm CMOS. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
23Igor Arsovski, Akhilesh Patil, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler 1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
23Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. Search on Bibsonomy DDECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt A low-power CAM using a 12-transistor design cell. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
20Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung Leakage Reduction techniques in a 0.13um SRAM Cell. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20Jung-Lin Yang, Erik Brunvand Using dynamic domino circuits in self-timed systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF asynchronous circuits, domino logic, self-timed circuits
16Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
16Tae-Bin Kim, Hyun-Jin Kim, Kee-Won Kwon Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
16Weijie Jiang, Pouya Houshmand, Marian Verhelst, Wim Dehaene A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W. Search on Bibsonomy ESSCIRC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
16Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. Search on Bibsonomy VLSI Technology and Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
16Hao Tian 0004, Mingzhe Wu, Yun Wei Li 0001 Capacitor Pre-Charge Method for Back-to-Back Seven-Level Hybrid Clamped Converter Without Extra Power Supply. Search on Bibsonomy IEEE Trans. Ind. Electron. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
16Sivaneswaran Sankar, Po-Hung Chen, Maryam Shojaei Baghini An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
16Tzu-Hsien Yang, Yong-Hwa Wen, Chun-Kai Chiu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai A Pre-Charge Tracking Technique in the 40 MHz High-Speed Switching 48-to-5 V GaN-Based DC-DC Buck Converter for Reducing Large Self-Commutation Loss and Achieving a High Efficiency of 95.4%. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
16Junji Sone, Tatsuya Sato, Shinmyo Yanagawa, Katsumi Yamada, Liwei Lin Study of Thin Polymer pre-charge Multi point Tactile device. Search on Bibsonomy VR Workshops The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
16Chuang Wang 0004, Yan Lu 0002, Rui Paulo Martins A Highly Integrated 3-Phase 4: 1 Resonant Switched-Capacitor Converter With Parasitic Loss Reduction and Fast Pre-Charge Startup. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
16Tzu-Hsien Yang, Chun-Kai Chiu, Yong-Hwa Wen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai A Pre-Charge Tracking Technique in the 40MHz High-switching 48-to-5V DC-DC Buck Converter with GaN Switches for Reducing Large Self-commutation Loss and Achieving a High Efficiency of 95.4%. Search on Bibsonomy ESSCIRC The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
16Partha De, Udaya Parampalli, Chittaranjan Mandal 0002 Secure Path Balanced BDD-Based Pre-Charge Logic for Masking. Search on Bibsonomy IEEE Trans. Circuits Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
16Jooyoon Kim, Jongsun Park 0001 Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit. Search on Bibsonomy ISOCC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
16Jiahao Yin, Chunmeng Dou, Danian Dong, Jie Yu 0027, Xiaoxin Xu, Qing Luo, Tiancheng Gong, Lu Tai, Peng Yuan, Xiaoyong Xue, Ming Liu 0022, Hangbing Lv A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
16Graeme Horsman, Angela King Policing and Crime Act 2017: Changes to pre-charge bail and the impact on digital forensic analysis. Search on Bibsonomy Comput. Law Secur. Rev. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
16Craig LaBoda, Chris Dwyer, Alvin R. Lebeck Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic. Search on Bibsonomy IEEE Micro The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan Formal modeling and verification for pre-charge half buffer gates and circuits. Search on Bibsonomy MWSCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Maoxin Ren, Lang Huang 0002, Xiliang Chen, Xu Yang 0012 Pre-charge strategy of modular multilevel converters with DC fault blocking capability based on multi-capacitor submodules. Search on Bibsonomy IECON The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Dongye Li, Yichao Sun, Jianfeng Zhao 0001, Zhendong Ji Fast pre-charge strategy of a modified MMC with enhanced DC fault ride-through capability. Search on Bibsonomy ISIE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks. Search on Bibsonomy VLSID The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Yongan Zheng, Lili Zhou, Fan Tian, Mingxiao He, Huailin Liao A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period pre-charge compensation scheme for ultra-low power systems. Search on Bibsonomy ISCAS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
16Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics. Search on Bibsonomy A-SSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
16Sahar Sarafi, Abu Khari bin A'Ain, Javad Abbaszadeh, Amin Chegini Pre-charge solution for low-power, area-efficient SAR ADC. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
16Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. Search on Bibsonomy HOST The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
16Partha De, Kunal Banerjee 0001, Chittaranjan A. Mandal, Debdeep Mukhopadhyay Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic. Search on Bibsonomy DSD The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
16Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti Security Evaluation and Optimization of the Delay-based Dual-rail Pre-charge Logic in Presence of Early Evaluation of Data. Search on Bibsonomy SECRYPT The full citation details ... 2013 DBLP  BibTeX  RDF
16Gong Chen 0002, Bo Yang 0004, Yu Zhang, Qing Dong 0002, Shigetoshi Nakatake A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
16Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family. Search on Bibsonomy MIXDES The full citation details ... 2013 DBLP  BibTeX  RDF
16Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
16Vikram B. Suresh, Wayne P. Burleson Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration. Search on Bibsonomy ISQED The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
16Zhimin Chen 0002, Patrick Schaumont Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2010 DBLP  BibTeX  RDF
16Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti Delay-based dual-rail pre-charge logic. Search on Bibsonomy ICECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
16Daisuke Suzuki, Minoru Saeki An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
16Retdian Agung Nicodimus, Shigetaka Takagi, Nobuo Fujii Reduction of Bootstrapped Switch Area Consumption Using Pre-Charge Phase. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
16Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. Search on Bibsonomy ETS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija Conditional pre-charge techniques for power-efficient dual-edge clocking. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution
10Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin A Design-for-Diagnosis Technique for SRAM Write Drivers. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
10Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF write driver, design-for-diagnosis, diagnosis, SRAM
10Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
10Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
10Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani Power Analysis Attacks on MDPL and DRSL Implementations. Search on Bibsonomy ICISC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF DRSL, MDPL, Side-Channel Attacks, DPA, flip-flop
10Jung-Lin Yang, Erik Brunvand Self-Timed Design with Dynamic Domino Circuits. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang A new robust handshake for asymmetric asynchronous micro-pipelines. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu A Robust Handshake for Asynchronous System. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
10Victor Varshavsky, Vyacheslav Marakhovsky A Neuron-MOS Threshold Element with Switching Capacitors. Search on Bibsonomy Fuzzy Days The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
10Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. Search on Bibsonomy MTDT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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