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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 65 publication records. Showing 65 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
95 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 435-444, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults |
65 | Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone |
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 77-85, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit |
65 | Thomas Popp, Stefan Mangard |
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 172-186, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Hardware Countermeasures, MDPL, Masking Logic, Dual-Rail Pre-Charge Logic, DPA, Side-Channel Analysis |
58 | Zhimin Chen, Yujie Zhou |
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 242-254, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA |
49 | Ching-Hwa Cheng |
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 147-158, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
48 | Toru Akishita, Masanobu Katagi, Yoshikazu Miyato, Asami Mizuno, Kyoji Shibutani |
A Practical DPA Countermeasure with BDD Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CARDIS ![In: Smart Card Research and Advanced Applications, 8th IFIP WG 8.8/11.2 International Conference, CARDIS 2008, London, UK, September 8-11, 2008. Proceedings, pp. 206-217, 2008, Springer, 978-3-540-85892-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dual-rail pre-charge logic, DPA, Binary Decision Diagram, countermeasure |
48 | Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt |
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 75-85, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
pre-charge, sense amplifier, 6T-cell, 8T-cell, low power, CAM |
46 | Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard 0001 |
Minimizing test power in SRAM through reduction of pre-charge activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1159-1164, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti |
Three-Phase Dual-Rail Pre-charge Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 232-241, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dual-rail logic, SABL, security, DPA |
29 | Benedikt Gierlichs |
DPA-Resistance Without Routing Constraints? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 107-120, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Differential Side Channel Analysis, DSCA, Masked Dual-rail Pre-charge Logic, MDPL, Gate-level masking, DRP |
26 | H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler |
A rail to rail, slew-boosted pre-charge buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Daisuke Suzuki, Minoru Saeki |
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 255-269, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Naeem Maroof, Bai-Sun Kong |
Charge sharing write driver and half- V DD pre-charge 8T SRAM with virtual ground for low-power write and read operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 12(1), pp. 94-98, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Youngil Kim, Sangsun Lee |
Soft pre-charge H/V switch for charge pump with NAND flash memory using external power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 10(17), pp. 20130497, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Nitin Kumar, Manoj Kumar 0005 |
Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz-6.1 GHz Applications in 0.18 μm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(11), pp. 1950182:1-1950182:14, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Igor Arsovski, Akhilesh Patil, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler |
1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(1), pp. 155-163, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, pp. 256-261, 2006, IEEE Computer Society, 1-4244-0185-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt |
A low-power CAM using a 12-transistor design cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 264-269, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung |
Leakage Reduction techniques in a 0.13um SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 215-221, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Jung-Lin Yang, Erik Brunvand |
Using dynamic domino circuits in self-timed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 253-256, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
asynchronous circuits, domino logic, self-timed circuits |
16 | Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang |
A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(4), pp. 1225-1234, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Tae-Bin Kim, Hyun-Jin Kim, Kee-Won Kwon |
Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(4), pp. 1326-1330, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Weijie Jiang, Pouya Houshmand, Marian Verhelst, Wim Dehaene |
A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 409-412, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang |
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hao Tian 0004, Mingzhe Wu, Yun Wei Li 0001 |
Capacitor Pre-Charge Method for Back-to-Back Seven-Level Hybrid Clamped Converter Without Extra Power Supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 69(12), pp. 12326-12335, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Sivaneswaran Sankar, Po-Hung Chen, Maryam Shojaei Baghini |
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(8), pp. 2404-2417, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Tzu-Hsien Yang, Yong-Hwa Wen, Chun-Kai Chiu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai |
A Pre-Charge Tracking Technique in the 40 MHz High-Speed Switching 48-to-5 V GaN-Based DC-DC Buck Converter for Reducing Large Self-Commutation Loss and Achieving a High Efficiency of 95.4%. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(7), pp. 2045-2053, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Junji Sone, Tatsuya Sato, Shinmyo Yanagawa, Katsumi Yamada, Liwei Lin |
Study of Thin Polymer pre-charge Multi point Tactile device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VR Workshops ![In: 2022 IEEE Conference on Virtual Reality and 3D User Interfaces Abstracts and Workshops, VR Workshops, Christchurch, New Zealand, March 12-16, 2022, pp. 316-318, 2022, IEEE, 978-1-6654-8402-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Chuang Wang 0004, Yan Lu 0002, Rui Paulo Martins |
A Highly Integrated 3-Phase 4: 1 Resonant Switched-Capacitor Converter With Parasitic Loss Reduction and Fast Pre-Charge Startup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(7), pp. 2608-2612, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Tzu-Hsien Yang, Chun-Kai Chiu, Yong-Hwa Wen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai |
A Pre-Charge Tracking Technique in the 40MHz High-switching 48-to-5V DC-DC Buck Converter with GaN Switches for Reducing Large Self-commutation Loss and Achieving a High Efficiency of 95.4%. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 47th ESSCIRC 2021 - European Solid State Circuits Conference, ESSCIR 2021, Grenoble, France, September 13-22, 2021, pp. 311-314, 2021, IEEE, 978-1-6654-3751-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Partha De, Udaya Parampalli, Chittaranjan Mandal 0002 |
Secure Path Balanced BDD-Based Pre-Charge Logic for Masking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. ![In: IEEE Trans. Circuits Syst. 67-I(12), pp. 4747-4760, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Jooyoon Kim, Jongsun Park 0001 |
Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2020, Yeosu, South Korea, October 21-24, 2020, pp. 147-148, 2020, IEEE, 978-1-7281-8331-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Jiahao Yin, Chunmeng Dou, Danian Dong, Jie Yu 0027, Xiaoxin Xu, Qing Luo, Tiancheng Gong, Lu Tai, Peng Yuan, Xiaoyong Xue, Ming Liu 0022, Hangbing Lv |
A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 16(12), pp. 20190201, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Graeme Horsman, Angela King |
Policing and Crime Act 2017: Changes to pre-charge bail and the impact on digital forensic analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Law Secur. Rev. ![In: Comput. Law Secur. Rev. 34(5), pp. 1139-1143, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Craig LaBoda, Chris Dwyer, Alvin R. Lebeck |
Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 37(4), pp. 52-62, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan |
Formal modeling and verification for pre-charge half buffer gates and circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, pp. 519-522, 2017, IEEE, 978-1-5090-6389-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Maoxin Ren, Lang Huang 0002, Xiliang Chen, Xu Yang 0012 |
Pre-charge strategy of modular multilevel converters with DC fault blocking capability based on multi-capacitor submodules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29 - November 1, 2017, pp. 4544-4550, 2017, IEEE, 978-1-5386-1127-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Dongye Li, Yichao Sun, Jianfeng Zhao 0001, Zhendong Ji |
Fast pre-charge strategy of a modified MMC with enhanced DC fault ride-through capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIE ![In: 26th IEEE International Symposium on Industrial Electronics, ISIE 2017, Edinburgh, United Kingdom, June 19-21, 2017, pp. 717-722, 2017, IEEE, 978-1-5090-1412-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran |
NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, January 7-11, 2017, pp. 167-172, 2017, IEEE Computer Society, 978-1-5090-5740-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Yongan Zheng, Lili Zhou, Fan Tian, Mingxiao He, Huailin Liao |
A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period pre-charge compensation scheme for ultra-low power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 830-833, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Chuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan |
Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016, pp. 177-180, 2016, IEEE, 978-1-5090-3699-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Sahar Sarafi, Abu Khari bin A'Ain, Javad Abbaszadeh, Amin Chegini |
Pre-charge solution for low-power, area-efficient SAR ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 12(20), pp. 20150546, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai |
A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2015, Washington, DC, USA, 5-7 May, 2015, pp. 112-117, 2015, IEEE Computer Society, 978-1-4673-7420-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Partha De, Kunal Banerjee 0001, Chittaranjan A. Mandal, Debdeep Mukhopadhyay |
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 641-644, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti |
Security Evaluation and Optimization of the Delay-based Dual-rail Pre-charge Logic in Presence of Early Evaluation of Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SECRYPT ![In: SECRYPT 2013 - Proceedings of the 10th International Conference on Security and Cryptography, Reykjavík, Iceland, 29-31 July, 2013, pp. 183-194, 2013, SciTePress, 978-989-8565-73-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
16 | Gong Chen 0002, Bo Yang 0004, Yu Zhang, Qing Dong 0002, Shigetoshi Nakatake |
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013, pp. 315-316, 2013, ACM, 978-1-4503-2032-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti |
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, Gdynia, Poland, June 20-22, 2013, pp. 163-168, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
16 | Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti |
A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(11), pp. 2128-2132, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Vikram B. Suresh, Wayne P. Burleson |
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 298-305, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Zhimin Chen 0002, Patrick Schaumont |
Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2010, pp. 272, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti |
Delay-based dual-rail pre-charge logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, pp. 53-56, 2009, IEEE, 978-1-4244-5090-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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16 | Daisuke Suzuki, Minoru Saeki |
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(1), pp. 184-192, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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16 | Retdian Agung Nicodimus, Shigetaka Takagi, Nobuo Fujii |
Reduction of Bootstrapped Switch Area Consumption Using Pre-Charge Phase. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2), pp. 476-482, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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16 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 10th European Test Symposium, ETS 2005, Tallinn, Estonia, May 22-25, 2005, pp. 116-121, 2005, IEEE Computer Society, 0-7695-2341-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija |
Conditional pre-charge techniques for power-efficient dual-edge clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 56-59, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution |
10 | Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin |
A Design-for-Diagnosis Technique for SRAM Write Drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1480-1485, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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10 | Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin |
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 89-94, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
write driver, design-for-diagnosis, diagnosis, SRAM |
10 | Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur |
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 560-565, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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10 | Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis |
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 94-98, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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10 | Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani |
Power Analysis Attacks on MDPL and DRSL Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2007, 10th International Conference, Seoul, Korea, November 29-30, 2007, Proceedings, pp. 259-272, 2007, Springer, 978-3-540-76787-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DRSL, MDPL, Side-Channel Attacks, DPA, flip-flop |
10 | Jung-Lin Yang, Erik Brunvand |
Self-Timed Design with Dynamic Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 217-219, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang |
A new robust handshake for asymmetric asynchronous micro-pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 209-212, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu |
A Robust Handshake for Asynchronous System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 16-19, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
10 | Victor Varshavsky, Vyacheslav Marakhovsky |
A Neuron-MOS Threshold Element with Switching Capacitors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fuzzy Days ![In: Computational Intelligence, Theory and Applications, International Conference, 7th Fuzzy Days, Dortmund, Germany, October 1-3, 2001, Proceedings, pp. 430-435, 2001, Springer, 3-540-42732-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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10 | Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo |
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, pp. 119-124, 2000, IEEE Computer Society, 0-7695-0689-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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