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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
118 | Jinpyo Park, Je-Hyung Lee, Soo-Mook Moon |
Register Allocation for Banked Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 39-47, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
banked register file, register allocation |
109 | Marc Tremblay, Bill Joy 0001, Ken Shin |
A three dimensional register file for superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 191-201, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows |
108 | Yoonseo Choi, Hwansoo Han |
Optimal register reassignment for register stack overflow minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(1), pp. 90-114, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
register stack, sequence graph, register allocation, Register assignment |
102 | Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero |
Speculative early register release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 291-302, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
physical register release, optimization, register file, register renaming |
92 | André Seznec, Eric Toullec, Olivier Rochecouste |
Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 383-394, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
89 | Minwook Ahn, Yunheung Paek |
Register coalescing techniques for heterogeneous register architecture with copy sifting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(2), pp. 16:1-16:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous register architecture, compiler, Register allocation, embedded processors, register coalescing |
83 | Nan Wu 0003, Mei Wen, Ju Ren 0002, Yi He 0008, Chunyuan Zhang |
Register Allocation on Stream Processor with Local Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 545-551, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
local register file, spilling, register allocation, VLIW, stream processor |
82 | G. X. Tyson, M. Smelyanskyi, Edward S. Davidson |
Evaluating the Use of Register Queues in Software Pipelined Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(8), pp. 769-783, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW |
82 | Liu Yang, Sun Chan, Guang R. Gao, Roy Ju, Guei-Yuan Lueh, Zhaoqing Zhang |
Inter-procedural stacked register allocation for itanium® like architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 215-225, 2003, ACM, 1-58113-733-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
hot region, inter-procedural stacked register allocation, quota assignment, register allocation, hotspot |
81 | Robert Yung, Neil C. Wilhelm |
Caching processor general registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 307-312, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file |
80 | Rama Sangireddy |
Register Organization for Enhanced On-Chip Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 180-190, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
77 | Minwook Ahn, Jooyeon Lee, Yunheung Paek |
Optimistic coalescing for heterogeneous register architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 93-102, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
heterogeneous register architecture, register coalesing, compiler, register allocation, embedded processors |
76 | Guei-Yuan Lueh, Thomas R. Gross, Ali-Reza Adl-Tabatabai |
Fusion-based register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 22(3), pp. 431-470, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
performance evaluation, register allocation |
75 | Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001 |
Early Register Release for Out-of-Order Processors with RegisterWindows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 225-234, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
75 | Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi |
Physical Register Inlining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 325-337, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
72 | Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev |
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 304-315, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
72 | Jun Yan 0008, Wei Zhang 0002 |
Compiler-guided register reliability improvement against soft errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 203-209, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
register lifetime, reliability, soft errors, register file |
72 | José-Lorenzo Cruz, Antonio González 0001, Mateo Valero, Nigel P. Topham |
Multiple-banked register file architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 316-325, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bypass logic, register file architecture, register file cache, dynamically-scheduled processor |
70 | Masaaki Kondo, Hiroshi Nakamura |
A Small, Fast and Low-Power Register File by Bit-Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 40-49, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
68 | Oguz Ergin, Deniz Balkan, Dmitry Ponomarev 0001, Kanad Ghose |
Early Register Deallocation Mechanisms Using Checkpointed Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1153-1166, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
register file optimization, Superscalar processors, precise interrupts |
68 | Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung |
Register renaming for x86 superscalar design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 336-343, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming |
67 | Liem Tran, Nicholas Nelson 0001, Fung Ngai, Steve Dropsho, Michael C. Huang 0001 |
Dynamically reducing pressure on the physical register file through simple register sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 78-87, 2004, IEEE Computer Society, 0-7803-8385-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
67 | Ivan D. Baev, Richard E. Hank, David H. Gross |
Prematerialization: reducing register pressure for free. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 285-294, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
rematerialization, register allocation, VLIW, Itanium, register pressure |
67 | Sid Ahmed Ali Touati |
Register Saturation in Instruction Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(4), pp. 393-449, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure |
67 | Xiaotong Zhuang, Santosh Pande |
Differential register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, Chicago, IL, USA, June 12-15, 2005, pp. 168-179, 2005, ACM, 1-59593-056-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
architected register, differential dncoding, register allocation |
67 | Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens |
Register Organization for Media Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 375-386, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
register organization, register architecture, processor architecture, media processors |
66 | Jason Cong, Yiping Fan, Junjuan Xu |
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 35:1-35:31, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
distributed register file, Behavioral synthesis, resource binding |
66 | Montserrat Ros, Peter Sutton |
A post-compilation register reassignment technique for improving hamming distance code compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 97-104, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
register reassignment, hamming distance, code compression |
66 | Christian Wimmer, Hanspeter Mössenböck |
Optimized interval splitting in a linear scan register allocator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 1st International Conference on Virtual Execution Environments, VEE 2005, Chicago, IL, USA, June 11-12, 2005, pp. 132-141, 2005, ACM, 1-59593-047-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
linear scan, java, optimization, compilers, graph-coloring, register allocation, just-in-time compilation |
66 | Michael D. Smith 0001, Norman Ramsey, Glenn H. Holloway |
A generalized algorithm for graph-coloring register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, Washington, DC, USA, June 9-11, 2004, pp. 277-288, 2004, ACM, 1-58113-807-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
graph coloring, register allocation |
65 | Xuan Guan, Yunsi Fei |
Reducing power consumption of embedded processors through register file partitioning and compiler support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 269-274, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
65 | Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose |
Increasing Processor Performance Through Early Register Release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 480-487, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
65 | Ulrich Hirnschrott, Andreas Krall, Bernhard Scholz |
Graph Coloring vs. Optimal Register Allocation for Optimizing Compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JMLC ![In: Modular Programming Languages, Joint Modular Languages Conference, JMLC 2003, Klagenfurt, Austria, August 25-27, 2003, Proceedings, pp. 202-213, 2003, Springer, 3-540-40796-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
65 | Xianglong Huang, Steve Carr 0001, Philip H. Sweany |
Loop Transformations for Architectures with Partitioned Register Banks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 48-55, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
64 | Nicola Zingirian, Massimo Maresca |
Selective Register Renaming: A Compiler-Driven Approach to Dynamic Register Renaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 9th International Conference, HPCN Europe 2001, Amsterdam, The Netherlands, June 25-27, 2001, Proceedings, pp. 344-352, 2001, Springer, 3-540-42293-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Dynamic Register Renaming, Instruction Level Parallelism, Register Allocation, Loop Parallelization |
62 | David W. Wall |
Register Windows versus Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'88 Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, June 22-24, 1988, pp. 67-78, 1988, ACM, 0-89791-269-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
62 | David W. Wall |
Register windows vs. register allocation (with retrospective) ![Search on Bibsonomy](Pics/bibsonomy.png) |
Best of PLDI ![In: 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, A Selection, pp. 270-282, 1988, ACM, 1-58113-623-4. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
62 | Jer-Yu Hsu, Yan-Zu Wu, Xuan-Yi Lin, Yeh-Ching Chung |
SCRF - A Hybrid Register File Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 9th International Conference, PaCT 2007, Pereslavl-Zalessky, Russia, September 3-7, 2007, Proceedings, pp. 525-536, 2007, Springer, 978-3-540-73939-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cluster processor architecture, register architecture, register allocation algorithm, VLIW processor |
62 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 32(6), pp. 447-474, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
register requirements, register file organization, clustered organization, Modulo scheduling, spill code |
62 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 252-261, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis |
62 | Nicola Zingirian, Massimo Maresca |
Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 8th International Conference, HPCN Europe 2000, Amsterdam, The Netherlands, May 8-10, 2000, Proceedings, pp. 343-352, 2000, Springer, 3-540-67553-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Dynamic Register Renaming, Image Processing, Instruction Level Parallelism, Register Allocation, Loop Parallelization |
61 | Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen 0001 |
Post-pass periodic register allocation to minimise loop unrolling degree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 141-150, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded code optimisation, periodic register allocation, software pipelining, loop unrolling |
61 | Peter Koepke, Russell G. Miller |
An Enhanced Theory of Infinite Time Register Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CiE ![In: Logic and Theory of Algorithms, 4th Conference on Computability in Europe, CiE 2008, Athens, Greece, June 15-20, 2008, Proceedings, pp. 306-315, 2008, Springer, 978-3-540-69405-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ordinal computability, hypercomputation, infinitary computation, register machine |
61 | Jason Cong, Yiping Fan, Wei Jiang |
Platform-based resource binding using a distributed register-file microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 709-715, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
distributed register file, behavior synthesis, resource binding |
61 | Xiaotong Zhuang, Santosh Pande |
Balancing register allocation across threads for a multithreaded network processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, Washington, DC, USA, June 9-11, 2004, pp. 289-300, 2004, ACM, 1-58113-807-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
register allocation, network processor, multithreaded processor |
61 | Akira Koseki, Hideaki Komatsu, Toshio Nakatani |
Preference-Directed Graph Coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Berlin, Germany, June 17-19, 2002, pp. 33-44, 2002, ACM, 1-58113-463-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
irregular-register architectures, graph coloring, register allocation, register coalescing |
60 | V. Krishna Nandivada, Fernando Magno Quintão Pereira, Jens Palsberg |
A Framework for End-to-End Verification and Evaluation of Register Allocators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 14th International Symposium, SAS 2007, Kongens Lyngby, Denmark, August 22-24, 2007, Proceedings, pp. 153-169, 2007, Springer, 978-3-540-74060-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Raid Ayoub, Alex Orailoglu |
Power efficient register file update approach for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 431-437, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Rakesh Nalluri, Rohan Garg 0003, Preeti Ranjan Panda |
Customization of Register File Banking Architecture for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 239-244, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Rama Sangireddy |
Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 227-232, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Rama Sangireddy, Arun K. Somani |
Exploiting Quiescent States in Register Lifetime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 368-374, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Xiaotong Zhuang, Santosh Pande |
Resolving Register Bank Conflicts for a Network Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 269-278, 2003, IEEE Computer Society, 0-7695-2021-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
60 | Sriraman Tallam, Rajiv Gupta 0001 |
Bitwidth aware global register allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Conference Record of POPL 2003: The 30th SIGPLAN-SIGACT Symposium on Principles of Programming Languages, New Orleans, Louisisana, USA, January 15-17, 2003, pp. 85-96, 2003, ACM, 1-58113-628-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
minimal bitwidth, packing interfering nodes, subword data, embedded applications |
60 | Sid Ahmed Ali Touati, Christine Eisenbeis |
Early Control of Register Pressure for Software Pipelined Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 12th International Conference, CC 2003, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003, Warsaw, Poland, April 7-11, 2003, Proceedings, pp. 17-32, 2003, Springer, 3-540-00904-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
58 | Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev |
Reducing register pressure in SMT processors through L2-miss-driven early register release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(3), pp. 13:1-13:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register file, Simultaneous multithreading |
58 | Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao |
Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(1), pp. 4-20, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures |
58 | Akira Koseki, Yoshiaki Fukazawa, Hideaki Komatsu |
A Register Allocation Technique Using Register Existence Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 404-411, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Instruction-Level Parallelism, Register Allocation, Program Dependence Graph, Code Scheduling |
58 | Guido Araujo, Sharad Malik |
Optimal code generation for embedded memory non-homogeneous register architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 36-41, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation |
57 | Jason Hiser, Steve Carr 0001, Philip H. Sweany, Steven J. Beaty |
Register Assignment for Software Pipelining with Partitioned Register Banks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 211-218, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
57 | Miquel Huguet, Tomás Lang |
Architectural Support for Reduced Register Saving / Restoring in Single-Window Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 9(1), pp. 66-97, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
57 | Suhyun Kim, Soo-Mook Moon |
Rotating register allocation with multiple rotating branches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 235-244, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
rotating register, register allocation, software pipelining |
57 | Byung-Sun Yang, Junpyo Lee, SeungIl Lee, Seongbae Park, Yoo C. Chung, Suhyun Kim, Kemal Ebcioglu, Erik R. Altman, Soo-Mook Moon |
Efficient Register Mapping and Allocation in LaTTe, an Open-Source Java Just-in-Time Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(1), pp. 57-69, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register mapping, copy coalescing, Java virtual machine, register allocation, just-in-time compilation |
57 | Hui Zeng, Kanad Ghose |
Register file caching for energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 244-249, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
register caching, energy-efficiency, register files |
56 | Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev 0001 |
Energy-efficient renaming with register versioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 171-176, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
microprocessor, register renaming |
56 | Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee |
Enabling compiler flow for embedded VLIW DSP processors with distributed register files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 146-148, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
distributed register files, embedded VLIW DSP compilers, software pipelining |
56 | Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown |
Increasing the number of effective registers in a low-power processor using a windowed register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 125-136, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
window assignment, low-power, graph partitioning, embedded processor, instruction encoding, register window |
56 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
MIRS: Modulo Scheduling with Integrated Register Spilling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 14th International Workshop, LCPC 2001, Cumberland Falls, KY, USA, August 1-3, 2001. Revised Papers, pp. 239-253, 2001, Springer, 3-540-04029-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code |
56 | Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen |
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(9), pp. 922-933, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
architecture, register file, simultaneous multithreading, Multithreaded architecture |
56 | Srinivas Katkoori, Ranga Vemuri, Jay Roy |
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 126-132, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Register Optimization, High Level Synthesis, Life-cycle Analysis |
56 | Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi |
A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 11th IEEE High Assurance Systems Engineering Symposium, HASE 2008, Nanjing, China, December 3 - 5, 2008, pp. 109-116, 2008, IEEE Computer Society, 978-0-7695-3482-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
56 | Shuai Wang 0006, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras |
Asymmetrically Banked Value-Aware Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 363-368, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally |
Register pointer architecture for efficient embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 600-605, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | Soontae Kim |
Reducing ALU and Register File Energy by Dynamic Zero Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the 26th IEEE International Performance Computing and Communications Conference, IPCCC 2007, April 11-13, 2007, New Orleans, Louisiana, USA, pp. 365-371, 2007, IEEE Computer Society, 1-4244-1138-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | Rahul Nagpal, Y. N. Srikant |
Register File Energy Optimization for Snooping Based Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil, pp. 161-168, 2007, IEEE Computer Society, 0-7695-3014-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Aneesh Aggarwal |
Address-Value Decoupling for Early Register Deallocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 2006 International Conference on Parallel Processing (ICPP 2006), 14-18 August 2006, Columbus, Ohio, USA, pp. 337-346, 2006, IEEE Computer Society, 0-7695-2636-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Sid Ahmed Ali Touati |
On the Optimality of Register Saturation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 33rd International Conference on Parallel Processing Workshops (ICPP 2004 Workshops), 15-18 August 2004, Montreal, Quebec, Canada, pp. 563-570, 2004, IEEE Computer Society, 0-7695-2198-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | Bengu Li, Youtao Zhang, Rajiv Gupta 0001 |
Speculative Subword Register Allocation in Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for High Performance Computing, 17th International Workshop, LCPC 2004, West Lafayette, IN, USA, September 22-24, 2004, Revised Selected Papers, pp. 56-71, 2004, Springer, 3-540-28009-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | J. Adam Butts, Gurindar S. Sohi |
Use-Based Register Caching with Decoupled Indexing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 302-313, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | Il Park 0001, Michael D. Powell, T. N. Vijaykumar |
Reducing register ports for higher speed and lower energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 171-182, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
56 | R. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen |
Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA, pp. 57-67, 2002, IEEE Computer Society, 0-7695-1534-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
56 | C. P. Ravikumar, R. Aggarwal, C. Sharma |
A Graph-Theoretic Approach for Register File Based Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 118-123, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
55 | Yunhe Shi, Kevin Casey, M. Anton Ertl, David Gregg |
Virtual machine showdown: Stack versus registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(4), pp. 2:1-2:36, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register architecture, stack architecture, virtual machine, Interpreter |
53 | Thomas Scholz, Michael Schäfers 0003 |
An improved dynamic register array concept for high-performance RISC processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 181-190, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing |
52 | Jie S. Hu, Shuai Wang 0006, Sotirios G. Ziavras |
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2006 International Conference on Dependable Systems and Networks (DSN 2006), 25-28 June 2006, Philadelphia, Pennsylvania, USA, Proceedings, pp. 281-290, 2006, IEEE Computer Society, 0-7695-2607-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Feng Zhou, Junchao Zhang, Chengyong Wu, Zhaoqing Zhang |
A Register Allocation Framework for Banked Register Files with Access Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 269-280, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Matthias Müller 0002, Andreas Wortmann 0002, Dominik Mader, Sven Simon 0001 |
Register Isolation for Synthesizable Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 228-237, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Fernando Magno Quintão Pereira, Jens Palsberg |
Register allocation by puzzle solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation, Tucson, AZ, USA, June 7-13, 2008, pp. 216-226, 2008, ACM, 978-1-59593-860-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
puzzle solving, register aliasing, register allocation |
52 | Florent Bouchez, Alain Darte, Fabrice Rastello |
Advanced conservative and optimistic register coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 147-156, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coloring number, greedy-k-colorable graph, register allocation, chordal graph, register coalescing |
52 | Sid Ahmed Ali Touati |
On the Periodic Register Need in Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(11), pp. 1493-1504, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining |
52 | Jian Wang 0046, Andreas Krall, M. Anton Ertl, Christine Eisenbeis |
Software pipelining with register allocation and spilling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 95-99, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, register allocation, software pipelining, loop scheduling, register spilling |
52 | Minwook Ahn, Yunheung Paek |
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers II, pp. 149-172, 2009, Springer, 978-3-642-00903-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous register architecture, register aliasing, compiler, code generation, register allocation, register coalescing |
51 | Christian Wimmer, Michael Franz |
Linear scan register allocation on SSA form. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 170-179, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SSA form deconstruction, lifetime analysis, linear scan, Java, register allocation, just-in-time compilation, SSA form |
51 | Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei |
Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 151-160, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
register allocation, placement and routing, coarse-grained, reconfigurable arrays |
51 | Weifeng Xu, Russell Tessier |
Tetris: a new register pressure control technique for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 113-122, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register pressure control, very long instruction word (VLIW) processor, instruction level parallelism |
51 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie |
Bypass aware instruction scheduling for register file power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario, Canada, June 14-16, 2006, pp. 173-181, 2006, ACM, 1-59593-362-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, processor bypasses, reservation table, power consumption, register file |
51 | Wann-Yun Shieh, Hsin-Dar Chen |
Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC Workshops ![In: Emerging Directions in Embedded and Ubiquitous Computing, EUC 2006 Workshops: NCUS, SecUbiq, USN, TRUST, ESO, and MSA, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 765-774, 2006, Springer, 3-540-36850-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer |
51 | Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown |
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 998-1012, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
optimization, Code generation, low-power design, graph partitioning, embedded processor, retargetable compilers, spill code, instruction encoding, register window |
51 | Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy |
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(1), pp. 189-216, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
lifecycle analysis, register optimization, high-level synthesis, hardware description languages, Behavioral synthesis, hierarchical specifications |
51 | Bernhard Scholz, Erik Eckstein |
Register allocation for irregular architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 139-148, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
boolean quadratic problem, register allocation |
51 | Jun Yan 0008, Wei Zhang 0002 |
Exploiting virtual registers to reduce pressure on real registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(4), pp. 3:1-3:18, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
short-lived variables, virtual register, register allocation, Register file, data forwarding |
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