Search results for "serializer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
115	Hyun-Joo Kim, Jung-Guk Kim, Chun-Hyon Chang, Sunyoung Han, Shin Hue	An Efficient Task Serializer for Hard Real-Time TMO Systems.	ISORC	2008	DBLP DOI BibTeX RDF	Task Serializer, TMO, Hard Real-time Systems
66	Krzysztof Iniewski, Marek Syrzycki	Low Power 2.5 Gb/s Serializer for SOC Applications.	ISVLSI	2004	DBLP DOI BibTeX RDF
57	Russell R. Atkinson, Carl Hewitt	Parallelism and Synchronization in Actor Systems.	POPL	1977	DBLP DOI BibTeX RDF
50	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
47	Hari Vijay Venkatanarayanan, Michael L. Bushnell	A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
47	Mattia Monga, Angelo Scotto	A generic serializer for mobile devices.	SAC	2005	DBLP DOI BibTeX RDF	mobile devices, NET, serialization
47	Magnus Eckersand, Fredrik Franzon, Ken Filliter	Using At-Speed BIST to Test LVDS Serializer/Deserializer Function.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	LVDS, BIST, differential, At-speed
38	Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces.	ASP-DAC	2007	DBLP DOI BibTeX RDF	Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron
38	Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu	A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
38	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny	Fast Asynchronous Shift Register for Bit-Serial Communication.	ASYNC	2006	DBLP DOI BibTeX RDF
31	Matthew D. Allen, Srinath Sridharan, Gurindar S. Sohi	Serialization sets: a dynamic dependence-based parallel execution model.	PPoPP	2009	DBLP DOI BibTeX RDF	serialization sets, parallel computing, runtime system, serializer
28	Mithilesh Kumar 0008, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya	A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link.	Integr.	2022	DBLP DOI BibTeX RDF
28	Yuki Hironaka, Taiki Yamae, Christopher L. Ayala, Nobuyuki Yoshikawa, Naoki Takeuchi	Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer.	IEEE Access	2022	DBLP DOI BibTeX RDF
28	Yunqi Yang, Ming Zhong, Qianli Ma, Ziyi Lin, Leliang Li, Guike Li, Liyuan Liu, Jian Liu 0021, Nanjian Wu, Haikun Jia, Xinghui Liu, Nan Qi	A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O.	ICTA	2022	DBLP DOI BibTeX RDF
28	Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande, Mahendra Sakare	Design of a PRBS generator and a serializer using active inductor employed CML latch.	MWSCAS	2021	DBLP DOI BibTeX RDF
28	Ming Zhong, Qingwen Wang, Yong Chen 0005, Jian Liu 0021, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, Nan Qi	A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects.	ICTA	2021	DBLP DOI BibTeX RDF
28	Mingyang You, Minjia Chen, Yihong Li, Guike Li, Jian Liu 0021, Yong Chen 0005, Yingtao Li, Nan Qi	A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects.	ICTA	2021	DBLP DOI BibTeX RDF
28	Utkarsh Upadhyaya, Souradip Sen, Sandeep Goyal, Shalabh Gupta	A 16 Gbps 10: 1 Serializer with Active Inductor Based CTLE for High Frequency Boosting.	ICECS	2020	DBLP DOI BibTeX RDF
28	Woosong Jung, Jinhyung Lee, Kwangho Lee, Hyojun Kim, Deog-Kyoon Jeong	A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface.	ISOCC	2020	DBLP DOI BibTeX RDF
28	Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya	Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
28	Yong-Un Jeong, Joo-Hyung Chae, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim	A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.	ISLPED	2019	DBLP DOI BibTeX RDF
28	Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim	A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
28	Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya	A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application.	iNIS	2017	DBLP DOI BibTeX RDF
28	Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim	A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface.	A-SSCC	2017	DBLP DOI BibTeX RDF
28	Ryan Clarke, Mitchell R. LeRoy, Srikumar Raman, Tuhin Guha Neogi, Russell P. Kraft, John F. McDonald 0001	140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
28	Giovanni Rovere, Chiara Bartolozzi, Nabil Imam, Rajit Manohar	Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications.	ISCAS	2015	DBLP DOI BibTeX RDF
28	Chang-Chun Zhang, Long Miao, Kui-ying Yin, Yu-feng Guo, Lei-Lei Liu	Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links.	IEICE Trans. Electron.	2014	DBLP DOI BibTeX RDF
28	Martin Dias, Mariano Martinez Peck, Stéphane Ducasse, Gabriela Arévalo	Fuel: a fast general purpose object graph serializer.	Softw. Pract. Exp.	2014	DBLP DOI BibTeX RDF
28	Oliver Schrape, Markus Appel, Frank Winkler 0001, Milos Krstic	A 12 Gb/s standard cell based ECL 4: 1 serializer with asynchronous parallel interface.	ICECS	2013	DBLP DOI BibTeX RDF
28	Kejun Wu, Peng Liu 0016, Qiaoyan Yu	A novel energy-efficient serializer design method for gigascale systems.	ISCAS	2013	DBLP DOI BibTeX RDF
28	Kang-Yeob Park, Woo-Young Choi, Seon-Young Lee, Wonseok Oh 0003	A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme.	ISCAS	2012	DBLP DOI BibTeX RDF
28	Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao	A novel low gate-count serializer topology with Multiplexer-Flip-Flops.	ISCAS	2012	DBLP DOI BibTeX RDF
28	David C. Keezer, Te-Hui Chen, Carl Edward Gray, Hyun Woo Choi, Sungyeol Kim, Seongkwan Lee, Hosun Yoo	Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter.	ITC	2012	DBLP DOI BibTeX RDF
28	Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
28	Maher Assaad, Mohammed H. Alser	An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
28	Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu	Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips.	VTS	2011	DBLP DOI BibTeX RDF
28	Jae-Hyuck Woo, Jae-Goo Lee, Young-Hyun Jun, Bai-Sun Kong	Low-Power High-Speed Data Serializer for Mobile TFT-LCD Driver ICs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
28	Chih-Hsing Lin, Yung-Chang Chang, Wen-Chih Huang, Wei-Chih Lai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Chun-Ming Huang, Chih-Chyau Yang, Shih-Lun Chen	A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification.	ISCAS	2010	DBLP DOI BibTeX RDF
28	Sachin P. Chodnekar, Devendra Sutar, Gajanan S. Gawde	Design of 32: 1 bit serializer working at 10GBPS.	ICWET	2010	DBLP DOI BibTeX RDF
28	Eung-Ju Kim, Kwan-Jae Lee, Sukki Kim	A high resolution Serializer and Deserializer architecture for mobile image sensor module.	CCECE	2010	DBLP DOI BibTeX RDF
28	Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker	A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
28	Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker	A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
28	Magnus Eckersand, Fredrik Franzon, Ken Filliter	Using at-speed BIST to test LVDS serializer/deserializer function.	ETW	2001	DBLP DOI BibTeX RDF
19	Heiner Litz, Holger Fröning, Ulrich Brüning 0001	A HyperTransport 3 Physical Layer Interface for FPGAs.	ARC	2009	DBLP DOI BibTeX RDF
19	Wesley Tansey, Eli Tilevich	Efficient automated marshaling of C++ data structures for MPI applications.	IPDPS	2008	DBLP DOI BibTeX RDF
19	Jae Y. Kim, Chih-Wei Yao, Alan N. Willson Jr.	A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Sounil Biswas, R. D. (Shawn) Blanton	Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.	VTS	2008	DBLP DOI BibTeX RDF	pass-fail test data, boolean minimization, minimum constrained subset cover, Mixed-signal test, test compaction
19	Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo	A practical approach of memory access parallelization to exploit multiple off-chip DDR memories.	DAC	2008	DBLP DOI BibTeX RDF	parallelization, memory, arbitration
19	Fei Yuan, Minghai Li	A new area-efficient 4-PAM 10 Gb/s CMOS serial link transmitter.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Tharaka Devadithya, Kenneth Chiu	Poster reception - Fast binary serialization for grid systems with XBS.	SC	2006	DBLP DOI BibTeX RDF
19	Yongjian Tang, Lenian He, Xiaolang Yan	A novel data processing circuit in high-speed serial communication.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Ming-Ta Hsieh, Gerald E. Sobelman	Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
19	Herwin Chan, Alireza Hodjat, Jun Shi 0001, Richard D. Wesel, Ingrid Verbauwhede	Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network.	ITCC (2)	2004	DBLP DOI BibTeX RDF
19	Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha	Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	communication devices test, high frequency test, jitter test, timing jitter
19	Graham Hetherington, Richard Simpson	Circular BIST testing the digital logic within a high speed Serdes.	ITC	2003	DBLP DOI BibTeX RDF
19	Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha	Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
19	Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha	Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division.	VTS	2002	DBLP DOI BibTeX RDF