Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
109 | Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang |
Visibility enhancement for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 13-18, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
silicon validation, functional verification, silicon debug |
103 | Ehab Anis, Nicola Nicolici |
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 225-230, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
84 | Kwang-Ting (Tim) Cheng |
Effective silicon debug is key for time to money. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(3), pp. 204, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
81 | Ho Fai Ko, Nicola Nicolici |
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2), pp. 285-297, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
80 | Joon-Sung Yang, Nur A. Touba |
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 345-351, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR |
78 | Hari Balachandran, Kenneth M. Butler, Neil Simpson |
Facilitating Rapid First Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 628-637, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
77 | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu |
A General Failure Candidate Ranking Framework for Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 352-358, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Silicon Debug |
77 | Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel |
Automatic generation of breakpoint hardware for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 514-517, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hardware-breakpoints, design-flow, silicon-debug, design-for-debug |
64 | Jagannath Keshava, Nagib Hakim, Chinna Prudvi |
Post-silicon validation challenges: how EDA and academia can help. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 3-7, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
design, verification, test, validation, emulation |
63 | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu |
Diagnosing Silicon Failures Based on Functional Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA, pp. 94-98, 2006, IEEE Computer Society, 978-0-7695-2839-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault diagnosis, Silicon debug, design for debug |
63 | Sandeep Kumar Goel, Bart Vermeulen |
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 407-416, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains |
63 | Doug Josephson |
The good, the bad, and the ugly of silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 3-6, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
design for test and debug, debug, validation, characterization |
63 | Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel |
Core-Based Scan Architecture for Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 638-647, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
61 | Rob Aitken, Erik Jan Marinissen |
Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(3), pp. 206-207, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
61 | Bart Vermeulen |
Functional Debug Techniques for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(3), pp. 208-215, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
58 | Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger |
Silicon Symptoms to Solutions: Applying Design for Debug Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 664-672, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic |
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 613-620, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
57 | Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk |
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 7:1-7:25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Field programmable gate array, system-on-chip, integrated circuit, silicon debug |
57 | Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham |
On-chip delay measurement for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 145-148, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
design for testability, delay fault testing, silicon debug |
55 | Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang 0006 |
BackSpace: Formal Analysis for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, FMCAD 2008, Portland, Oregon, USA, 17-20 November 2008, pp. 1-10, 2008, IEEE, 978-1-4244-2735-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 55-62, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
53 | Miron Abramovici |
In-System Silicon Validation and Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(3), pp. 216-223, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
50 | Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak |
On Silicon-Based Speed Path Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 35-41, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Young-Jun Kwon, Ben Mathew, Hong Hao |
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 727-732, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
46 | Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green |
Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(3), pp. 232-239, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP |
46 | |
Panel Summaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 598-599, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IEEE European Test Symposium, IEEE Infrastructure IP Workshop, silicon debug, microelectronics, infrastructure IP |
41 | Inhyuk Choi, Hyunggoy Oh, Young-Woo Lee, Sungho Kang 0001 |
Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 67(12), pp. 1835-1839, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
41 | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic |
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, pp. 294-299, 2006, IEEE, 978-0-7803-9707-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Kai Yang, Kwang-Ting Cheng |
Silicon Debug for Timing Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11), pp. 2084-2088, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham |
A Scheme for On-Chip Timing Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 24-29, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Sandeep Kumar Goel, Bart Vermeulen |
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 1103-1110, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra |
BLoG: post-silicon bug localization in processors using bug localization graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 368-373, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
IFRA, BLoG, silicon debug, post-silicon validation |
31 | Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi |
Debugging from high level down to gate level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 627-630, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
post-silicon debug, dependence analysis, system level design, equivalence checking, high-level design |
31 | Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan |
Online cache state dumping for processor debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 358-363, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cache compression, processor debug, silicon debug, design for debug, post-silicon validation |
31 | Desta Tadesse, R. Iris Bahar, Joel Grodstein |
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 339-344, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Microprocessor Diagnosis, Pass/Fail Region, Maximum Likelihood Estimation, Silicon Debug |
31 | Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller |
A reconfigurable design-for-debug infrastructure for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 7-12, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
assertion-based debug, at-speed debug, what-if experiments, silicon debug |
31 | Robert C. Aitken |
ITC is Cool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 616, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high-frequency test, board and system test, test compression, silicon debug, International Test Conference, ITC |
29 | Yu Huang 0005, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung |
Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 44-49, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Atanu Chattopadhyay, Zeljko Zilic |
Serial reconfigurable mismatch-tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 611-612, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
process variation, clock skew, clock networks |
25 | Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda |
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 40th IEEE VLSI Test Symposium, VTS 2022, San Diego, CA, USA, April 25-27, 2022, pp. 1-7, 2022, IEEE, 978-1-6654-1060-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Hayoung Lee, Hyunggoy Oh, Sungho Kang 0001 |
On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 56443-56456, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Sidhartha Sankar Rout, Sujay Deb, Kanad Basu |
WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11), pp. 2372-2385, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Binod Kumar 0001, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh |
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(4), pp. 1002-1015, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Kamran Rahmani, Prabhat Mishra 0001 |
Feature-Based Signal Selection for Post-Silicon Debug Using Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 8(4), pp. 907-915, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Siamack BeigMohammadi, Bijan Alizadeh |
Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1), pp. 272-276, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Yun Cheng, Huawei Li 0001, Ying Wang 0001, Xiaowei Li 0001 |
Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4), pp. 767-779, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Binod Kumar 0001, Masahiro Fujita, Virendra Singh |
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 35(5), pp. 655-678, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Amit Jakati, Manish Sharma, Joy Liao |
Innovative Practices on Software and Hardware based Silicon Debug/Fault Isolation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019, pp. 1, 2019, IEEE, 978-1-7281-1170-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Yun Cheng, Huawei Li 0001, Ying Wang 0001, Haihua Shen, Bo Liu 0018, Xiaowei Li 0001 |
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10), pp. 2166-2179, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Bijan Alizadeh, Mehdi Shakeri |
QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12), pp. 4326-4335, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Ankit Jindal, Binod Kumar 0001, Nitish Jindal, Masahiro Fujita, Virendra Singh |
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 46-51, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Yuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng 0001 |
Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 602-607, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Pallav Gupta |
An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018, pp. 1-8, 2018, IEEE, 978-1-5386-8382-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan |
Application level hardware tracing for scaling post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pp. 92:1-92:6, 2018, ACM, 978-1-5386-4114-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Hyunggoy Oh, Taewoo Han, Inhyuk Choi, Sungho Kang 0001 |
An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(1), pp. 38-44, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Hyunggoy Oh, Inhyuk Choi, Sungho Kang 0001 |
DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(9), pp. 1504-1517, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Shuo-Lian Hong, Kuen-Jong Lee |
A run-pause-resume silicon debug technique for multiple clock domain systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017, pp. 46-51, 2017, IEEE, 978-1-5386-3051-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang 0001 |
A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2017, Seoul, South Korea, November 5-8, 2017, pp. 121-122, 2017, IEEE, 978-1-5386-2285-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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25 | Yun Cheng, Huawei Li 0001, Ying Wang 0001, Yingke Gao, Bo Liu 0018, Xiaowei Li 0001 |
Flip-flop clustering based trace signal selection for post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017, pp. 1-6, 2017, IEEE Computer Society, 978-1-5090-4482-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Shuo-Lian Hong, Kuen-Jong Lee |
A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017, pp. 1-10, 2017, IEEE, 978-1-5386-3413-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Binod Kumar 0001, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita |
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 753-766, 2017, Springer, 978-981-10-7469-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Kamran Rahmani, Sudhi Proch, Prabhat Mishra 0001 |
Efficient Selection of Trace and Scan Signals for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(1), pp. 313-323, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Binod Kumar 0001, Ankit Jindal, Virendra Singh |
A trace signal selection algorithm for improved post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2016 IEEE East-West Design & Test Symposium, EWDTS 2016, Yerevan, Armenia, October 14-17, 2016, pp. 1-4, 2016, IEEE Computer Society, 978-1-5090-0693-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Siamack BeigMohammadi, Bijan Alizadeh |
Combinational trace signal selection with improved state restoration for post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 1369-1374, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
25 | Jing Zhang, Lars-Johan Fritz, Liang Liu 0002, Erik Larsson |
Compressor design for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, pp. 1-2, 2016, IEEE, 978-1-4673-9659-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Prabanjan Komari, Ranga Vemuri |
A novel simulation based approach for trace signal selection in silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, AZ, USA, October 2-5, 2016, pp. 193-200, 2016, IEEE Computer Society, 978-1-5090-5142-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Mike Ricchetti, Eric Rentschler, Amit Majumdar 0002, Mike Lowe, Mark LaVine, Skip Lindsey, Sharad Kumar |
Special panel session IIB: "System validation and silicon debug - Is standardization possible?". ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016, pp. 1, 2016, IEEE Computer Society, 978-1-4673-8454-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Yuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra 0001 |
Trace Buffer Attack: Security versus observability study in post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015, pp. 355-360, 2015, IEEE, 978-1-4673-9140-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura |
Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015, pp. 263, 2015, ACM, 978-1-4503-3315-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee |
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 1281-1284, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
25 | Amin Vali, Nicola Nicolici |
Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NATW ![In: 24th IEEE North Atlantic Test Workshop, NATW 2015, Johnson City, NY, USA, May 11-13, 2015, pp. 17-22, 2015, IEEE, 978-1-4673-7417-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif |
Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015, Salvador, Brazil, August 31 - September 4, 2015, pp. 17:1-17:7, 2015, ACM, 978-1-4503-3763-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif |
Vericonn: a tool to generate efficient interconnection networks for post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 16th Latin-American Test Symposium, LATS 2015, Puerto Vallarta, Mexico, March 25-27, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4673-6710-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Mike Ricchetti |
Innovative practices session 3C: Advances in silicon debug & diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 33rd IEEE VLSI Test Symposium, VTS 2015, Napa, CA, USA, April 27-29, 2015, pp. 1, 2015, IEEE Computer Society, 978-1-4799-7597-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Min Li, Azadeh Davoodi |
A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7), pp. 1081-1094, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Prateek Thakyal, Prabhat Mishra 0001 |
Layout-Aware Selection of Trace Signals for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014, pp. 326-331, 2014, IEEE Computer Society, 978-1-4799-3763-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Min Li, Azadeh Davoodi |
Multi-mode trace signal selection for post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014, pp. 640-645, 2014, IEEE, 978-1-4799-2816-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Yun Cheng, Huawei Li 0001, Xiaowei Li 0001 |
An On-Line Timing Error Detection Method for Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, pp. 263-268, 2014, IEEE Computer Society, 978-1-4799-6030-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Sabyasachi Deyati, Barry John Muldrey, Aritra Banerjee, Abhijit Chatterjee |
Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 32nd IEEE VLSI Test Symposium, VTS 2014, Napa, CA, USA, April 13-17, 2014, pp. 1-6, 2014, IEEE Computer Society, 978-1-4799-2611-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Sergej Deutsch, Krishnendu Chakrabarty |
Massive signal tracing using on-chip DRAM for in-system silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014, pp. 1-10, 2014, IEEE Computer Society, 978-1-4799-4722-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Joon-Sung Yang, Nur A. Touba |
Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(2), pp. 320-328, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Eddie Hung, Steven J. E. Wilton |
Scalable Signal Selection for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(6), pp. 1103-1115, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Kanad Basu, Prabhat Mishra 0001, Priyadarsan Patra, Amir Nahir, Allon Adir |
Dynamic Selection of Trace Signals for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 14th International Workshop on Microprocessor Test and Verification, MTV 2013, Austin, TX, USA, December 11-13, 2013, pp. 62-67, 2013, IEEE Computer Society, 978-1-4799-3246-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Min Li, Azadeh Davoodi |
A hybrid approach for fast and accurate trace signal selection for post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 485-490, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos |
Accelerating post silicon debug of deep electrical faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), Chania, Crete, Greece, July 8-10, 2013, pp. 61-66, 2013, IEEE, 978-1-4799-0662-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Nikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González 0001 |
Deconfigurable microprocessor architectures for silicon debug acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013, pp. 631-642, 2013, ACM, 978-1-4503-2079-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici |
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(6), pp. 1118-1131, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang 0006 |
Formal-Analysis-Based Trace Computation for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(11), pp. 1997-2010, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Joon-Sung Yang, Nur A. Touba |
Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3), pp. 442-446, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Flavio M. de Paula, Alan J. Hu, Amir Nahir |
nuTAB-BackSpace: Rewriting to Normalize Non-determinism in Post-silicon Debug Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification - 24th International Conference, CAV 2012, Berkeley, CA, USA, July 7-13, 2012 Proceedings, pp. 513-531, 2012, Springer, 978-3-642-31423-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Johnny J. W. Kuan, Tor M. Aamodt |
Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 13th International Workshop on Microprocessor Test and Verification, MTV 2012, Austin, TX, USA, December 10-13, 2012, pp. 70-75, 2012, IEEE Computer Society, 978-1-4673-4441-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita |
Automated data analysis techniques for a modern silicon debug environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, pp. 298-303, 2012, IEEE, 978-1-4673-0770-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Amir Masoud Gharehbaghi, Masahiro Fujita |
Transaction-based post-silicon debug of many-core System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 702-708, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Xiao Liu 0011, Qiang Xu 0001 |
On efficient silicon debug with flexible trace interconnection fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, pp. 1-9, 2012, IEEE Computer Society, 978-1-4673-1594-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Srikanth Venkataraman, Nagesh Tamarapalli |
Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 25th International Conference on VLSI Design, Hyderabad, India, January 7-11, 2012, pp. 16-17, 2012, IEEE Computer Society, 978-1-4673-0438-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Feng Yuan, Xiao Liu 0011, Qiang Xu 0001 |
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, pp. 555-560, 2012, ACM, 978-1-4503-1199-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Ehab Anis Daoud, Nicola Nicolici |
On Using Lossy Compression for Repeatable Experiments during Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(7), pp. 937-950, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De |
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9), pp. 2017-2025, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Xiao Liu 0011, Qiang Xu 0001 |
On multiplexed signal tracing for post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 685-690, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco |
Simulation-based signal selection for state restoration in silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, California, USA, November 7-10, 2011, pp. 595-601, 2011, IEEE Computer Society, 978-1-4577-1399-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|