Search results for "silicon-debug"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
109	Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang	Visibility enhancement for silicon debug.	DAC	2006	DBLP DOI BibTeX RDF	silicon validation, functional verification, silicon debug
103	Ehab Anis, Nicola Nicolici	Interactive presentation: Low cost debug architecture using lossy compression for silicon debug.	DATE	2007	DBLP DOI BibTeX RDF
84	Kwang-Ting (Tim) Cheng	Effective silicon debug is key for time to money.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
81	Ho Fai Ko, Nicola Nicolici	Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
80	Joon-Sung Yang, Nur A. Touba	Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture.	VTS	2008	DBLP DOI BibTeX RDF	Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR
78	Hari Balachandran, Kenneth M. Butler, Neil Simpson	Facilitating Rapid First Silicon Debug.	ITC	2002	DBLP DOI BibTeX RDF
77	Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu	A General Failure Candidate Ranking Framework for Silicon Debug.	VTS	2008	DBLP DOI BibTeX RDF	Silicon Debug
77	Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel	Automatic generation of breakpoint hardware for silicon debug.	DAC	2004	DBLP DOI BibTeX RDF	hardware-breakpoints, design-flow, silicon-debug, design-for-debug
64	Jagannath Keshava, Nagib Hakim, Chinna Prudvi	Post-silicon validation challenges: how EDA and academia can help.	DAC	2010	DBLP DOI BibTeX RDF	design, verification, test, validation, emulation
63	Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu	Diagnosing Silicon Failures Based on Functional Test Patterns.	MTV	2006	DBLP DOI BibTeX RDF	fault diagnosis, Silicon debug, design for debug
63	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
63	Doug Josephson	The good, the bad, and the ugly of silicon debug.	DAC	2006	DBLP DOI BibTeX RDF	design for test and debug, debug, validation, characterization
63	Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel	Core-Based Scan Architecture for Silicon Debug.	ITC	2002	DBLP DOI BibTeX RDF
61	Rob Aitken, Erik Jan Marinissen	Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
61	Bart Vermeulen	Functional Debug Techniques for Embedded Systems.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
58	Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger	Silicon Symptoms to Solutions: Applying Design for Debug Techniques.	ITC	2002	DBLP DOI BibTeX RDF
57	Marc Boule, Jean-Samuel Chenard, Zeljko Zilic	Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis.	ISQED	2007	DBLP DOI BibTeX RDF
57	Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Field programmable gate array, system-on-chip, integrated circuit, silicon debug
57	Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham	On-chip delay measurement for silicon debug.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	design for testability, delay fault testing, silicon debug
55	Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang 0006	BackSpace: Formal Analysis for Post-Silicon Debug.	FMCAD	2008	DBLP DOI BibTeX RDF
55	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.	MTV	2005	DBLP DOI BibTeX RDF
53	Miron Abramovici	In-System Silicon Validation and Debug.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
50	Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak	On Silicon-Based Speed Path Identification.	VTS	2005	DBLP DOI BibTeX RDF
49	Young-Jun Kwon, Ben Mathew, Hong Hao	FakeFault: a silicon debug software tool for microprocessor embedded memory arrays.	ITC	1998	DBLP DOI BibTeX RDF
46	Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green	Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP
46		Panel Summaries.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	IEEE European Test Symposium, IEEE Infrastructure IP Workshop, silicon debug, microelectronics, infrastructure IP
41	Inhyuk Choi, Hyunggoy Oh, Young-Woo Lee, Sungho Kang 0001	Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
41	Marc Boule, Jean-Samuel Chenard, Zeljko Zilic	Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.	ICCD	2006	DBLP DOI BibTeX RDF
40	Kai Yang, Kwang-Ting Cheng	Silicon Debug for Timing Errors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
35	Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham	A Scheme for On-Chip Timing Characterization.	VTS	2006	DBLP DOI BibTeX RDF
32	Sandeep Kumar Goel, Bart Vermeulen	Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	ITC	2002	DBLP DOI BibTeX RDF
31	Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra	BLoG: post-silicon bug localization in processors using bug localization graphs.	DAC	2010	DBLP DOI BibTeX RDF	IFRA, BLoG, silicon debug, post-silicon validation
31	Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi	Debugging from high level down to gate level.	DAC	2009	DBLP DOI BibTeX RDF	post-silicon debug, dependence analysis, system level design, equivalence checking, high-level design
31	Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan	Online cache state dumping for processor debug.	DAC	2009	DBLP DOI BibTeX RDF	cache compression, processor debug, silicon debug, design for debug, post-silicon validation
31	Desta Tadesse, R. Iris Bahar, Joel Grodstein	Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation.	VTS	2008	DBLP DOI BibTeX RDF	Microprocessor Diagnosis, Pass/Fail Region, Maximum Likelihood Estimation, Silicon Debug
31	Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller	A reconfigurable design-for-debug infrastructure for SoCs.	DAC	2006	DBLP DOI BibTeX RDF	assertion-based debug, at-speed debug, what-if experiments, silicon debug
31	Robert C. Aitken	ITC is Cool.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	high-frequency test, board and system test, test compression, silicon debug, International Test Conference, ITC
29	Yu Huang 0005, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung	Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
26	Atanu Chattopadhyay, Zeljko Zilic	Serial reconfigurable mismatch-tolerant clock distribution.	DAC	2009	DBLP DOI BibTeX RDF	process variation, clock skew, clock networks
25	Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda	Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.	VTS	2022	DBLP DOI BibTeX RDF
25	Hayoung Lee, Hyunggoy Oh, Sungho Kang 0001	On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug.	IEEE Access	2021	DBLP DOI BibTeX RDF
25	Sidhartha Sankar Rout, Sujay Deb, Kanad Basu	WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
25	Binod Kumar 0001, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh	A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
25	Kamran Rahmani, Prabhat Mishra 0001	Feature-Based Signal Selection for Post-Silicon Debug Using Machine Learning.	IEEE Trans. Emerg. Top. Comput.	2020	DBLP DOI BibTeX RDF
25	Siamack BeigMohammadi, Bijan Alizadeh	Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
25	Yun Cheng, Huawei Li 0001, Ying Wang 0001, Xiaowei Li 0001	Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
25	Binod Kumar 0001, Masahiro Fujita, Virendra Singh	SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.	J. Electron. Test.	2019	DBLP DOI BibTeX RDF
25	Amit Jakati, Manish Sharma, Joy Liao	Innovative Practices on Software and Hardware based Silicon Debug/Fault Isolation.	VTS	2019	DBLP DOI BibTeX RDF
25	Yun Cheng, Huawei Li 0001, Ying Wang 0001, Haihua Shen, Bo Liu 0018, Xiaowei Li 0001	On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
25	Bijan Alizadeh, Mehdi Shakeri	QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
25	Ankit Jindal, Binod Kumar 0001, Nitish Jindal, Masahiro Fujita, Virendra Singh	Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm.	ISVLSI	2018	DBLP DOI BibTeX RDF
25	Yuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng 0001	Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors.	ISVLSI	2018	DBLP DOI BibTeX RDF
25	Pallav Gupta	An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug.	ITC	2018	DBLP DOI BibTeX RDF
25	Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan	Application level hardware tracing for scaling post-silicon debug.	DAC	2018	DBLP DOI BibTeX RDF
25	Hyunggoy Oh, Taewoo Han, Inhyuk Choi, Sungho Kang 0001	An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
25	Hyunggoy Oh, Inhyuk Choi, Sungho Kang 0001	DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
25	Shuo-Lian Hong, Kuen-Jong Lee	A run-pause-resume silicon debug technique for multiple clock domain systems.	ITC-Asia	2017	DBLP DOI BibTeX RDF
25	Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang 0001	A selective error data capture method using on-chip DRAM for silicon debug of multi-core design.	ISOCC	2017	DBLP DOI BibTeX RDF
25	Yun Cheng, Huawei Li 0001, Ying Wang 0001, Yingke Gao, Bo Liu 0018, Xiaowei Li 0001	Flip-flop clustering based trace signal selection for post-silicon debug.	VTS	2017	DBLP DOI BibTeX RDF
25	Shuo-Lian Hong, Kuen-Jong Lee	A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems.	ITC	2017	DBLP DOI BibTeX RDF
25	Binod Kumar 0001, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita	A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection.	VDAT	2017	DBLP DOI BibTeX RDF
25	Kamran Rahmani, Sudhi Proch, Prabhat Mishra 0001	Efficient Selection of Trace and Scan Signals for Post-Silicon Debug.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
25	Binod Kumar 0001, Ankit Jindal, Virendra Singh	A trace signal selection algorithm for improved post-silicon debug.	EWDTS	2016	DBLP DOI BibTeX RDF
25	Siamack BeigMohammadi, Bijan Alizadeh	Combinational trace signal selection with improved state restoration for post-silicon debug.	DATE	2016	DBLP BibTeX RDF
25	Jing Zhang, Lars-Johan Fritz, Liang Liu 0002, Erik Larsson	Compressor design for silicon debug.	ETS	2016	DBLP DOI BibTeX RDF
25	Prabanjan Komari, Ranga Vemuri	A novel simulation based approach for trace signal selection in silicon debug.	ICCD	2016	DBLP DOI BibTeX RDF
25	Mike Ricchetti, Eric Rentschler, Amit Majumdar 0002, Mike Lowe, Mark LaVine, Skip Lindsey, Sharad Kumar	Special panel session IIB: "System validation and silicon debug - Is standardization possible?".	VTS	2016	DBLP DOI BibTeX RDF
25	Yuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra 0001	Trace Buffer Attack: Security versus observability study in post-silicon debug.	VLSI-SoC	2015	DBLP DOI BibTeX RDF
25	Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura	Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
25	Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee	A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC.	DATE	2015	DBLP BibTeX RDF
25	Amin Vali, Nicola Nicolici	Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug.	NATW	2015	DBLP DOI BibTeX RDF
25	André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif	Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks.	SBCCI	2015	DBLP DOI BibTeX RDF
25	André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif	Vericonn: a tool to generate efficient interconnection networks for post-silicon debug.	LATS	2015	DBLP DOI BibTeX RDF
25	Mike Ricchetti	Innovative practices session 3C: Advances in silicon debug & diagnosis.	VTS	2015	DBLP DOI BibTeX RDF
25	Min Li, Azadeh Davoodi	A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
25	Prateek Thakyal, Prabhat Mishra 0001	Layout-Aware Selection of Trace Signals for Post-Silicon Debug.	ISVLSI	2014	DBLP DOI BibTeX RDF
25	Min Li, Azadeh Davoodi	Multi-mode trace signal selection for post-silicon debug.	ASP-DAC	2014	DBLP DOI BibTeX RDF
25	Yun Cheng, Huawei Li 0001, Xiaowei Li 0001	An On-Line Timing Error Detection Method for Silicon Debug.	ATS	2014	DBLP DOI BibTeX RDF
25	Sabyasachi Deyati, Barry John Muldrey, Aritra Banerjee, Abhijit Chatterjee	Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits.	VTS	2014	DBLP DOI BibTeX RDF
25	Sergej Deutsch, Krishnendu Chakrabarty	Massive signal tracing using on-chip DRAM for in-system silicon debug.	ITC	2014	DBLP DOI BibTeX RDF
25	Joon-Sung Yang, Nur A. Touba	Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
25	Eddie Hung, Steven J. E. Wilton	Scalable Signal Selection for Post-Silicon Debug.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
25	Kanad Basu, Prabhat Mishra 0001, Priyadarsan Patra, Amir Nahir, Allon Adir	Dynamic Selection of Trace Signals for Post-Silicon Debug.	MTV	2013	DBLP DOI BibTeX RDF
25	Min Li, Azadeh Davoodi	A hybrid approach for fast and accurate trace signal selection for post-silicon debug.	DATE	2013	DBLP DOI BibTeX RDF
25	Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos	Accelerating post silicon debug of deep electrical faults.	IOLTS	2013	DBLP DOI BibTeX RDF
25	Nikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González 0001	Deconfigurable microprocessor architectures for silicon debug acceleration.	ISCA	2013	DBLP DOI BibTeX RDF
25	Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici	Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
25	Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang 0006	Formal-Analysis-Based Trace Computation for Post-Silicon Debug.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
25	Joon-Sung Yang, Nur A. Touba	Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2012	DBLP DOI BibTeX RDF
25	Flavio M. de Paula, Alan J. Hu, Amir Nahir	nuTAB-BackSpace: Rewriting to Normalize Non-determinism in Post-silicon Debug Traces.	CAV	2012	DBLP DOI BibTeX RDF
25	Johnny J. W. Kuan, Tor M. Aamodt	Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug.	MTV	2012	DBLP DOI BibTeX RDF
25	Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita	Automated data analysis techniques for a modern silicon debug environment.	ASP-DAC	2012	DBLP DOI BibTeX RDF
25	Amir Masoud Gharehbaghi, Masahiro Fujita	Transaction-based post-silicon debug of many-core System-on-Chips.	ISQED	2012	DBLP DOI BibTeX RDF
25	Xiao Liu 0011, Qiang Xu 0001	On efficient silicon debug with flexible trace interconnection fabric.	ITC	2012	DBLP DOI BibTeX RDF
25	Srikanth Venkataraman, Nagesh Tamarapalli	Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield.	VLSI Design	2012	DBLP DOI BibTeX RDF
25	Feng Yuan, Xiao Liu 0011, Qiang Xu 0001	X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug.	DAC	2012	DBLP DOI BibTeX RDF
25	Ehab Anis Daoud, Nicola Nicolici	On Using Lossy Compression for Repeatable Experiments during Silicon Debug.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
25	Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
25	Xiao Liu 0011, Qiang Xu 0001	On multiplexed signal tracing for post-silicon debug.	DATE	2011	DBLP DOI BibTeX RDF
25	Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco	Simulation-based signal selection for state restoration in silicon debug.	ICCAD	2011	DBLP DOI BibTeX RDF