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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4075 occurrences of 1437 keywords
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Results
Found 23195 publication records. Showing 23195 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | Chunhong Chen |
Physical design with multiple on-chip voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 118-118, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
66 | Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer |
Energy-conscious compilation based on voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 2-11, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
energy-aware compilation, optimizing compilers, voltage scaling, loop transformations |
65 | Luis Henrique de Carvalho Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. M. Van Noije |
Ultra low-voltage ultra low-power CMOS threshold voltage reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 80-82, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, CMOS, low voltage, threshold voltage, voltage reference |
62 | Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg |
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 147-160, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
memory technology, dynamic voltage scaling, DRAM, molecular electronics, molecular memory, low-power memory |
61 | Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou |
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 381-386, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
stochastic gradient search, scheduling, optimization, power management, dynamic voltage scaling (DVS), heterogeneous systems, multi-processor systems |
60 | Selçuk Köse, Eby G. Friedman |
On-chip point-of-load voltage regulator for distributed power supplies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 377-380, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dc-dc voltage regulation, on-chip voltage regulator, power delivery, active filter |
58 | Abhishek A. Sinkar, Nam Sung Kim |
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 189-194, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptive voltage positioning, multicore processor |
56 | Huizhan Yi, Xuejun Yang |
Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 79-88, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Jongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang |
A Prevenient Voltage Stress Test Method for High Density Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 516-520, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
voltage stress test, acceleration factor, burn-in test, junction temperature, constant voltage stress, voltage ramp stress, reliability |
52 | Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao |
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 233-236, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage |
52 | Volkan Kursun, Eby G. Friedman |
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 104-109, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Dylan Dah-Chuan Lu, David Ki-Wai Cheng, Yim-Shu Lee |
Single-switch flyback power-factor-corrected AC/DC converter with loosely regulated intermediate storage capacitor voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 264-267, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
50 | Puru Choudhary, Diana Marculescu |
Hardware based frequency/voltage control of voltage frequency island systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 34-39, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic frequency and voltage scaling, mixed-clock fifos, voltage-frequency islands, throughput, globally asynchronous locally synchronous |
50 | Jonathan T.-Y. Chang, Edward J. McCluskey |
Quantitative analysis of very-low-voltage testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 332-337, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
very-low-voltage testing, static CMOS chips, supply voltage, rated conditions, early-life failures, test conditions, test speed, VLSI, VLSI, integrated circuit testing, CMOS integrated circuits, failure analysis, quantitative analysis, threshold voltage, integrated circuit noise |
50 | Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner |
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1239-1252, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Adnan Khashman, Kadri Buruncuk, Samir Jabr |
Intelligent Detection of Voltage Instability in Power Distribution Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: Computational and Ambient Intelligence, 9th International Work-Conference on Artificial Neural Networks, IWANN 2007, San Sebastián, Spain, June 20-22, 2007, Proceedings, pp. 870-877, 2007, Springer, 978-3-540-73006-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Voltage Instability Detection, Neural networks, Image Processing, Intelligent Systems, Power Distribution Systems |
50 | Sherif A. Tawfik, Volkan Kursun |
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 62-67, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD |
50 | Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu |
Post-placement voltage island generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 641-646, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
tree, floorplanning, voltage island |
50 | Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu |
Architecting voltage islands in core-based system-on-a-chip designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 180-185, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiple VDD, low-power, floorplanning, system-on-a-chip, voltage island |
50 | Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner |
Theoretical and practical limits of dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 868-873, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
minimum energy point, dynamic voltage scaling |
50 | Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge |
Reducing pipeline energy demands with local DVS and dynamic retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 319-324, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dynamic retiming with global DVS, local DVS, razor |
48 | Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David Cox, Mohammad M. Mojarradi |
A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 218-221, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Han-Saem Yun, Jihong Kim 0001 |
On energy-optimal voltage scheduling for fixed-priority hard real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 2(3), pp. 393-430, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
real-time systems, approximation algorithms, dynamic voltage scaling, Fixed-priority scheduling, fully polynomial time approximation scheme, variable voltage processor |
46 | Woo-Cheol Kwon, Taewhan Kim |
Optimal voltage allocation techniques for dynamically variable voltage processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(1), pp. 211-230, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, low power design, Dynamic voltage scaling, variable voltage processor |
46 | Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri |
A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 504-506, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Weixun Wang, Prabhat Mishra 0001 |
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 705-710, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
real-time systems, approximation algorithm, dynamic voltage scaling, energy-aware scheduling |
46 | Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti |
Postplacement voltage assignment under performance constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 46:1-46:20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
voltage assignment, Low power, timing, Voronoi diagram |
46 | Le Yan, Lin Zhong 0001, Niraj K. Jha |
User-perceived latency driven voltage scaling for interactive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 624-627, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
adaptive body biasing, computer responsiveness, dynamic voltage scaling, power consumption |
46 | Yann-Hang Lee, Yoonmee Doh, C. Mani Krishna 0001 |
EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 221-228, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
dynamic reclaiming, energy and power optimization, scheduling, real-time systems, voltage scaling |
44 | Huaizhi Wu, Martin D. F. Wong, I-Min Liu |
Timing-constrained and voltage-island-aware voltage assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 429-432, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
voltage assignment, low power, timing, voronoi diagram |
44 | Koichi Nose, Soo-Ik Chae, Takayasu Sakurai |
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 228-230, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
gate capacitance, low supply voltage, low-power design |
44 | Juan José Carrillo, Elkim Roa, José Vieira, Wilhelmus A. M. Van Noije |
A low-voltage bandgap reference source based on the current-mode technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS voltage reference, temperature coefficient, analog circuits, low voltage |
44 | Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Enabling ultra low voltage system operation by tolerating on-chip cache failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 307-310, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fault-tolerant cache, low voltage operation, dynamic voltage scaling |
44 | Filipe G. Ramos, Laercio Caldeira, Tales Cleber Pimenta |
A programmable voltage reference optimized for power management applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 36-41, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DC/DC converter, programmable voltage reference, power management, voltage reference |
44 | Zhiyu Liu, Volkan Kursun |
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 31-36, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage |
44 | Jeffrey A. Barnett |
Dynamic Task-Level Voltage Scheduling Optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(5), pp. 508-520, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic voltage scheduling, agile voltage scheduling, power management points, energy management, Energy-aware systems, time management |
44 | Jonathan T.-Y. Chang, Edward J. McCluskey |
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 446-, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC |
44 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 344-353, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
44 | Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong |
Incremental power optimization for multiple supply voltage design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 280-286, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
44 | Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri |
A Single-supply True Voltage Level Shifter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 979-984, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree |
A Robust Level-Shifter Design for Adaptive Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 383-388, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Jingmeng Liu, Tianmiao Wang, Dong Xu 0005, Lipeng Sun |
Research on high-voltage inverter controlling system based on wave algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAM ![In: 2008 IEEE Conference on Robotics, Automation and Mechatronics, RAM 2008, 21-24 September 2008, Chengdu, China, pp. 970-975, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Jiong Luo, Niraj K. Jha, Li-Shiuan Peh |
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 427-437, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Kayhan Gulez, Ibrahim Aliskan, Tarik Veli Mumcu, Galip Cansever |
Neural Network Based Control of AC-AC Converter for Voltage Sags, Harmonics and EMI Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (1) ![In: Advanced Intelligent Computing Theories and Applications. With Aspects of Theoretical and Methodological Issues, Third International Conference on Intelligent Computing, ICIC 2007, Qingdao, China, August 21-24, 2007, Proceedings, pp. 534-544, 2007, Springer, 978-3-540-74170-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, Chung-Chih Hung |
A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3844-3847, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Taewhan Kim |
Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia, pp. 199-206, 2006, IEEE Computer Society, 0-7695-2676-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(9), pp. 1103-1107, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Huizhan Yi, Xuejun Yang, Juan Chen 0001 |
The Optimal Profile-Guided Greedy Dynamic Voltage Scaling in Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 708-719, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Anirudh Devgan |
Transient simulation of integrated circuits in the charge-voltage plane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11), pp. 1379-1390, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
44 | Anirudh Devgan |
Efficient and accurate transient simulation in charge-voltage plane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 110-114, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
44 | Wanli Jiang, Eric Peterson |
Performance Comparison of VLV, ULV, and ECR Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(2), pp. 137-147, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
very low voltage test, dynamic current test, test threshold, test effectiveness, test efficiency |
44 | Mark C. Johnson, Kaushik Roy 0001 |
Datapath scheduling with multiple supply voltages and level converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 2(3), pp. 227-248, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
datapath scheduling, level conversion, scheduling, high-level synthesis, low power design, DSP, power optimization, multiple voltage |
42 | Christian Jesús B. Fayomi, Gilson I. Wirth, Jaime Ramírez-Angulo, Akira Matsuzawa |
"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1716-1719, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Cosmin Popa |
Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 117-124, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Ming-Dou Ker, Hung-Tai Liao |
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1121-1124, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Erik J. Mentze, Herbert L. Hess, Kevin M. Buck, T. G. Windley |
A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(12), pp. 1347-1353, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Jaewon Seo, Nikil D. Dutt |
A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 836-841, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Nestoras Tzartzanis, William W. Walker |
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 107-, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Pavel Ghosh, Arunabha Sen |
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 535-541, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
greedy randomized heuristic, multi-processor system-on-chip (MPSoC), integer linear program, network-on-chip (NoC), voltage islanding |
42 | Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier |
Thermal-aware voltage droop compensation for multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 335-340, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
monitor network-on-chip, thermal monitor, voltage emergency |
42 | Noraliza Hamzah, Hanim Ismail, Zuhaina Zakaria |
The Application of Support Vector Machine in Classifying the Causes of Voltage Sag in Power System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSKT ![In: Rough Sets and Knowledge Technology, 4th International Conference, RSKT 2009, Gold Coast, Australia, July 14-16, 2009. Proceedings, pp. 421-428, 2009, Springer, 978-3-642-02961-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
voltage sag, support vector machine, radial basis function, polynomial, Power quality |
42 | Wen Chang Huang, Jin Chang Cheng, Po Chih Liou |
A Charge Pump Circuit - Cascading High-Voltage Clock Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 332-337, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
voltage doubler, Charge pump |
42 | Dipanjan Sengupta, Resve A. Saleh |
Application-driven floorplan-aware voltage island design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 155-160, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dynamic programming, energy, floorplan, voltage island |
42 | Seung Woo Son 0001, Konrad Malkowski, Guilin Chen, Mahmut T. Kandemir, Padma Raghavan |
Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 41(3), pp. 179-213, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Parallel sparse matrix, Computation, Dynamic voltage scaling, Communication networks, Energy consumption |
42 | Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He 0001, Tanay Karnik |
Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 326-329, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
DC/DC conversion, zero voltage switching |
42 | Jean Michel Daga, E. Ottaviano, Daniel Auvergne |
Temperature Effect on Delay for Low Voltage Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 680-685, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
temperature effect, derating, Low power, delay, Low voltage |
42 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 467-472, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage |
40 | Kim M. Hazelwood, David M. Brooks |
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 326-331, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
voltage emergencies, power-aware computing, hardware-software co-design, dI/dt |
40 | Leila Koushaeian, Stan Skafidas |
A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 95-98, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bandgap voltage reference, self-biased, self-cascode, temperature coefficient, voltage reference |
40 | Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu |
Collaborative voltage scaling with online STA and variable-latency datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 347-352, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
collaborative voltage scaling, online STA, variable-latency datapath, adaptive voltage scaling |
40 | Bei Yu 0001, Sheqin Dong, Satoshi Goto, Song Chen 0001 |
Voltage-island driven floorplanning considering level-shifter positions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 51-56, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
convex network flow, level shifter assignment, voltage assignment, white space redistribution, voltage-island |
40 | Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia |
On-die CMOS voltage droop detection and dynamiccompensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 35-40, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
di/dt voltage droop, on-die voltage droop compensation, power supply droop, predictive current injection |
40 | Omid Mirmotahari, Yngvar Berg |
Low Voltage Design against Power Analysis Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 545-548, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Low Voltage (LV), Floating-Gate (FG) and supply current analysis, Differential Power Analysis (DPA), Ultra Low Voltage (ULV) |
40 | Maha Nizam, Farid N. Najm, Anirudh Devgan |
Power grid voltage integrity verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 239-244, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
voltage integrity, power grid, voltage drop |
40 | Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo |
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 84-87, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
variable supply voltage, low power, finite state machine, dynamic voltage scaling, formal model, synchronous dataflow |
39 | Huaizhi Wu, Martin D. F. Wong |
Incremental Improvement of Voltage Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2), pp. 217-230, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Licheng Jin, Ratnesh Kumar 0001, Nicola Elia |
Security constrained emergency voltage stabilization: A Model Predictive Control based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: Proceedings of the 47th IEEE Conference on Decision and Control, CDC 2008, December 9-11, 2008, Cancún, Mexico, pp. 2469-2474, 2008, IEEE, 978-1-4244-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Pavel Ghosh, Arunabha Sen |
Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 79-84, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi |
Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 262-275, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Qiang Ma 0002, Evangeline F. Y. Young |
Voltage island-driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 644-649, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Huaizhi Wu, Martin D. F. Wong |
Improving Voltage Assignment by Outlier Detection and Incremental Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 459-464, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Eric Karl, Dennis Sylvester, David T. Blaauw |
Timing error correction techniques for voltage-scalable on-chip memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3563-3566, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada |
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 423-432, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Saowanee Saewong, Ragunathan Rajkumar |
Practical Voltage-Scaling for Fixed-Priority RT-Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: Proceedings of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2003), May 27-30, 2003, Toronto, Canada, pp. 106-, 2003, IEEE Computer Society, 0-7695-1956-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg |
A case for dynamic pipeline scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 1-8, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating |
38 | Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang 0001, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De |
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 26-29, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt |
38 | Felipe Rodríguez Valdés, Julio Avila, Raymundo A. Caballero Pimentel, David Castro Baltasar |
Breakdown Voltage Behavior Under High Voltage and Frequency Signals on Isolating Solid Materials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONIELECOMP ![In: 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005 - 2 March 2005, Puebla, Mexico, pp. 78-82, 2005, IEEE Computer Society, 0-7695-2283-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai |
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1859-1862, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Ferdinando Bedeschi, Edoardo Bonizzoni, Andrea Fantini, Claudio Resta, Guido Torelli |
A low-power low-voltage MOSFET-only voltage reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 57-60, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman |
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 517-521, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Fernando Muñoz 0001, Antonio J. López-Martín, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio Jesús Torralba Silgado, Meghraj Kachare, Bernardo Palomo Vázquez |
Extremely low supply voltage circuits based on quasi-floating gate supply voltage boosting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 817-820, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada |
DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 305-308, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Tohru Ishihara, Hiroto Yasuura |
Voltage scheduling problem for dynamically variable voltage processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 197-202, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li 0001 |
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 831-836, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
low-dropout regulator, on-chip voltage regulation, power delivery network, power efficiency |
38 | Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang |
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 5-12, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multiple-supply voltage designs, physical design, floorplanning, vlsi |
38 | Jungseob Lee, Nam Sung Kim |
Optimizing total power of many-core processors considering voltage scaling limit and process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 201-206, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
voltage and frequency scaling, process variations, parallel applications, many-core processor |
38 | M. Ali-Bakhshian, K. Sadeghi |
A novel continuous-time common-mode feedback for low-voltage switched-OPAMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 296-300, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CMFB, delta-sigma, switched-OPAMP, low-voltage, continuous-time |
38 | Jaewon Seo, Taewhan Kim, Ki-Seok Chung |
Profile-based optimal intra-task voltage scheduling for hard real-time applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 87-92, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
intra-task voltage scheduling, DVS, low energy design |
38 | Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob |
A control-theoretic approach to dynamic voltage scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 255-266, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
nqPID, low-power, dynamic voltage scaling, PID |
38 | Ed Grochowski, David Ayers, Vivek Tiwari |
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 7-16, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Power delivery, supply voltage drop, simulation, microprocessor, inductive noise, di/dt |
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