Search results for "voltage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
78	Chunhong Chen	Physical design with multiple on-chip voltages.	ISPD	2002	DBLP DOI BibTeX RDF
66	Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer	Energy-conscious compilation based on voltage scaling.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	energy-aware compilation, optimizing compilers, voltage scaling, loop transformations
65	Luis Henrique de Carvalho Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. M. Van Noije	Ultra low-voltage ultra low-power CMOS threshold voltage reference.	SBCCI	2006	DBLP DOI BibTeX RDF	low power, CMOS, low voltage, threshold voltage, voltage reference
62	Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg	ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	memory technology, dynamic voltage scaling, DRAM, molecular electronics, molecular memory, low-power memory
61	Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou	An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes.	ISLPED	2004	DBLP DOI BibTeX RDF	stochastic gradient search, scheduling, optimization, power management, dynamic voltage scaling (DVS), heterogeneous systems, multi-processor systems
60	Selçuk Köse, Eby G. Friedman	On-chip point-of-load voltage regulator for distributed power supplies.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	dc-dc voltage regulation, on-chip voltage regulator, power delivery, active filter
58	Abhishek A. Sinkar, Nam Sung Kim	Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive voltage positioning, multicore processor
56	Huizhan Yi, Xuejun Yang	Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
54	Jongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang	A Prevenient Voltage Stress Test Method for High Density Memory.	DELTA	2008	DBLP DOI BibTeX RDF	voltage stress test, acceleration factor, burn-in test, junction temperature, constant voltage stress, voltage ramp stress, reliability
52	Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.	ISVLSI	2004	DBLP DOI BibTeX RDF	CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
52	Volkan Kursun, Eby G. Friedman	Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
52	Dylan Dah-Chuan Lu, David Ki-Wai Cheng, Yim-Shu Lee	Single-switch flyback power-factor-corrected AC/DC converter with loosely regulated intermediate storage capacitor voltage.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
50	Puru Choudhary, Diana Marculescu	Hardware based frequency/voltage control of voltage frequency island systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	dynamic frequency and voltage scaling, mixed-clock fifos, voltage-frequency islands, throughput, globally asynchronous locally synchronous
50	Jonathan T.-Y. Chang, Edward J. McCluskey	Quantitative analysis of very-low-voltage testing.	VTS	1996	DBLP DOI BibTeX RDF	very-low-voltage testing, static CMOS chips, supply voltage, rated conditions, early-life failures, test conditions, test speed, VLSI, VLSI, integrated circuit testing, CMOS integrated circuits, failure analysis, quantitative analysis, threshold voltage, integrated circuit noise
50	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
50	Adnan Khashman, Kadri Buruncuk, Samir Jabr	Intelligent Detection of Voltage Instability in Power Distribution Systems.	IWANN	2007	DBLP DOI BibTeX RDF	Voltage Instability Detection, Neural networks, Image Processing, Intelligent Systems, Power Distribution Systems
50	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
50	Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu	Post-placement voltage island generation.	ICCAD	2006	DBLP DOI BibTeX RDF	tree, floorplanning, voltage island
50	Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu	Architecting voltage islands in core-based system-on-a-chip designs.	ISLPED	2004	DBLP DOI BibTeX RDF	multiple VDD, low-power, floorplanning, system-on-a-chip, voltage island
50	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	Theoretical and practical limits of dynamic voltage scaling.	DAC	2004	DBLP DOI BibTeX RDF	minimum energy point, dynamic voltage scaling
50	Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge	Reducing pipeline energy demands with local DVS and dynamic retiming.	ISLPED	2004	DBLP DOI BibTeX RDF	dynamic retiming with global DVS, local DVS, razor
48	Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David Cox, Mohammad M. Mojarradi	A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI Process.	ISVLSI	2004	DBLP DOI BibTeX RDF
48	Han-Saem Yun, Jihong Kim 0001	On energy-optimal voltage scheduling for fixed-priority hard real-time systems.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	real-time systems, approximation algorithms, dynamic voltage scaling, Fixed-priority scheduling, fully polynomial time approximation scheme, variable voltage processor
46	Woo-Cheol Kwon, Taewhan Kim	Optimal voltage allocation techniques for dynamically variable voltage processors.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	scheduling, low power design, Dynamic voltage scaling, variable voltage processor
46	Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri	A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature.	VLSI Design	2003	DBLP DOI BibTeX RDF
46	Weixun Wang, Prabhat Mishra 0001	PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme.	DAC	2010	DBLP DOI BibTeX RDF	real-time systems, approximation algorithm, dynamic voltage scaling, energy-aware scheduling
46	Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti	Postplacement voltage assignment under performance constraints.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	voltage assignment, Low power, timing, Voronoi diagram
46	Le Yan, Lin Zhong 0001, Niraj K. Jha	User-perceived latency driven voltage scaling for interactive applications.	DAC	2005	DBLP DOI BibTeX RDF	adaptive body biasing, computer responsiveness, dynamic voltage scaling, power consumption
46	Yann-Hang Lee, Yoonmee Doh, C. Mani Krishna 0001	EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems.	CASES	2001	DBLP DOI BibTeX RDF	dynamic reclaiming, energy and power optimization, scheduling, real-time systems, voltage scaling
44	Huaizhi Wu, Martin D. F. Wong, I-Min Liu	Timing-constrained and voltage-island-aware voltage assignment.	DAC	2006	DBLP DOI BibTeX RDF	voltage assignment, low power, timing, voronoi diagram
44	Koichi Nose, Soo-Ik Chae, Takayasu Sakurai	Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	gate capacitance, low supply voltage, low-power design
44	Juan José Carrillo, Elkim Roa, José Vieira, Wilhelmus A. M. Van Noije	A low-voltage bandgap reference source based on the current-mode technique.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS voltage reference, temperature coefficient, analog circuits, low voltage
44	Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Enabling ultra low voltage system operation by tolerating on-chip cache failures.	ISLPED	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, low voltage operation, dynamic voltage scaling
44	Filipe G. Ramos, Laercio Caldeira, Tales Cleber Pimenta	A programmable voltage reference optimized for power management applications.	SBCCI	2007	DBLP DOI BibTeX RDF	DC/DC converter, programmable voltage reference, power management, voltage reference
44	Zhiyu Liu, Volkan Kursun	Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages.	ISQED	2006	DBLP DOI BibTeX RDF	Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage
44	Jeffrey A. Barnett	Dynamic Task-Level Voltage Scheduling Optimizations.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	dynamic voltage scheduling, agile voltage scheduling, power management points, energy management, Energy-aware systems, time management
44	Jonathan T.-Y. Chang, Edward J. McCluskey	SHOrt voltage elevation (SHOVE) test for weak CMOS ICs.	VTS	1997	DBLP DOI BibTeX RDF	short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC
44	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
44	Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong	Incremental power optimization for multiple supply voltage design.	ISQED	2009	DBLP DOI BibTeX RDF
44	Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri	A Single-supply True Voltage Level Shifter.	DATE	2008	DBLP DOI BibTeX RDF
44	Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree	A Robust Level-Shifter Design for Adaptive Voltage Scaling.	VLSI Design	2008	DBLP DOI BibTeX RDF
44	Jingmeng Liu, Tianmiao Wang, Dong Xu 0005, Lipeng Sun	Research on high-voltage inverter controlling system based on wave algorithm.	RAM	2008	DBLP DOI BibTeX RDF
44	Jiong Luo, Niraj K. Jha, Li-Shiuan Peh	Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
44	Kayhan Gulez, Ibrahim Aliskan, Tarik Veli Mumcu, Galip Cansever	Neural Network Based Control of AC-AC Converter for Voltage Sags, Harmonics and EMI Reduction.	ICIC (1)	2007	DBLP DOI BibTeX RDF
44	Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, Chung-Chih Hung	A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation.	ISCAS	2007	DBLP DOI BibTeX RDF
44	Taewhan Kim	Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling.	RTCSA	2006	DBLP DOI BibTeX RDF
44	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
44	Huizhan Yi, Xuejun Yang, Juan Chen 0001	The Optimal Profile-Guided Greedy Dynamic Voltage Scaling in Real-Time Applications.	ICESS	2005	DBLP DOI BibTeX RDF
44	Anirudh Devgan	Transient simulation of integrated circuits in the charge-voltage plane.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
44	Anirudh Devgan	Efficient and accurate transient simulation in charge-voltage plane.	ICCAD	1995	DBLP DOI BibTeX RDF
44	Wanli Jiang, Eric Peterson	Performance Comparison of VLV, ULV, and ECR Tests.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	very low voltage test, dynamic current test, test threshold, test effectiveness, test efficiency
44	Mark C. Johnson, Kaushik Roy 0001	Datapath scheduling with multiple supply voltages and level converters.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	datapath scheduling, level conversion, scheduling, high-level synthesis, low power design, DSP, power optimization, multiple voltage
42	Christian Jesús B. Fayomi, Gilson I. Wirth, Jaime Ramírez-Angulo, Akira Matsuzawa	"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
42	Cosmin Popa	Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs.	PATMOS	2007	DBLP DOI BibTeX RDF
42	Ming-Dou Ker, Hung-Tai Liao	Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
42	Erik J. Mentze, Herbert L. Hess, Kevin M. Buck, T. G. Windley	A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
42	Jaewon Seo, Nikil D. Dutt	A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
42	Nestoras Tzartzanis, William W. Walker	A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File.	ICCD	2003	DBLP DOI BibTeX RDF
42	Pavel Ghosh, Arunabha Sen	Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints.	SAC	2010	DBLP DOI BibTeX RDF	greedy randomized heuristic, multi-processor system-on-chip (MPSoC), integer linear program, network-on-chip (NoC), voltage islanding
42	Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier	Thermal-aware voltage droop compensation for multi-core architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	monitor network-on-chip, thermal monitor, voltage emergency
42	Noraliza Hamzah, Hanim Ismail, Zuhaina Zakaria	The Application of Support Vector Machine in Classifying the Causes of Voltage Sag in Power System.	RSKT	2009	DBLP DOI BibTeX RDF	voltage sag, support vector machine, radial basis function, polynomial, Power quality
42	Wen Chang Huang, Jin Chang Cheng, Po Chih Liou	A Charge Pump Circuit - Cascading High-Voltage Clock Generator.	DELTA	2008	DBLP DOI BibTeX RDF	voltage doubler, Charge pump
42	Dipanjan Sengupta, Resve A. Saleh	Application-driven floorplan-aware voltage island design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic programming, energy, floorplan, voltage island
42	Seung Woo Son 0001, Konrad Malkowski, Guilin Chen, Mahmut T. Kandemir, Padma Raghavan	Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Parallel sparse matrix, Computation, Dynamic voltage scaling, Communication networks, Energy consumption
42	Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He 0001, Tanay Karnik	Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.	ISLPED	2006	DBLP DOI BibTeX RDF	DC/DC conversion, zero voltage switching
42	Jean Michel Daga, E. Ottaviano, Daniel Auvergne	Temperature Effect on Delay for Low Voltage Applications.	DATE	1998	DBLP DOI BibTeX RDF	temperature effect, derating, Low power, delay, Low voltage
42	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Low-swing clock domino logic incorporating dual supply and dual threshold voltages.	DAC	2002	DBLP DOI BibTeX RDF	low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage
40	Kim M. Hazelwood, David M. Brooks	Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization.	ISLPED	2004	DBLP DOI BibTeX RDF	voltage emergencies, power-aware computing, hardware-software co-design, dI/dt
40	Leila Koushaeian, Stan Skafidas	A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp.	ISLPED	2010	DBLP DOI BibTeX RDF	bandgap voltage reference, self-biased, self-cascode, temperature coefficient, voltage reference
40	Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu	Collaborative voltage scaling with online STA and variable-latency datapath.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	collaborative voltage scaling, online STA, variable-latency datapath, adaptive voltage scaling
40	Bei Yu 0001, Sheqin Dong, Satoshi Goto, Song Chen 0001	Voltage-island driven floorplanning considering level-shifter positions.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	convex network flow, level shifter assignment, voltage assignment, white space redistribution, voltage-island
40	Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia	On-die CMOS voltage droop detection and dynamiccompensation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	di/dt voltage droop, on-die voltage droop compensation, power supply droop, predictive current injection
40	Omid Mirmotahari, Yngvar Berg	Low Voltage Design against Power Analysis Attacks.	DELTA	2008	DBLP DOI BibTeX RDF	Low Voltage (LV), Floating-Gate (FG) and supply current analysis, Differential Power Analysis (DPA), Ultra Low Voltage (ULV)
40	Maha Nizam, Farid N. Najm, Anirudh Devgan	Power grid voltage integrity verification.	ISLPED	2005	DBLP DOI BibTeX RDF	voltage integrity, power grid, voltage drop
40	Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo	An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model.	ISLPED	2002	DBLP DOI BibTeX RDF	variable supply voltage, low power, finite state machine, dynamic voltage scaling, formal model, synchronous dataflow
39	Huaizhi Wu, Martin D. F. Wong	Incremental Improvement of Voltage Assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
39	Licheng Jin, Ratnesh Kumar 0001, Nicola Elia	Security constrained emergency voltage stabilization: A Model Predictive Control based approach.	CDC	2008	DBLP DOI BibTeX RDF
39	Pavel Ghosh, Arunabha Sen	Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoC.	SoCC	2008	DBLP DOI BibTeX RDF
39	Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz, Bashir M. Al-Hashimi	Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
39	Qiang Ma 0002, Evangeline F. Y. Young	Voltage island-driven floorplanning.	ICCAD	2007	DBLP DOI BibTeX RDF
39	Huaizhi Wu, Martin D. F. Wong	Improving Voltage Assignment by Outlier Detection and Incremental Placement.	DAC	2007	DBLP DOI BibTeX RDF
39	Eric Karl, Dennis Sylvester, David T. Blaauw	Timing error correction techniques for voltage-scalable on-chip memories.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
39	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
39	Saowanee Saewong, Ragunathan Rajkumar	Practical Voltage-Scaling for Fixed-Priority RT-Systems.	IEEE Real Time Technology and Applications Symposium	2003	DBLP DOI BibTeX RDF
39	Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg	A case for dynamic pipeline scaling.	CASES	2002	DBLP DOI BibTeX RDF	configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating
38	Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang 0001, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.	ISLPED	2005	DBLP DOI BibTeX RDF	Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt
38	Felipe Rodríguez Valdés, Julio Avila, Raymundo A. Caballero Pimentel, David Castro Baltasar	Breakdown Voltage Behavior Under High Voltage and Frequency Signals on Isolating Solid Materials.	CONIELECOMP	2005	DBLP DOI BibTeX RDF
38	Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai	Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
38	Ferdinando Bedeschi, Edoardo Bonizzoni, Andrea Fantini, Claudio Resta, Guido Torelli	A low-power low-voltage MOSFET-only voltage reference.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
38	Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman	High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.	ISQED	2004	DBLP DOI BibTeX RDF
38	Fernando Muñoz 0001, Antonio J. López-Martín, Ramón González Carvajal, Jaime Ramírez-Angulo, Antonio Jesús Torralba Silgado, Meghraj Kachare, Bernardo Palomo Vázquez	Extremely low supply voltage circuits based on quasi-floating gate supply voltage boosting.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
38	Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada	DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path.	ISQED	2000	DBLP DOI BibTeX RDF
38	Tohru Ishihara, Hiroto Yasuura	Voltage scheduling problem for dynamically variable voltage processors.	ISLPED	1998	DBLP DOI BibTeX RDF
38	Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li 0001	Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation.	DAC	2010	DBLP DOI BibTeX RDF	low-dropout regulator, on-chip voltage regulation, power delivery network, power efficiency
38	Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs.	ISPD	2009	DBLP DOI BibTeX RDF	multiple-supply voltage designs, physical design, floorplanning, vlsi
38	Jungseob Lee, Nam Sung Kim	Optimizing total power of many-core processors considering voltage scaling limit and process variations.	ISLPED	2009	DBLP DOI BibTeX RDF	voltage and frequency scaling, process variations, parallel applications, many-core processor
38	M. Ali-Bakhshian, K. Sadeghi	A novel continuous-time common-mode feedback for low-voltage switched-OPAMP.	ISLPED	2004	DBLP DOI BibTeX RDF	CMFB, delta-sigma, switched-OPAMP, low-voltage, continuous-time
38	Jaewon Seo, Taewhan Kim, Ki-Seok Chung	Profile-based optimal intra-task voltage scheduling for hard real-time applications.	DAC	2004	DBLP DOI BibTeX RDF	intra-task voltage scheduling, DVS, low energy design
38	Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob	A control-theoretic approach to dynamic voltage scheduling.	CASES	2003	DBLP DOI BibTeX RDF	nqPID, low-power, dynamic voltage scaling, PID
38	Ed Grochowski, David Ayers, Vivek Tiwari	Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation.	HPCA	2002	DBLP DOI BibTeX RDF	Power delivery, supply voltage drop, simulation, microprocessor, inductive noise, di/dt