Search results for "wires"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
86	Valeriu Beiu, Walid Ibrahim, Rafic Z. Makki	On Wires Holding a Handful of Electrons.	NanoNet	2009	DBLP DOI BibTeX RDF	Nano-electronics, interconnects (wires), noise (intrinsic), reliability, communication
77	Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska	Postlayout logic restructuring using alternative wires.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
70	Saroj K. Nayak	Carbon nanotube, graphene and atomic wires as next generation interconnects: current status and future promise.	SLIP	2009	DBLP DOI BibTeX RDF	quantum simulation, performance, design, reliability
64	Michal Koucký 0001, Pavel Pudlák, Denis Thérien	Bounded-depth circuits: separating wires from gates.	STOC	2005	DBLP DOI BibTeX RDF	communication, complexity, lower bounds, regular languages, wires, constant-depth circuits, gates
62	Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu	Synthesis for multiple input wires replacement of a gate for wiring consideration.	ICCAD	1999	DBLP DOI BibTeX RDF
62	Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal	Logic emulation with virtual wires.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
55	Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi	Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect
55	Kenichi Shinkai, Masanori Hashimoto, Takao Onoye	Future Prediction of Self-Heating in Short Intra-Block Wires.	ISQED	2007	DBLP DOI BibTeX RDF
55	Ron Ho, Jonathan Gainsley, Robert J. Drost	Long Wires and Asynchronous Control.	ASYNC	2004	DBLP DOI BibTeX RDF
54	Avinoam Kolodny	Networks on chips: keeping up with Rent's rule and Moore's law.	SLIP	2007	DBLP DOI BibTeX RDF	routing, timing, interconnect, power, on-chip network, wires
53	Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz	Interconnect scaling implications for CAD.	ICCAD	1999	DBLP DOI BibTeX RDF
47	Sobeeh Almukhaizim, Yiorgos Makris	Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires.	IEEE Trans. Reliab.	2008	DBLP DOI BibTeX RDF
47	Po-Hao Chang, Jia-Ming Chen, Chao-Ying Shen	On an Efficient Closed Form Expression to Estimate the Crosstalk Noise in the Circuit with Multiple Wires.	APCCAS	2006	DBLP DOI BibTeX RDF
47	Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin	Datapath and control for quantum wires.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Architecture, Control, Layout
45	Yung-Chih Chen, Chun-Yao Wang	An Improved Approach for AlternativeWires Identi.cation.	ICCD	2005	DBLP DOI BibTeX RDF
45	Christian A. Duncan, Alon Efrat, Stephen G. Kobourov, Carola Wenk	Drawing with Fat Edges.	GD	2001	DBLP DOI BibTeX RDF
45	Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell	Topological channel routing [VLSI].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
41	Sandro Carrara, Cristina Boero, Giovanni De Micheli	Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing.	NanoNet	2009	DBLP DOI BibTeX RDF	Quantum Wires, Gold Nano-Particles, Oxidases, Cytochromes, Electrochemical detection, Carbon Nanotubes, Quantum Dots
40	Hitoshi Kino, Toshiaki Yahiro, Fumiaki Takemura, Tetsuya Morizono	Robust PD Control Using Adaptive Compensation for Completely Restrained Parallel-Wire Driven Robots: Translational Systems Using the Minimum Number of Wires Under Zero-Gravity Condition.	IEEE Trans. Robotics	2007	DBLP DOI BibTeX RDF
40	Hisashi Osumi, Masayuki Saitoh	Control of a Redundant Manipulator Mounted on a Base Plate Suspended by Six Wires.	IROS	2006	DBLP DOI BibTeX RDF
40	Hua Xiang 0001, I-Min Liu, Martin D. F. Wong	Wire Planning with Bounded Over-the-Block Wires.	ISQED	2005	DBLP DOI BibTeX RDF	over-the-block, wire planning, routing
40	Vijaya Ramachandran	On driving many long wires in a VLSI layout.	J. ACM	1986	DBLP DOI BibTeX RDF
39	Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato	Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity.	PDP	2008	DBLP DOI BibTeX RDF	SDM, Spatial Division Multiplexing, parallel links, Networks on chip, NoCs, Wiring, Wires
39	Charbel J. Akl, Magdy A. Bayoumi	Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	high-speed signaling, repeater, wires
38	Mackenzie R. Scott, Rajeevan Amirtharajah	Pulse width modulation for reduced peak power full-swing on-chip interconnect.	ISLPED	2009	DBLP DOI BibTeX RDF	low power interconnect, peak power, pulse width modulation
38	Eric Rachlin, John E. Savage	Analysis of Mask-Based Nanowire Decoders.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Hardware, Stochastic processes, Emerging technologies, Miscellaneous
38	Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra	Simultaneous Switching Noise: The Relation between Bus Layout and Coding.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques
38	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.	ISQED	2008	DBLP DOI BibTeX RDF	reliability, global routing, thermal
38	Eric Rachlin, John E. Savage, Benjamin Gojman	Analysis of a Mask-Based Nanowire Decoder.	ISVLSI	2005	DBLP DOI BibTeX RDF
38	Hao Yu 0001, Lei He 0001	Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction.	ISQED	2005	DBLP DOI BibTeX RDF
38	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Microarchitecture-aware floorplanning using a statistical design of experiments approach.	DAC	2005	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, wire pipelining
38	Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, Martin D. F. Wong, I-Min Liu	A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
38	Maurice Herlihy, Srikanta Tirthapura	Randomized Smoothing Networks.	IPDPS	2004	DBLP DOI BibTeX RDF
38	Maurice Herlihy, Srikanta Tirthapura	Self-Stabilizing Smoothing and Counting Maurice Herlihy, Srikanta Tirthapura.	ICDCS	2003	DBLP DOI BibTeX RDF
38	Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, D. F. Wong 0001, I-Min Liu	A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.	DATE	2002	DBLP DOI BibTeX RDF
38	Zhan Chen, Fook-Luen Heng	A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement.	DFT	1998	DBLP DOI BibTeX RDF	layout compaction, design for reliability, electromigration
36	Alexander Wires	Complexity in Young's lattice.	Ann. Pure Appl. Log.	2022	DBLP DOI BibTeX RDF
36	Jake Wires, Andrew Warfield	Mirador: An Active Control Plane for Datacenter Storage.	FAST	2017	DBLP BibTeX RDF
36	Mihir Nanavati, Jake Wires, Andrew Warfield	Decibel: Isolation and Sharing in Disaggregated Rack-Scale Storage.	NSDI	2017	DBLP BibTeX RDF
36	Jake Wires, Pradeep Ganesan, Andrew Warfield	Sketches of space: ownership accounting for shared storage.	SoCC	2017	DBLP DOI BibTeX RDF
36	Alexander Wires	On finite Taylor algebras.	Int. J. Algebra Comput.	2016	DBLP DOI BibTeX RDF
36	Mihir Nanavati, Malte Schwarzkopf, Jake Wires, Andrew Warfield	Non-volatile storage.	Commun. ACM	2016	DBLP DOI BibTeX RDF
36	Jake Wires, Stephen Ingram, Zachary Drudi, Nicholas J. A. Harvey, Andrew Warfield	Counter Stacks and the Elusive Working Set.	login Usenix Mag.	2015	DBLP BibTeX RDF
36	Alexander Wires	Dichotomy for finite tournaments of mixed-type.	Discret. Math.	2015	DBLP DOI BibTeX RDF
36	Mihir Nanavati, Malte Schwarzkopf, Jake Wires, Andrew Warfield	Non-volatile Storage.	ACM Queue	2015	DBLP DOI BibTeX RDF
36	Zachary Drudi, Nicholas J. A. Harvey, Stephen Ingram, Andrew Warfield, Jake Wires	Approximating Hit Rate Curves using Streaming Algorithms.	APPROX-RANDOM	2015	DBLP DOI BibTeX RDF
36	Brendan Cully, Jake Wires, Dutch T. Meyer, Kevin Jamieson 0002, Keir Fraser, Tim Deegan, Daniel Stodden, Geoffrey Lefebvre, Daniel Ferstay, Andrew Warfield	Strata: scalable high-performance storage on virtualized non-volatile memory.	FAST	2014	DBLP BibTeX RDF
36	Jake Wires, Stephen Ingram, Zachary Drudi, Nicholas J. A. Harvey, Andrew Warfield	Characterizing Storage Workloads with Counter Stacks.	OSDI	2014	DBLP BibTeX RDF
36	Dutch T. Meyer, Jake Wires, Norman C. Hutchinson, Andrew Warfield	Namespace Management in Virtual Desktops.	login Usenix Mag.	2011	DBLP BibTeX RDF
36	Mohammad Shamma, Dutch T. Meyer, Jake Wires, Maria Ivanova, Norman C. Hutchinson, Andrew Warfield	Capo: Recapitulating Storage for Virtual Desktops.	FAST	2011	DBLP BibTeX RDF
36	Jake Wires, Mark Spear, Andrew Warfield	Exposing File System Mappings with MapFS.	HotStorage	2011	DBLP BibTeX RDF
36	Jake Wires, Andrew Warfield	Beyond Blocks and Files.	login Usenix Mag.	2010	DBLP BibTeX RDF
36	Dutch T. Meyer, Mohammad Shamma, Jake Wires, Quan Zhang, Norman C. Hutchinson, Andrew Warfield	Fast and Cautious Evolution of Cloud Storage.	HotStorage	2010	DBLP BibTeX RDF
36	Dutch T. Meyer, Brendan Cully, Jake Wires, Norman C. Hutchinson, Andrew Warfield	Block Mason.	Workshop on I/O Virtualization	2008	DBLP BibTeX RDF
36	Jake Wires, Michael J. Feeley	Secure file system versioning at the block level.	EuroSys	2007	DBLP DOI BibTeX RDF
36	Kent E. Wires, Michael J. Schulte	Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	reciprocal square root, Newton-Raphson iteration, computer arithmetic, function approximation, table lookup, reciprocal
36	Mohammed S. Alam, Abhishek Gupta, Jake Wires, Son Thanh Vuong	APHIDS++: Evolution of A Programmable Hybrid Intrusion Detection System.	MATA	2005	DBLP DOI BibTeX RDF
36	Kent E. Wires, Michael J. Schulte, Don McCarley	FPGA Resource Reduction Through Truncated Multiplication.	FPL	2001	DBLP DOI BibTeX RDF
36	Kent E. Wires, Michael J. Schulte, James E. Stine	Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation.	ICCD	2001	DBLP DOI BibTeX RDF
36	Michael J. Schulte, Kent E. Wires	High-Speed Inverse Square Roots.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF	inverse square roots, truncated multiplication, squaring units, computer arithmetic, error analysis, VLSI design, Function approximation
34		Expression of Concern: Wang, C., Zhang, Q., Liu, W., Liu, Y. & Miao, L. Facial feature discovery for ethnicity recognition. WIREs Data Mining Knowl. Discov. 9 e1278 (2019).	WIREs Data Mining Knowl. Discov.	2020	DBLP DOI BibTeX RDF
34	Witold Pedrycz	Introducing WIREs data mining and knowledge discovery.	WIREs Data Mining Knowl. Discov.	2011	DBLP DOI BibTeX RDF
34	Thorben Casper, Ulrich Römer, Herbert De Gersem, Sebastian Schöps	Coupled simulation of transient heat flow and electric currents in thin wires: Application to bond wires in microelectronic chip packaging.	Comput. Math. Appl.	2020	DBLP DOI BibTeX RDF
34	Ilias Giechaskiel, Ken Eguro, Kasper Bonne Rasmussen	Leakier Wires: Exploiting FPGA Long Wires for Covert- and Side-channel Attacks.	ACM Trans. Reconfigurable Technol. Syst.	2019	DBLP DOI BibTeX RDF
34	Thorben Casper, Ulrich Römer, Sebastian Schöps, Herbert De Gersem	Coupled Simulation of Transient Heat Flow and Electric Currents in Thin Wires: Application to Bond Wires in Microelectronic Chip Packaging.	CoRR	2018	DBLP BibTeX RDF
34	Ilias Giechaskiel, Kasper Bonne Rasmussen, Ken Eguro	Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires.	AsiaCCS	2018	DBLP DOI BibTeX RDF
34	Andrew Adamatzky	Physarum wires: Self-growing self-repairing smart wires made from slime mould.	CoRR	2013	DBLP BibTeX RDF
34	Chih-Wei Jim Chang, Malgorzata Marek-Sadowska	Who are the alternative wires in your neighborhood? (alternative wires identification without search).	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
32	Seongmoo Heo, Krste Asanovic	Replacing global wires with an on-chip network: a power analysis.	ISLPED	2005	DBLP DOI BibTeX RDF	on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
32	Tang Li 0004, Lijin Fang, Hongguang Wang	Obstacle-navigation control for a mobile robot suspended on overhead ground wires.	ICARCV	2004	DBLP DOI BibTeX RDF
32	Ester M. Garzón, Siham Tabik, Amelia Rubio Bretones, Inmaculada García	Analysis of the Interaction of Electromagnetic Signals with Thin-Wires Structures. Multiprocessing Issues for an Iterative Method.	VECPAR	2004	DBLP DOI BibTeX RDF
32	Hua Xiang 0001, Kai-Yuan Chao, D. F. Wong 0001	ECO algorithms for removing overlaps between power rails and signal wires.	ICCAD	2002	DBLP DOI BibTeX RDF
32	Himanshu Kaul, Dennis Sylvester, David T. Blaauw	Active shields: a new approach to shielding global wires.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF
32	Shih-Chii Liu, John G. Harris	Dynamic wires: An alanog VLSI model for object-based processing.	Int. J. Comput. Vis.	1992	DBLP DOI BibTeX RDF
32	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen	Optimal Interconnect ATPG Under a Ground-Bounce Constraint.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	testing, interconnect, Hamming distance, wires, ground bounce
32	Ron Ho	High-performance ULSI: the real limiter to interconnect scaling.	SLIP	2005	DBLP DOI BibTeX RDF	VLSI, wireless, 3D, scaling, proximity, repeaters, wires
32	Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev	Low-latency asynchronous FIFO buffers.	ASYNC	1995	DBLP DOI BibTeX RDF	buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay
32	David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska	Circuit partitioning with logic perturbation.	ICCAD	1995	DBLP DOI BibTeX RDF	alternative wires, circuit partitioning
32	Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru	Lagrangian method for wire routing of layout design.	ANNES	1995	DBLP DOI BibTeX RDF	wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method
30	Rosemary M. Francis, Simon W. Moore	FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.	FPGA	2009	DBLP DOI BibTeX RDF	tdm wiring, fpga, routing
30	Rupesh S. Shelar	An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.	ISPD	2009	DBLP DOI BibTeX RDF	routing, power, clock distribution
30	Jin-Tai Yan, Zhi-Wei Chen	Redundant wire insertion for yield improvement.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	redundant wire, routing, yield
30	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Timing-aware power-optimal ordering of signals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Wire ordering, wire spacing, power optimization, interconnect optimization
30	Eduardo Luis Rhod, Luigi Carro	An efficient test and characterization approach for nanowire-based architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	nanoPLA, test, yield, characterization, nanowires
30	Shiyan Hu, Zhuo Li 0001, Charles J. Alpert	A polynomial time approximation scheme for timing constrained minimum cost layer assignment.	ICCAD	2008	DBLP DOI BibTeX RDF
30	Arpita Patra, Ashish Choudhary, Kannan Srinathan, C. Pandu Rangan	Perfectly Reliable and Secure Communication in Directed Networks Tolerating Mixed Adversary.	DISC	2007	DBLP DOI BibTeX RDF
30	Arpita Patra, Bhavani Shankar, Ashish Choudhary, K. Srinathan, C. Pandu Rangan	Perfectly Secure Message Transmission in Directed Networks Tolerating Threshold and Non Threshold Adversary.	CANS	2007	DBLP DOI BibTeX RDF	Reliable and Secure Communication, Information Theoretic Security, Directed Networks, Communication Efficiency
30	Maurice Herlihy, Srikanta Tirthapura	Self-stabilizing smoothing and balancing networks.	Distributed Comput.	2006	DBLP DOI BibTeX RDF	Smoothing networks, Self-stabilization, Counting networks
30	Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen	Optimal shielding insertion for inductive noise avoidance.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter	Interconnect-Aware Coherence Protocols for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
30	Krishnan Sundaresan, Nihar R. Mahapatra	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.	HPCA	2005	DBLP DOI BibTeX RDF
30	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Return path selection for loop RL extraction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
30	Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi	SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	SPFD, collaboration of logic and physical design, global rewiring (GR), one-to-many rewiring (OMR), logic optimization
30	K. Srinathan, Arvind Narayanan, C. Pandu Rangan	Optimal Perfectly Secure Message Transmission.	CRYPTO	2004	DBLP DOI BibTeX RDF
30	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Global interconnect trade-off for technology over memory modules to application level: case study.	SLIP	2003	DBLP DOI BibTeX RDF	Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
30	Paul Wielage, Kees Goossens	Networks on Silicon: Blessing or Nightmare?	DSD	2002	DBLP DOI BibTeX RDF
30	Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Optimising bandwidth over deep sub-micron interconnect.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
30	Mike Sheng, Jonathan Rose	Mixing buffers and pass transistors in FPGA routing architectures.	FPGA	2001	DBLP DOI BibTeX RDF
30	Phillip Christie, José Pineda de Gyvez	Pre-layout prediction of interconnect manufacturability.	SLIP	2001	DBLP DOI BibTeX RDF	design, reliability, interconnect, theory, yield, Rent's rule, critical areas
30	Yu-Liang Wu, Wangning Long, Hongbing Fan	A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks.	VLSI Design	2000	DBLP DOI BibTeX RDF	Alternative wiring, Graph-based pattern matching, Logic synthesis