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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 954 occurrences of 591 keywords
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Results
Found 1954 publication records. Showing 1951 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
86 | Valeriu Beiu, Walid Ibrahim, Rafic Z. Makki |
On Wires Holding a Handful of Electrons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 259-269, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Nano-electronics, interconnects (wires), noise (intrinsic), reliability, communication |
77 | Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska |
Postlayout logic restructuring using alternative wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6), pp. 587-596, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
70 | Saroj K. Nayak |
Carbon nanotube, graphene and atomic wires as next generation interconnects: current status and future promise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 109-110, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
quantum simulation, performance, design, reliability |
64 | Michal Koucký 0001, Pavel Pudlák, Denis Thérien |
Bounded-depth circuits: separating wires from gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 37th Annual ACM Symposium on Theory of Computing, Baltimore, MD, USA, May 22-24, 2005, pp. 257-265, 2005, ACM, 1-58113-960-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
communication, complexity, lower bounds, regular languages, wires, constant-depth circuits, gates |
62 | Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu |
Synthesis for multiple input wires replacement of a gate for wiring consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 115-119, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
62 | Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal |
Logic emulation with virtual wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6), pp. 609-626, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
55 | Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi |
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(1), pp. 57-76, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect |
55 | Kenichi Shinkai, Masanori Hashimoto, Takao Onoye |
Future Prediction of Self-Heating in Short Intra-Block Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 660-665, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Ron Ho, Jonathan Gainsley, Robert J. Drost |
Long Wires and Asynchronous Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 240-249, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Avinoam Kolodny |
Networks on chips: keeping up with Rent's rule and Moore's law. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 55-56, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
routing, timing, interconnect, power, on-chip network, wires |
53 | Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz |
Interconnect scaling implications for CAD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 425-429, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
47 | Sobeeh Almukhaizim, Yiorgos Makris |
Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 57(1), pp. 23-31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Po-Hao Chang, Jia-Ming Chen, Chao-Ying Shen |
On an Efficient Closed Form Expression to Estimate the Crosstalk Noise in the Circuit with Multiple Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1329-1332, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin |
Datapath and control for quantum wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(1), pp. 34-61, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Architecture, Control, Layout |
45 | Yung-Chih Chen, Chun-Yao Wang |
An Improved Approach for AlternativeWires Identi.cation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 711-716, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Christian A. Duncan, Alon Efrat, Stephen G. Kobourov, Carola Wenk |
Drawing with Fat Edges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 9th International Symposium, GD 2001 Vienna, Austria, September 23-26, 2001, Revised Papers, pp. 162-177, 2001, Springer, 3-540-43309-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell |
Topological channel routing [VLSI]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10), pp. 1177-1197, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
41 | Sandro Carrara, Cristina Boero, Giovanni De Micheli |
Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 189-199, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Quantum Wires, Gold Nano-Particles, Oxidases, Cytochromes, Electrochemical detection, Carbon Nanotubes, Quantum Dots |
40 | Hitoshi Kino, Toshiaki Yahiro, Fumiaki Takemura, Tetsuya Morizono |
Robust PD Control Using Adaptive Compensation for Completely Restrained Parallel-Wire Driven Robots: Translational Systems Using the Minimum Number of Wires Under Zero-Gravity Condition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Robotics ![In: IEEE Trans. Robotics 23(4), pp. 803-812, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Hisashi Osumi, Masayuki Saitoh |
Control of a Redundant Manipulator Mounted on a Base Plate Suspended by Six Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2006, October 9-15, 2006, Beijing, China, pp. 73-78, 2006, IEEE, 1-4244-0258-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Hua Xiang 0001, I-Min Liu, Martin D. F. Wong |
Wire Planning with Bounded Over-the-Block Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 622-627, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
over-the-block, wire planning, routing |
40 | Vijaya Ramachandran |
On driving many long wires in a VLSI layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 33(4), pp. 687-701, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
39 | Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato |
Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 20-29, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SDM, Spatial Division Multiplexing, parallel links, Networks on chip, NoCs, Wiring, Wires |
39 | Charbel J. Akl, Magdy A. Bayoumi |
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 327-332, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
high-speed signaling, repeater, wires |
38 | Mackenzie R. Scott, Rajeevan Amirtharajah |
Pulse width modulation for reduced peak power full-swing on-chip interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 213-218, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power interconnect, peak power, pulse width modulation |
38 | Eric Rachlin, John E. Savage |
Analysis of Mask-Based Nanowire Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(2), pp. 175-187, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hardware, Stochastic processes, Emerging technologies, Miscellaneous |
38 | Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra |
Simultaneous Switching Noise: The Relation between Bus Layout and Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 76-86, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques |
38 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 470-475, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reliability, global routing, thermal |
38 | Eric Rachlin, John E. Savage, Benjamin Gojman |
Analysis of a Mask-Based Nanowire Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 6-13, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Hao Yu 0001, Lei He 0001 |
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 682-687, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
Microarchitecture-aware floorplanning using a statistical design of experiments approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 579-584, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, wire pipelining |
38 | Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, Martin D. F. Wong, I-Min Liu |
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 141-147, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Maurice Herlihy, Srikanta Tirthapura |
Randomized Smoothing Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Maurice Herlihy, Srikanta Tirthapura |
Self-Stabilizing Smoothing and Counting Maurice Herlihy, Srikanta Tirthapura. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 23rd International Conference on Distributed Computing Systems (ICDCS 2003), 19-22 May 2003, Providence, RI, USA, pp. 4-11, 2003, IEEE Computer Society, 0-7695-1920-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, D. F. Wong 0001, I-Min Liu |
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 470-475, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Zhan Chen, Fook-Luen Heng |
A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 56-63, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
layout compaction, design for reliability, electromigration |
36 | Alexander Wires |
Complexity in Young's lattice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Pure Appl. Log. ![In: Ann. Pure Appl. Log. 173(4), pp. 103075, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
36 | Jake Wires, Andrew Warfield |
Mirador: An Active Control Plane for Datacenter Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FAST ![In: 15th USENIX Conference on File and Storage Technologies, FAST 2017, Santa Clara, CA, USA, February 27 - March 2, 2017, pp. 213-228, 2017, USENIX Association, 978-1-931971-36-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
36 | Mihir Nanavati, Jake Wires, Andrew Warfield |
Decibel: Isolation and Sharing in Disaggregated Rack-Scale Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NSDI ![In: 14th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2017, Boston, MA, USA, March 27-29, 2017, pp. 17-33, 2017, USENIX Association, 978-1-931971-37-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
36 | Jake Wires, Pradeep Ganesan, Andrew Warfield |
Sketches of space: ownership accounting for shared storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Proceedings of the 2017 Symposium on Cloud Computing, SoCC 2017, Santa Clara, CA, USA, September 24-27, 2017, pp. 535-547, 2017, ACM, 978-1-4503-5028-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
36 | Alexander Wires |
On finite Taylor algebras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Algebra Comput. ![In: Int. J. Algebra Comput. 26(8), pp. 1547-1571, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
36 | Mihir Nanavati, Malte Schwarzkopf, Jake Wires, Andrew Warfield |
Non-volatile storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 59(1), pp. 56-63, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
36 | Jake Wires, Stephen Ingram, Zachary Drudi, Nicholas J. A. Harvey, Andrew Warfield |
Counter Stacks and the Elusive Working Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
login Usenix Mag. ![In: login Usenix Mag. 40(1), 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
36 | Alexander Wires |
Dichotomy for finite tournaments of mixed-type. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Math. ![In: Discret. Math. 338(12), pp. 2523-2538, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Mihir Nanavati, Malte Schwarzkopf, Jake Wires, Andrew Warfield |
Non-volatile Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Queue ![In: ACM Queue 13(9), pp. 20, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Zachary Drudi, Nicholas J. A. Harvey, Stephen Ingram, Andrew Warfield, Jake Wires |
Approximating Hit Rate Curves using Streaming Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques, APPROX/RANDOM 2015, August 24-26, 2015, Princeton, NJ, USA, pp. 225-241, 2015, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-939897-89-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Brendan Cully, Jake Wires, Dutch T. Meyer, Kevin Jamieson 0002, Keir Fraser, Tim Deegan, Daniel Stodden, Geoffrey Lefebvre, Daniel Ferstay, Andrew Warfield |
Strata: scalable high-performance storage on virtualized non-volatile memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FAST ![In: Proceedings of the 12th USENIX conference on File and Storage Technologies, FAST 2014, Santa Clara, CA, USA, February 17-20, 2014, pp. 17-31, 2014, USENIX, 978-1-931971-08-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
36 | Jake Wires, Stephen Ingram, Zachary Drudi, Nicholas J. A. Harvey, Andrew Warfield |
Characterizing Storage Workloads with Counter Stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OSDI ![In: 11th USENIX Symposium on Operating Systems Design and Implementation, OSDI '14, Broomfield, CO, USA, October 6-8, 2014., pp. 335-349, 2014, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
36 | Dutch T. Meyer, Jake Wires, Norman C. Hutchinson, Andrew Warfield |
Namespace Management in Virtual Desktops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
login Usenix Mag. ![In: login Usenix Mag. 36(1), 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
36 | Mohammad Shamma, Dutch T. Meyer, Jake Wires, Maria Ivanova, Norman C. Hutchinson, Andrew Warfield |
Capo: Recapitulating Storage for Virtual Desktops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FAST ![In: 9th USENIX Conference on File and Storage Technologies, San Jose, CA, USA, February 15-17, 2011, pp. 31-45, 2011, USENIX, 978-1-931971-82-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
36 | Jake Wires, Mark Spear, Andrew Warfield |
Exposing File System Mappings with MapFS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HotStorage ![In: 3rd USENIX Workshop on Hot Topics in Storage and File Systems, HotStorage'11, Portland, OR, USA, June 14, 2011, 2011, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
36 | Jake Wires, Andrew Warfield |
Beyond Blocks and Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
login Usenix Mag. ![In: login Usenix Mag. 35(2), 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
36 | Dutch T. Meyer, Mohammad Shamma, Jake Wires, Quan Zhang, Norman C. Hutchinson, Andrew Warfield |
Fast and Cautious Evolution of Cloud Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HotStorage ![In: 2nd USENIX Workshop on Hot Topics in Storage and File Systems, HotStorage'10, Boston, MA, USA, June 22, 2010, 2010, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
36 | Dutch T. Meyer, Brendan Cully, Jake Wires, Norman C. Hutchinson, Andrew Warfield |
Block Mason. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on I/O Virtualization ![In: First Workshop on I/O Virtualization, WIOV'08, San Diego, CA, USA, December 10-11, 2008, Proceedings, 2008, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
36 | Jake Wires, Michael J. Feeley |
Secure file system versioning at the block level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, pp. 203-215, 2007, ACM, 978-1-59593-636-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Kent E. Wires, Michael J. Schulte |
Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(3), pp. 257-272, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reciprocal square root, Newton-Raphson iteration, computer arithmetic, function approximation, table lookup, reciprocal |
36 | Mohammed S. Alam, Abhishek Gupta, Jake Wires, Son Thanh Vuong |
APHIDS++: Evolution of A Programmable Hybrid Intrusion Detection System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MATA ![In: Mobility Aware Technologies and Applications, Second International Workshop, MATA 2005, Montreal, Canada, October 17-19, 2005, Proceedings, pp. 22-31, 2005, Springer, 3-540-29410-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Kent E. Wires, Michael J. Schulte, Don McCarley |
FPGA Resource Reduction Through Truncated Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 574-583, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Kent E. Wires, Michael J. Schulte, James E. Stine |
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 497-500, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
36 | Michael J. Schulte, Kent E. Wires |
High-Speed Inverse Square Roots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 124-, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
inverse square roots, truncated multiplication, squaring units, computer arithmetic, error analysis, VLSI design, Function approximation |
34 | |
Expression of Concern: Wang, C., Zhang, Q., Liu, W., Liu, Y. & Miao, L. Facial feature discovery for ethnicity recognition. WIREs Data Mining Knowl. Discov. 9 e1278 (2019). ![Search on Bibsonomy](Pics/bibsonomy.png) |
WIREs Data Mining Knowl. Discov. ![In: WIREs Data Mining Knowl. Discov. 10(6), pp. 9, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Witold Pedrycz |
Introducing WIREs data mining and knowledge discovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WIREs Data Mining Knowl. Discov. ![In: WIREs Data Mining Knowl. Discov. 1(1), pp. 1, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
34 | Thorben Casper, Ulrich Römer, Herbert De Gersem, Sebastian Schöps |
Coupled simulation of transient heat flow and electric currents in thin wires: Application to bond wires in microelectronic chip packaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Math. Appl. ![In: Comput. Math. Appl. 79(6), pp. 1781-1801, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
34 | Ilias Giechaskiel, Ken Eguro, Kasper Bonne Rasmussen |
Leakier Wires: Exploiting FPGA Long Wires for Covert- and Side-channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 12(3), pp. 11:1-11:29, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
34 | Thorben Casper, Ulrich Römer, Sebastian Schöps, Herbert De Gersem |
Coupled Simulation of Transient Heat Flow and Electric Currents in Thin Wires: Application to Bond Wires in Microelectronic Chip Packaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1809.09034, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
34 | Ilias Giechaskiel, Kasper Bonne Rasmussen, Ken Eguro |
Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaCCS ![In: Proceedings of the 2018 on Asia Conference on Computer and Communications Security, AsiaCCS 2018, Incheon, Republic of Korea, June 04-08, 2018, pp. 15-27, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
34 | Andrew Adamatzky |
Physarum wires: Self-growing self-repairing smart wires made from slime mould. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1309.3583, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
34 | Chih-Wei Jim Chang, Malgorzata Marek-Sadowska |
Who are the alternative wires in your neighborhood? (alternative wires identification without search). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 103-108, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Seongmoo Heo, Krste Asanovic |
Replacing global wires with an on-chip network: a power analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 369-374, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture |
32 | Tang Li 0004, Lijin Fang, Hongguang Wang |
Obstacle-navigation control for a mobile robot suspended on overhead ground wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: 8th International Conference on Control, Automation, Robotics and Vision, ICARCV 2004, Kunming, China, 6-9 December 2004, Proceedings, pp. 2082-2087, 2004, IEEE, 0-7803-8653-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Ester M. Garzón, Siham Tabik, Amelia Rubio Bretones, Inmaculada García |
Analysis of the Interaction of Electromagnetic Signals with Thin-Wires Structures. Multiprocessing Issues for an Iterative Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2004, 6th International Conference, Valencia, Spain, June 28-30, 2004, Revised Selected and Invited Papers, pp. 78-89, 2004, Springer, 3-540-25424-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Hua Xiang 0001, Kai-Yuan Chao, D. F. Wong 0001 |
ECO algorithms for removing overlaps between power rails and signal wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 67-74, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Himanshu Kaul, Dennis Sylvester, David T. Blaauw |
Active shields: a new approach to shielding global wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 112-117, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Shih-Chii Liu, John G. Harris |
Dynamic wires: An alanog VLSI model for object-based processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 8(3), pp. 231-239, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
32 | Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen |
Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 17-31, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
testing, interconnect, Hamming distance, wires, ground bounce |
32 | Ron Ho |
High-performance ULSI: the real limiter to interconnect scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 3, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, wireless, 3D, scaling, proximity, repeaters, wires |
32 | Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev |
Low-latency asynchronous FIFO buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 24-31, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay |
32 | David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska |
Circuit partitioning with logic perturbation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 650-655, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
alternative wires, circuit partitioning |
32 | Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru |
Lagrangian method for wire routing of layout design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANNES ![In: 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), November 20-23, 1995, Dunedin, New Zealand, pp. 350-354, 1995, IEEE Computer Society, 0-8186-7174-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method |
30 | Rosemary M. Francis, Simon W. Moore |
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 285, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
tdm wiring, fpga, routing |
30 | Rupesh S. Shelar |
An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 141-148, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
routing, power, clock distribution |
30 | Jin-Tai Yan, Zhi-Wei Chen |
Redundant wire insertion for yield improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 409-412, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
redundant wire, routing, yield |
30 | Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer |
Timing-aware power-optimal ordering of signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 65:1-65:17, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Wire ordering, wire spacing, power optimization, interconnect optimization |
30 | Eduardo Luis Rhod, Luigi Carro |
An efficient test and characterization approach for nanowire-based architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 34-39, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
nanoPLA, test, yield, characterization, nanowires |
30 | Shiyan Hu, Zhuo Li 0001, Charles J. Alpert |
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 112-115, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Arpita Patra, Ashish Choudhary, Kannan Srinathan, C. Pandu Rangan |
Perfectly Reliable and Secure Communication in Directed Networks Tolerating Mixed Adversary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 21st International Symposium, DISC 2007, Lemesos, Cyprus, September 24-26, 2007, Proceedings, pp. 496-498, 2007, Springer, 978-3-540-75141-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Arpita Patra, Bhavani Shankar, Ashish Choudhary, K. Srinathan, C. Pandu Rangan |
Perfectly Secure Message Transmission in Directed Networks Tolerating Threshold and Non Threshold Adversary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANS ![In: Cryptology and Network Security, 6th International Conference, CANS 2007, Singapore, December 8-10, 2007, Proceedings, pp. 80-101, 2007, Springer, 978-3-540-76968-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Reliable and Secure Communication, Information Theoretic Security, Directed Networks, Communication Efficiency |
30 | Maurice Herlihy, Srikanta Tirthapura |
Self-stabilizing smoothing and balancing networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 18(5), pp. 345-357, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Smoothing networks, Self-stabilization, Counting networks |
30 | Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen |
Optimal shielding insertion for inductive noise avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter |
Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA, pp. 339-351, 2006, IEEE Computer Society, 0-7695-2608-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Krishnan Sundaresan, Nihar R. Mahapatra |
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 51-60, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
Return path selection for loop RL extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1078-1081, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi |
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 348-353, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SPFD, collaboration of logic and physical design, global rewiring (GR), one-to-many rewiring (OMR), logic optimization |
30 | K. Srinathan, Arvind Narayanan, C. Pandu Rangan |
Optimal Perfectly Secure Message Transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO 2004, 24th Annual International CryptologyConference, Santa Barbara, California, USA, August 15-19, 2004, Proceedings, pp. 545-561, 2004, Springer, 3-540-22668-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex |
Global interconnect trade-off for technology over memory modules to application level: case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 125-132, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect |
30 | Paul Wielage, Kees Goossens |
Networks on Silicon: Blessing or Nightmare? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 196-200, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Optimising bandwidth over deep sub-micron interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 193-196, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Mike Sheng, Jonathan Rose |
Mixing buffers and pass transistors in FPGA routing architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 75-84, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Phillip Christie, José Pineda de Gyvez |
Pre-layout prediction of interconnect manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 167-173, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
design, reliability, interconnect, theory, yield, Rent's rule, critical areas |
30 | Yu-Liang Wu, Wangning Long, Hongbing Fan |
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 268-273, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Alternative wiring, Graph-based pattern matching, Logic synthesis |
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