|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 139 occurrences of 109 keywords
|
|
|
Results
Found 401 publication records. Showing 401 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Benton H. Calhoun, Jonathan F. Bolus, Sudhanshu Khanna, Andrew D. Jurik, Alfred C. Weaver, Travis N. Blalock |
Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 1437-1440, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Matthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Hannu Tenhunen, Lauri Koskinen |
Adaptive Sub-Threshold Test Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009, San Francisco, California, USA, July 29 - August 1, 2009, pp. 197-203, 2009, IEEE Computer Society, 978-0-7695-3714-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Chi-Ying Tsui, Robert Yi-Ching Au, Ricky Yiu-kee Choi |
Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 41(1), pp. 76-86, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jonggab Kil, Jie Gu 0003, Chris H. Kim |
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 456-465, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Sona P. Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta, R. S. Gupta |
Performance assessment and sub-threshold analysis of gate material engineered AlGaN/GaN HEMT for enhanced carrier transport efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 39(12), pp. 1416-1424, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Omer Can Akgun, Yusuf Leblebici |
Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 4(3), pp. 320-336, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Hyunju Ham, Toshimasa Matsuoka, Kenji Taniguchi 0001 |
Sub-threshold signal detection using noise statistics for communications applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 1167-1170, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | David T. Blaauw, James Kitchener, Braden Phillips |
Optimizing addition for sub-threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: 42nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2008, Pacific Grove, CA, USA, October 26-29, 2008, pp. 751-756, 2008, IEEE, 978-1-4244-2940-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy 0001 |
A high sensitivity process variation sensor utilizing sub-threshold operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008, pp. 125-128, 2008, IEEE, 978-1-4244-2018-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Niklas Lotze, Maurits Ortmanns, Yiannos Manoli |
Variability of flip-flop timing at sub-threshold voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, pp. 221-224, 2008, ACM, 978-1-60558-109-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Syed Imtiaz Haider, Leyla Nazhandali |
Utilizing sub-threshold technology for the creation of secure circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3182-3185, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao |
65NM sub-threshold 11T-SRAM for ultra low voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 113-118, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Benton H. Calhoun, Anantha P. Chandrakasan |
A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(3), pp. 680-688, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yoshioki Isobe, Kiyohito Hara, Dondee Navarro, Youichi Takeda, Tatsuya Ezaki, Mitiko Miura-Mattausch |
Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 90-C(4), pp. 885-894, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Hui Shao, Chi-Ying Tsui |
A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007, pp. 312-315, 2007, IEEE, 978-1-4244-1125-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Bo Zhai |
Ultra-low power processor design using sub-threshold design techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
RDF |
|
15 | Benton H. Calhoun, Anantha P. Chandrakasan |
Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(7), pp. 1673-1679, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Benton H. Calhoun, Anantha P. Chandrakasan |
Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(1), pp. 238-245, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Nikolaos P. Papadopoulos, Alkis A. Hatzopoulos, Dimitris K. Papakostas, C. A. Dimitriadis, Stilianos Siskos |
Modeling the impact of light on the performance of polycrystalline thin-film transistors at the sub-threshold region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 37(11), pp. 1313-1320, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Alice Wang, Benton H. Calhoun, Anantha P. Chandrakasan |
Sub-threshold Design for Ultra Low-Power Systems ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
DOI RDF |
|
15 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 995-1000, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Vivienne Sze, Raúl Blázquez, Manish Bhardwaj, Anantha P. Chandrakasan |
An Energy Efficient Sub-Threshold Baseband Processor Architecture for Pulsed Ultra-Wideband Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (3) ![In: 2006 IEEE International Conference on Acoustics Speech and Signal Processing, ICASSP 2006, Toulouse, France, May 14-19, 2006, pp. 908-911, 2006, IEEE, 1-4244-0469-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Minato Kawaguchi, Hiroyuki Mino, Dominique M. Durand |
Information Transmission in Hippocampal CA1 Neuron Models in the Presence of Poisson Shot Noise: the Case of Periodic Sub-threshold Spike Trains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMBC ![In: 28th International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2006, New York City, NY, USA, August 30 - September 3, 2006, Main Volume, pp. 4196-4199, 2006, IEEE, 1-4244-0032-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Benton H. Calhoun, Anantha P. Chandrakasan |
A 256kb Sub-threshold SRAM in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 2592-2601, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Benton H. Calhoun, Anantha P. Chandrakasan |
Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005, pp. 363-366, 2005, IEEE, 0-7803-9205-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Carlos Aguirre, Doris Campos, Pedro Pascual, Eduardo Serrano |
Neuronal Behavior with Sub-threshold Oscillations and Spiking/Bursting Activity Using a Piecewise Linear Two-Dimensional Map. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (1) ![In: Artificial Neural Networks: Biological Inspirations - ICANN 2005, 15th International Conference, Warsaw, Poland, September 11-15, 2005, Proceedings, Part I, pp. 103-108, 2005, Springer, 3-540-28752-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Benton H. Calhoun |
Low energy digital circuit design using sub-threshold operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2005 |
RDF |
|
15 | Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown |
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, pp. 313-316, 2003, IEEE, 0-7803-7995-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Gregor Wenning, Klaus Obermayer |
Adjusting stochastic resonance in a leaky integrate and fire neuron to sub-threshold stimulus distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neurocomputing ![In: Neurocomputing 44-46, pp. 225-231, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Frank Sill, Frank Grassert, Dirk Timmermann |
Total leakage power optimization with improved mixed gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 154-159, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
MVT, leakage currents, threshold voltage |
14 | Nikolay N. Elkin, Anatoly P. Napartovich, Alexander G. Sukharev, Dmitri V. Vysotsky |
3D Modelling of Diode Laser Active Cavity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAA ![In: Numerical Analysis and Its Applications, Third International Conference, NAA 2004, Rousse, Bulgaria, June 29 - July 3, 2004, Revised Selected Papers, pp. 272-279, 2004, Springer, 3-540-24937-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Xin Fu, Tao Li, José A. B. Fortes |
Soft error vulnerability aware process variation mitigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 93-104, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Enno de Lange, Martin Hasler |
Predicting single spikes and spike patterns with the Hindmarsh-Rose model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biol. Cybern. ![In: Biol. Cybern. 99(4-5), pp. 349-360, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hindmarsh-Rose model, Parameter fitting, Quantitative neuron modeling, Spike-timing, Neocortical neurons, Nonlinear optimization, Nonlinear dynamics, Bifurcation analysis |
14 | Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu |
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 583-588, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy 0001 |
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 583-586, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Youngbok Kim, Anuj Agarwal, Sameer R. Sonkusale |
Low power current mode ADC for CMOS sensor IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 584-587, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Ashutosh S. Dhodapkar, James E. Smith 0001 |
Tuning Reconfigurable Microarchitectures for Power Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Manoj Sachdev |
Deep sub-micron IDDQ testing: issues and solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 271-278, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | Saihua Lin, Yu Wang 0002, Rong Luo, Huazhong Yang |
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 304-309, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon |
Integrated circuit design with NEM relays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 750-757, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur |
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 509-514, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Juan Gao, Philip Holmes |
On the dynamics of electrically-coupled neurons with inhibitory synapses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Neurosci. ![In: J. Comput. Neurosci. 22(1), pp. 39-61, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Bifurcation diagrams, Electrical coupling, Inhibitory synapses, Integrate-and-fire models, Poincaré maps |
11 | Rodrigo Jaramillo-Ramirez, Mohab Anis |
A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3724-3727, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Chanseok Hwang, Peng Rong, Massoud Pedram |
Sleep transistor distribution in row-based MTCMOS designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 235-240, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
leakage minimization, placement, MTCMOS |
11 | Jing Li 0073, Kunhyuk Kang, Aditya Bansal, Kaushik Roy 0001 |
High Performance and Low Power Electronics on Flexible Substrate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 274-275, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija |
Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 148-156, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Chanseok Hwang, Chang Woo Kang, Massoud Pedram |
Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 741-746, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Srivathsan Krishnamohan, Nihar R. Mahapatra |
Increasing the energy efficiency of pipelined circuits via slack redistribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 436-441, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
slack passing, time borrowing, low-power design |
11 | H. C. Srinivasaiah, Navakanta Bhat |
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 285-290, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Disposable spacer, Transmission of moments technique, Plackett-Burman design, Sensitivity analysis, Statistical modeling, CMOS technology, Response surface methodology, Monte carlo analysis |
11 | Rohini Krishnan, José Pineda de Gyvez |
Low Energy Switch Block For FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 209-214, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Narender Hanchate, Nagarajan Ranganathan |
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 228-233, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Sagar S. Sabade, D. M. H. Walker |
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 755-760, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Stephen P. Kornachuk, Michael C. Smayling |
New strategies for gridded physical design for 32nm technologies and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 61-62, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm |
10 | Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie 0001, Mary Jane Irwin, Osama Awadel Karim |
A low-power phase change memory based hybrid cache architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 395-398, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
PRAM, phase change memory |
10 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 177-182, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
10 | Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta |
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 183-188, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | A. K. Mrunal, M. A. Shirasgaonkar, Rajendra M. Patrikar |
Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1488-1491, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Sagar S. Sabade, D. M. H. Walker |
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 81-86, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal |
Xetal-Pro: an ultra-low energy and high throughput SIMD processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 543-548, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Xetal-Pro, hybrid memory system, SIMD, low-energy |
7 | Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta |
Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 200-209, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-energy circuits, single electron transistors, binary decision diagram logic circuits |
7 | Jader A. De Lima |
A compact low-distortion low-power instrumentation amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
class-AB output stage, double-port amplifier, instrumentation amplifier |
7 | Hongbo Zhou 0001, Hong-Ju Yang, Haiyun Xu, Qiang Cheng |
A New Computational Tool for the Post Session Analysis of the Prepulse Inhibition Test in Neural Science. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 1077-1080, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
7 | Basab Datta, Wayne P. Burleson |
Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 145-148, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sensor, interconnect, temperature, oscillator |
7 | Kuande Wang, Li Chen, Jinsheng Yang |
AN ultra low power fault tolerant SRAM design in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 1076-1079, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
7 | S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya |
100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 105-110, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
7 | QuanJun Cao, Yimen Zhang, Yuming Zhang, HongLiang Lv, YueHu Wang, XiaoYan Tang, Hui Guo |
Improved empirical DC I-V model for 4H-SiC MESFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(8), pp. 1184-1192, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
4H-SiC MESFET, DC I-V characteristics, nonlinear regression, empirical model, Levenberg-Marquardt method |
7 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 42-51, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
7 | Ming Liu 0015, Hong Chen 0002, Run Chen, Zhihua Wang 0001 |
Low-power IC design for a wireless BCI system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1560-1563, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
7 | Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer |
Improving the power-delay product in SCL circuits using source follower output stage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 145-148, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
7 | Betty Prince |
Nanotechnology and emerging memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 4, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory |
7 | Siddharth Garg, Diana Marculescu |
On the impact of manufacturing process variations on the lifetime of sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 203-208, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
leakage power variability, manufacturing process variations, sensor networks, lifetime |
7 | Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud |
A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2351-2354, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu |
A Study on Impact of Leakage Current on Dynamic Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1069-1072, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien |
New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3740-3743, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Tamer Cakici, Keejong Kim, Kaushik Roy 0001 |
FinFET Based SRAM Design for Low Standby Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 127-132, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Ashesh Rastogi, Wei Chen, Sandip Kundu |
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 712-715, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud |
A nanowatt ADC for ultra low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Srinjoy Mitra, Stefano Fusi, Giacomo Indiveri |
A VLSI spike-driven dynamic synapse which learns only when necessary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | K. Kiyoyama, Yoshinobu Tanaka, Michihisa Onoda |
A low current consumption delta-sigma modulator for body-implanted chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Sanjeev K. Jain, Pankaj Agarwal |
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 495-498, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Shan Gao, Junning Chen, Daoming Ke, Xiulong Wu |
A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1465-1468, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy 0001 |
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 971-976, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive source biasing, hold failures, low power SRAM |
7 | Alice Morelli, Rosapia Lauro Grotto, Fortunato Tito Arecchi |
A Feature-Based Model of Semantic Memory: The Importance of Being Chaotic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BVAI ![In: Brain, Vision, and Artificial Intelligence, First International Symposium, BVAI 2005, Naples, Italy, October 19-21, 2005, Proceedings, pp. 328-337, 2005, Springer, 3-540-29282-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001 |
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 8-13, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage |
7 | Leila Shepherd, Chris Toumazou |
Towards an implantable ultra-low power biochemical signal processor for blood and tissue monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5226-5229, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | M. Kiyoyama, Michihisa Onoda, Yoshinobu Tanaka |
A low current consumption CMOS latched comparator for body-implanted chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1940-1943, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | R. Srinivasan, Navakanta Bhat |
Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 392-396, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri |
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 43-46, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
leakage power, self-adjusting, body-biasing |
7 | Fredrik Edin, Christian K. Machens, Hartmut Schütze, Andreas V. M. Herz |
Searching for Optimal Sensory Signals: Iterative Stimulus Reconstruction in Closed-Loop Experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Neurosci. ![In: J. Comput. Neurosci. 17(1), pp. 47-56, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
stimulus reconstruction, insect, auditory receptor, neural coding |
7 | Mahadevan Gomathisankaran, Akhilesh Tyagi |
WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 105-114, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Hari Ananthan, Aditya Bansal, Kaushik Roy 0001 |
FinFET SRAM - Device and Circuit Design Considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 511-516, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Kaviraj Chopra, Sarma B. K. Vrudhula |
Implicit pseudo boolean enumeration algorithms for input vector control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 767-772, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods |
7 | Cassondra Neau, Kaushik Roy 0001 |
Optimal body bias selection for leakage improvement and process compensation over different technology generations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 116-121, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias |
7 | Saied Hemati, Amir H. Banihashemi |
Iterative decoding in analog CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 15-20, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
analog CMOS, analog iterative decoder, asynchronous iterative decoding, min-sum decoding, soft decoding, analog circuit, turbo codes, iterative decoding, low-density parity-check codes |
7 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni |
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 100-105, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Giancarlo La Camera, Stefano Fusi, Walter Senn, Alexander Rauch, Hans-Rudolf Lüscher |
When NMDA Receptor Conductances Increase Inter-spike Interval Variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN ![In: Artificial Neural Networks - ICANN 2002, International Conference, Madrid, Spain, August 28-30, 2002, Proceedings, pp. 235-240, 2002, Springer, 3-540-44074-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Anton Chichkov, Dirk Merlier, Peter Cox |
Current Testing Procedure for Deep Submicron Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 219-224, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ASIC testing, IDDQ, deep submicron |
7 | Juan M. Díez, Juan Carlos López 0001 |
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 645-649, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
7 | Claude Thibeault, Luc Boisvert |
On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 202-210, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
current signatures, diagnosis, Integrated circuits, bridging faults, Iddq testing |
Displaying result #301 - #400 of 401 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ >>] |
|