Search results for "sub-threshold"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Benton H. Calhoun, Jonathan F. Bolus, Sudhanshu Khanna, Andrew D. Jurik, Alfred C. Weaver, Travis N. Blalock	Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Matthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Hannu Tenhunen, Lauri Koskinen	Adaptive Sub-Threshold Test Circuit.	AHS	2009	DBLP DOI BibTeX RDF
15	Chi-Ying Tsui, Robert Yi-Ching Au, Ricky Yiu-kee Choi	Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping.	Integr.	2008	DBLP DOI BibTeX RDF
15	Jonggab Kil, Jie Gu 0003, Chris H. Kim	A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Sona P. Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta, R. S. Gupta	Performance assessment and sub-threshold analysis of gate material engineered AlGaN/GaN HEMT for enhanced carrier transport efficiency.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
15	Omer Can Akgun, Yusuf Leblebici	Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime.	J. Low Power Electron.	2008	DBLP DOI BibTeX RDF
15	Hyunju Ham, Toshimasa Matsuoka, Kenji Taniguchi 0001	Sub-threshold signal detection using noise statistics for communications applications.	ICECS	2008	DBLP DOI BibTeX RDF
15	David T. Blaauw, James Kitchener, Braden Phillips	Optimizing addition for sub-threshold logic.	ACSCC	2008	DBLP DOI BibTeX RDF
15	Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy 0001	A high sensitivity process variation sensor utilizing sub-threshold operation.	CICC	2008	DBLP DOI BibTeX RDF
15	Niklas Lotze, Maurits Ortmanns, Yiannos Manoli	Variability of flip-flop timing at sub-threshold voltages.	ISLPED	2008	DBLP DOI BibTeX RDF
15	Syed Imtiaz Haider, Leyla Nazhandali	Utilizing sub-threshold technology for the creation of secure circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao	65NM sub-threshold 11T-SRAM for ultra low voltage applications.	SoCC	2008	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Anantha P. Chandrakasan	A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
15	Yoshioki Isobe, Kiyohito Hara, Dondee Navarro, Youichi Takeda, Tatsuya Ezaki, Mitiko Miura-Mattausch	Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
15	Hui Shao, Chi-Ying Tsui	A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic.	ESSCIRC	2007	DBLP DOI BibTeX RDF
15	Bo Zhai	Ultra-low power processor design using sub-threshold design techniques.		2007	RDF
15	Benton H. Calhoun, Anantha P. Chandrakasan	Static noise margin variation for sub-threshold SRAM in 65-nm CMOS.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Anantha P. Chandrakasan	Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
15	Nikolaos P. Papadopoulos, Alkis A. Hatzopoulos, Dimitris K. Papakostas, C. A. Dimitriadis, Stilianos Siskos	Modeling the impact of light on the performance of polycrystalline thin-film transistors at the sub-threshold region.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
15	Alice Wang, Benton H. Calhoun, Anantha P. Chandrakasan	Sub-threshold Design for Ultra Low-Power Systems		2006	DOI RDF
15	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
15	Vivienne Sze, Raúl Blázquez, Manish Bhardwaj, Anantha P. Chandrakasan	An Energy Efficient Sub-Threshold Baseband Processor Architecture for Pulsed Ultra-Wideband Communications.	ICASSP (3)	2006	DBLP DOI BibTeX RDF
15	Minato Kawaguchi, Hiroyuki Mino, Dominique M. Durand	Information Transmission in Hippocampal CA1 Neuron Models in the Presence of Poisson Shot Noise: the Case of Periodic Sub-threshold Spike Trains.	EMBC	2006	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Anantha P. Chandrakasan	A 256kb Sub-threshold SRAM in 65nm CMOS.	ISSCC	2006	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Anantha P. Chandrakasan	Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS.	ESSCIRC	2005	DBLP DOI BibTeX RDF
15	Carlos Aguirre, Doris Campos, Pedro Pascual, Eduardo Serrano	Neuronal Behavior with Sub-threshold Oscillations and Spiking/Bursting Activity Using a Piecewise Linear Two-Dimensional Map.	ICANN (1)	2005	DBLP DOI BibTeX RDF
15	Benton H. Calhoun	Low energy digital circuit design using sub-threshold operation.		2005	RDF
15	Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown	Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies.	ESSCIRC	2003	DBLP DOI BibTeX RDF
15	Gregor Wenning, Klaus Obermayer	Adjusting stochastic resonance in a leaky integrate and fire neuron to sub-threshold stimulus distributions.	Neurocomputing	2002	DBLP DOI BibTeX RDF
14	Frank Sill, Frank Grassert, Dirk Timmermann	Total leakage power optimization with improved mixed gates.	SBCCI	2005	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
14	Nikolay N. Elkin, Anatoly P. Napartovich, Alexander G. Sukharev, Dmitri V. Vysotsky	3D Modelling of Diode Laser Active Cavity.	NAA	2004	DBLP DOI BibTeX RDF
14	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
14	Enno de Lange, Martin Hasler	Predicting single spikes and spike patterns with the Hindmarsh-Rose model.	Biol. Cybern.	2008	DBLP DOI BibTeX RDF	Hindmarsh-Rose model, Parameter fitting, Quantitative neuron modeling, Spike-timing, Neocortical neurons, Nonlinear optimization, Nonlinear dynamics, Bifurcation analysis
14	Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu	An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy 0001	Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.	ICCAD	2006	DBLP DOI BibTeX RDF
14	Youngbok Kim, Anuj Agarwal, Sameer R. Sonkusale	Low power current mode ADC for CMOS sensor IC.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
14	Ashutosh S. Dhodapkar, James E. Smith 0001	Tuning Reconfigurable Microarchitectures for Power Efficiency.	IPDPS	2004	DBLP DOI BibTeX RDF
13	Manoj Sachdev	Deep sub-micron IDDQ testing: issues and solutions.	ED&TC	1997	DBLP DOI BibTeX RDF
11	Saihua Lin, Yu Wang 0002, Rong Luo, Huazhong Yang	A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Fred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon	Integrated circuit design with NEM relays.	ICCAD	2008	DBLP DOI BibTeX RDF
11	S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur	Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block.	VLSI Design	2008	DBLP DOI BibTeX RDF
11	Juan Gao, Philip Holmes	On the dynamics of electrically-coupled neurons with inhibitory synapses.	J. Comput. Neurosci.	2007	DBLP DOI BibTeX RDF	Bifurcation diagrams, Electrical coupling, Inhibitory synapses, Integrate-and-fire models, Poincaré maps
11	Rodrigo Jaramillo-Ramirez, Mohab Anis	A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
11	Jing Li 0073, Kunhyuk Kang, Aditya Bansal, Kaushik Roy 0001	High Performance and Low Power Electronics on Flexible Substrate.	DAC	2007	DBLP DOI BibTeX RDF
11	Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija	Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design.	PATMOS	2006	DBLP DOI BibTeX RDF
11	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino	Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Chanseok Hwang, Chang Woo Kang, Massoud Pedram	Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.	ISQED	2006	DBLP DOI BibTeX RDF
11	Srivathsan Krishnamohan, Nihar R. Mahapatra	Increasing the energy efficiency of pipelined circuits via slack redistribution.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	slack passing, time borrowing, low-power design
11	H. C. Srinivasaiah, Navakanta Bhat	Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment.	VLSI Design	2004	DBLP DOI BibTeX RDF	Disposable spacer, Transmission of moments technique, Plackett-Burman design, Sensitivity analysis, Statistical modeling, CMOS technology, Response surface methodology, Monte carlo analysis
11	Rohini Krishnan, José Pineda de Gyvez	Low Energy Switch Block For FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
11	Narender Hanchate, Nagarajan Ranganathan	A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.	VLSI Design	2004	DBLP DOI BibTeX RDF
11	Sagar S. Sabade, D. M. H. Walker	Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
10	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
10	Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie 0001, Mary Jane Irwin, Osama Awadel Karim	A low-power phase change memory based hybrid cache architecture.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	PRAM, phase change memory
10	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
10	Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta	Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
10	A. K. Mrunal, M. A. Shirasgaonkar, Rajendra M. Patrikar	Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL).	APCCAS	2006	DBLP DOI BibTeX RDF
10	Sagar S. Sabade, D. M. H. Walker	Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction.	VTS	2002	DBLP DOI BibTeX RDF
7	Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal	Xetal-Pro: an ultra-low energy and high throughput SIMD processor.	DAC	2010	DBLP DOI BibTeX RDF	Xetal-Pro, hybrid memory system, SIMD, low-energy
7	Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta	Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.	NanoNet	2009	DBLP DOI BibTeX RDF	low-energy circuits, single electron transistors, binary decision diagram logic circuits
7	Jader A. De Lima	A compact low-distortion low-power instrumentation amplifier.	SBCCI	2009	DBLP DOI BibTeX RDF	class-AB output stage, double-port amplifier, instrumentation amplifier
7	Hongbo Zhou 0001, Hong-Ju Yang, Haiyun Xu, Qiang Cheng	A New Computational Tool for the Post Session Analysis of the Prepulse Inhibition Test in Neural Science.	CSE (2)	2009	DBLP DOI BibTeX RDF
7	Basab Datta, Wayne P. Burleson	Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sensor, interconnect, temperature, oscillator
7	Kuande Wang, Li Chen, Jinsheng Yang	AN ultra low power fault tolerant SRAM design in 90nm CMOS.	CCECE	2009	DBLP DOI BibTeX RDF
7	S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya	100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS.	VLSI Design	2009	DBLP DOI BibTeX RDF
7	QuanJun Cao, Yimen Zhang, Yuming Zhang, HongLiang Lv, YueHu Wang, XiaoYan Tang, Hui Guo	Improved empirical DC I-V model for 4H-SiC MESFETs.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	4H-SiC MESFET, DC I-V characteristics, nonlinear regression, empirical model, Levenberg-Marquardt method
7	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
7	Ming Liu 0015, Hong Chen 0002, Run Chen, Zhihua Wang 0001	Low-power IC design for a wireless BCI system.	ISCAS	2008	DBLP DOI BibTeX RDF
7	Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer	Improving the power-delay product in SCL circuits using source follower output stage.	ISCAS	2008	DBLP DOI BibTeX RDF
7	Betty Prince	Nanotechnology and emerging memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory
7	Siddharth Garg, Diana Marculescu	On the impact of manufacturing process variations on the lifetime of sensor networks.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	leakage power variability, manufacturing process variations, sensor networks, lifetime
7	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
7	Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu	A Study on Impact of Leakage Current on Dynamic Power.	ISCAS	2007	DBLP DOI BibTeX RDF
7	Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien	New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode.	ISCAS	2007	DBLP DOI BibTeX RDF
7	Tamer Cakici, Keejong Kim, Kaushik Roy 0001	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
7	Ashesh Rastogi, Wei Chen, Sandip Kundu	On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.	DAC	2007	DBLP DOI BibTeX RDF
7	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A nanowatt ADC for ultra low power applications.	ISCAS	2006	DBLP DOI BibTeX RDF
7	Srinjoy Mitra, Stefano Fusi, Giacomo Indiveri	A VLSI spike-driven dynamic synapse which learns only when necessary.	ISCAS	2006	DBLP DOI BibTeX RDF
7	K. Kiyoyama, Yoshinobu Tanaka, Michihisa Onoda	A low current consumption delta-sigma modulator for body-implanted chip.	ISCAS	2006	DBLP DOI BibTeX RDF
7	Sanjeev K. Jain, Pankaj Agarwal	A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology.	VLSI Design	2006	DBLP DOI BibTeX RDF
7	Shan Gao, Junning Chen, Daoming Ke, Xiulong Wu	A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design.	APCCAS	2006	DBLP DOI BibTeX RDF
7	Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy 0001	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.	DAC	2006	DBLP DOI BibTeX RDF	adaptive source biasing, hold failures, low power SRAM
7	Alice Morelli, Rosapia Lauro Grotto, Fortunato Tito Arecchi	A Feature-Based Model of Semantic Memory: The Importance of Being Chaotic.	BVAI	2005	DBLP DOI BibTeX RDF
7	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.	ISLPED	2005	DBLP DOI BibTeX RDF	double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage
7	Leila Shepherd, Chris Toumazou	Towards an implantable ultra-low power biochemical signal processor for blood and tissue monitoring.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
7	M. Kiyoyama, Michihisa Onoda, Yoshinobu Tanaka	A low current consumption CMOS latched comparator for body-implanted chip.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
7	R. Srinivasan, Navakanta Bhat	Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications.	VLSI Design	2005	DBLP DOI BibTeX RDF
7	Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri	A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents.	DAC	2005	DBLP DOI BibTeX RDF	leakage power, self-adjusting, body-biasing
7	Fredrik Edin, Christian K. Machens, Hartmut Schütze, Andreas V. M. Herz	Searching for Optimal Sensory Signals: Iterative Stimulus Reconstruction in Closed-Loop Experiments.	J. Comput. Neurosci.	2004	DBLP DOI BibTeX RDF	stimulus reconstruction, insect, auditory receptor, neural coding
7	Mahadevan Gomathisankaran, Akhilesh Tyagi	WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays.	ISVLSI	2004	DBLP DOI BibTeX RDF
7	Hari Ananthan, Aditya Bansal, Kaushik Roy 0001	FinFET SRAM - Device and Circuit Design Considerations.	ISQED	2004	DBLP DOI BibTeX RDF
7	Kaviraj Chopra, Sarma B. K. Vrudhula	Implicit pseudo boolean enumeration algorithms for input vector control.	DAC	2004	DBLP DOI BibTeX RDF	power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods
7	Cassondra Neau, Kaushik Roy 0001	Optimal body bias selection for leakage improvement and process compensation over different technology generations.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias
7	Saied Hemati, Amir H. Banihashemi	Iterative decoding in analog CMOS.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	analog CMOS, analog iterative decoder, asynchronous iterative decoding, min-sum decoding, soft decoding, analog circuit, turbo codes, iterative decoding, low-density parity-check codes
7	Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni	Extending the Viability of IDDQ Testing in the Deep Submicron Era.	ISQED	2002	DBLP DOI BibTeX RDF
7	Giancarlo La Camera, Stefano Fusi, Walter Senn, Alexander Rauch, Hans-Rudolf Lüscher	When NMDA Receptor Conductances Increase Inter-spike Interval Variability.	ICANN	2002	DBLP DOI BibTeX RDF
7	Anton Chichkov, Dirk Merlier, Peter Cox	Current Testing Procedure for Deep Submicron Devices.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	ASIC testing, IDDQ, deep submicron
7	Juan M. Díez, Juan Carlos López 0001	Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion.	DATE	2000	DBLP DOI BibTeX RDF
7	Claude Thibeault, Luc Boisvert	On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis.	DFT	1998	DBLP DOI BibTeX RDF	current signatures, diagnosis, Integrated circuits, bridging faults, Iddq testing