Search results for "Synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Srinivas Katkoori, Nand Kumar, Ranga Vemuri	High level profiling based low power synthesis technique.	ICCD	1995	DBLP DOI BibTeX RDF	high level profiling based low power synthesis technique, average switching capacitance, user-specified set, switching capacitance, VLSI, delay, logic design, power estimation, area
19	Yen-Min Huang, Chinya V. Ravishankar	Designing an Agent Synthesis System for Cross-RPC Communication.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	agent synthesis system, cross-RPC communication, RPC protocols, large heterogeneous environment, RPC agents, RPC heterogeneities, agent development costs, cross-RPC performance, distributed systems, parallel programming, protocols, rapid prototyping, software prototyping, remote procedure calls, remote procedure call, telecommunications computing, transport layer, maintenance costs
19	Sanghoon Sull, Narendra Ahuja	Integrated 3-D Analysis and Analysis-Guided Synthesis of Flight Image Sequences.	IEEE Trans. Pattern Anal. Mach. Intell.	1994	DBLP DOI BibTeX RDF	3-D analysis, analysis-guided synthesis, flight image sequences, 3-D motion, point features, texture gradient, vanishing line, planar textured surface, sequential batch method, image attributes, binocular sequence, synthetic sequence, workstation monitor, performance evaluation, optimization, image segmentation, motion estimation, image sequences, optical flow, lines, monocular image sequence, motion recovery, multiple cues
19	Bapiraju Vinnakota, Niraj K. Jha	Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	algorithm-based fault-tolerant systems, computation-intensive tasks, ABFT scheme, synthesis method, fault-tolerant median filter, reliability, graph theory, parallel architectures, fault tolerant computing, dependence graphs, parallelarchitectures
19	Zohar Manna, Richard J. Waldinger	Fundamentals of Deductive Program Synthesis.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	deductive program synthesis, deductive-tableau system, theorem-proving framework, nonclausal resolution rule, induction rule, formal specification, artificial intelligence, specification, theorem proving, program testing, reasoning, inference mechanisms, proof
19	Jarke J. van Wijk	Spot noise texture synthesis for data visualization.	SIGGRAPH	1991	DBLP DOI BibTeX RDF	scientific visualization, texture synthesis, fractals, flow visualization, particle systems
19	Jayanth V. Rajan, Donald E. Thomas	Synthesis by delayed binding of decisions.	DAC	1985	DBLP DOI BibTeX RDF	behavioral partioning, synthesis, automatic design
19	Sebastián Uchitel, Greg Brunet, Marsha Chechik	Synthesis of Partial Behavior Models from Properties and Scenarios.	IEEE Trans. Software Eng.	2009	DBLP DOI BibTeX RDF
19	Anthony C. Robinson	Needs Assessment for the Design of Information Synthesis Visual Analytics Tools.	IV	2009	DBLP DOI BibTeX RDF
19	Feng Wang 0004, Yuan Xie 0001, Andrés Takach	Variation-aware resource sharing and binding in behavioral synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
19	Sandip Ray, Kecheng Hao, Yan Chen 0001, Fei Xie, Jin Yang 0006	Formal Verification for High-Assurance Behavioral Synthesis.	ATVA	2009	DBLP DOI BibTeX RDF
19	Yoad Lustig, Moshe Y. Vardi	Synthesis from Component Libraries.	FoSSaCS	2009	DBLP DOI BibTeX RDF
19	Vyas Krishnan, Srinivas Katkoori	Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
19	Gabriel Recatalá, Eris Chinellato, Angel P. del Pobil, Youcef Mezouar, Philippe Martinet	Biologically-inspired 3D grasp synthesis based on visual exploration.	Auton. Robots	2008	DBLP DOI BibTeX RDF	Biologically-inspired robots, Models of human manipulation, Grasping/dexterous manipulation, Active perception, Robot vision
19	Sushanta K. Mandal, Shamik Sural, Amit Patra	ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Gülin Tulunay, Sina Balkir	A Synthesis Tool for CMOS RF Low-Noise Amplifiers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Tao Xu 0002, Krishnendu Chakrabarty	Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Physical design automation, microfluidics, biochips, module placement
19	Roberto Costantini, Luciano Sbaiz, Sabine Süsstrunk	Higher Order SVD Analysis for Dynamic Texture Synthesis.	IEEE Trans. Image Process.	2008	DBLP DOI BibTeX RDF
19	Hsien-I Lin, C. S. George Lee	Self-organizing skill synthesis.	IROS	2008	DBLP DOI BibTeX RDF
19	Feng Wang 0004, Guangyu Sun 0003, Yuan Xie 0001	A Variation Aware High Level Synthesis Framework.	DATE	2008	DBLP DOI BibTeX RDF
19	Sharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi	Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations.	DSD	2008	DBLP DOI BibTeX RDF
19	Morteza Damavandpeyma, Siamak Mohammadi	Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool.	DSD	2008	DBLP DOI BibTeX RDF
19	Chia-Ming Cheng, Shu-Jyuan Lin, Shang-Hong Lai, Jinn-Cherng Yang	Improved novel view synthesis from depth image with large baseline.	ICPR	2008	DBLP DOI BibTeX RDF
19	Junyu Dong, Yuanxu Duan, Guimei Sun, Lin Qi 0004	Texture synthesis by Support Vector Machines.	ICPR	2008	DBLP DOI BibTeX RDF
19	Huan Ren, Shantanu Dutt	Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure.	ICCAD	2008	DBLP DOI BibTeX RDF
19	Fanghua Liu, Hongtao Wu, Lüzhong Ma	Intellectualized Structural Synthesis and Classification of the 3-DOF Space Parallel Robot Mechanisms.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Parallel robot mechanisms, Single open chain limb
19	Sen Wang, Xianfeng David Gu, Hong Qin 0001	Automatic non-rigid registration of 3D dynamic data for facial expression synthesis and transfer.	CVPR	2008	DBLP DOI BibTeX RDF
19	Ting Liu 0007, Camel Tanougast, Serge Weber	A framework of architectural synthesis for dynamically reconfigurable FPGAs.	SoCC	2008	DBLP DOI BibTeX RDF
19	Palle Dahlstedt	Dynamic Mapping Strategies for Expressive Synthesis Performance and Improvisation.	CMMR	2008	DBLP DOI BibTeX RDF
19	Yulia Korukhova	An approach to automatic deductive synthesis of functional programs.	Ann. Math. Artif. Intell.	2007	DBLP DOI BibTeX RDF	Mathematics Subject Classification 68T20
19	Antonio Criminisi, Andrew Blake 0001, Carsten Rother, Jamie Shotton, Philip H. S. Torr	Efficient Dense Stereo with Occlusions for New View-Synthesis by Four-State Dynamic Programming.	Int. J. Comput. Vis.	2007	DBLP DOI BibTeX RDF	dense stereo, gaze correction, image-based rendering, video-conferencing
19	Takao Konishi, Naohiro Hamada, Hiroshi Saito	A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation.	CIT	2007	DBLP DOI BibTeX RDF
19	Xiao Xiao Hu, Hongjie Zhang, Zhu Liang Yu, Meng Hwa Er	Pattern Synthesis via Convex Optimization for Microphone Arrays.	SiPS	2007	DBLP DOI BibTeX RDF
19	Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li 0001, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz	The nuts and bolts of physical synthesis.	SLIP	2007	DBLP DOI BibTeX RDF
19	Fan Yang 0001, Xuan Zeng 0001, Yangfeng Su, Dian Zhou	RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Cong Zhang, Amol Bakshi, Viktor K. Prasanna	ModelML: a Markup Language for Automatic Model Synthesis.	IRI	2007	DBLP DOI BibTeX RDF
19	Sebastián Uchitel, Greg Brunet, Marsha Chechik	Behaviour Model Synthesis from Properties and Scenarios.	ICSE	2007	DBLP DOI BibTeX RDF
19	Zdenek Krnoul, Milos Zelezný	Translation and Conversion for Czech Sign Speech Synthesis.	TSD	2007	DBLP DOI BibTeX RDF
19	Chunpeng Li, Shihong Xia, Zhaoqi Wang	Pose Synthesis Using the Inverse of Jacobian Matrix Learned from Examples.	VR	2007	DBLP DOI BibTeX RDF
19	Pallav Gupta, Abhinav Agrawal 0002, Niraj K. Jha	An Algorithm for Synthesis of Reversible Logic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Arthur Nieuwoudt, Yehia Massoud	Variability-Aware Multilevel Integrated Spiral Inductor Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Hua Tang, Hui Zhang 0057, Alex Doboli	Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Christof Faller	Parametric multichannel audio coding: synthesis of coherence cues.	IEEE Trans. Speech Audio Process.	2006	DBLP DOI BibTeX RDF
19	Wei-Chen Chang, Alvin Wen-Yu Su	A Multichannel Recurrent Network Analysis/Synthesis Model for Coupled-String Instruments.	IEEE Trans. Speech Audio Process.	2006	DBLP DOI BibTeX RDF
19	Gaurav Singh 0006, Sandeep K. Shukla	Low-power hardware synthesis from TRS-based specifications.	MEMOCODE	2006	DBLP DOI BibTeX RDF
19	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida	Pre-synthesis optimization of multiplications to improve circuit performance.	DATE	2006	DBLP DOI BibTeX RDF
19	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada	Function Call Optimization in Behavioral Synthesis.	DSD	2006	DBLP DOI BibTeX RDF
19	Sven Schewe	Synthesis for Probabilistic Environments.	ATVA	2006	DBLP DOI BibTeX RDF
19	Sujan Pandey, Manfred Glesner	Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.	ISCAS	2006	DBLP DOI BibTeX RDF
19	George Economakos	Behavioral synthesis with SystemC and PSL assertions for interface specification.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Zhigang Gao, Zhaohui Wu 0001, Hong Li	Implementation Synthesis of Embedded Software Under Operating Systems Supporting the Hybrid Scheduling Model.	EUC	2006	DBLP DOI BibTeX RDF
19	Renqiu Huang, Ranga Vemuri	Transformation synthesis for data intensive applications to FPGAs.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
19	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF
19	Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin	High-Level Synthesis for Self-Timed Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
19	Nattawut Thepayasuwan, Alex Doboli	Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Toffoli network synthesis with templates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	Darko Kirovski, Milenko Drinic, Miodrag Potkonjak	Engineering change protocols for behavioral and system synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	Mariam Momenzadeh, Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	Hiroshi Kawasaki, Kyoung-Dae Seo, Yutaka Ohsawa, Ryo Furukawa 0001	Patch-based BTF synthesis for real-time rendering.	ICIP (1)	2005	DBLP DOI BibTeX RDF
19	Toshihisa Tanaka	Optimal design for synthesis filters of oversampled uniform perfect reconstruction filter banks with 50% overlapping.	ICIP (1)	2005	DBLP DOI BibTeX RDF
19	Francisco-Javier Veredas, Jordi Carrabina	Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.	PATMOS	2005	DBLP DOI BibTeX RDF
19	Huiying Yang, Anuradha Agarwal, Ranga Vemuri	Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams.	ISVLSI	2005	DBLP DOI BibTeX RDF
19	Raoul F. Badaoui, Ranga Vemuri	Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis.	DATE	2005	DBLP DOI BibTeX RDF
19	Eddie Cooke, Noel E. O'Connor	Scalable Virtual Viewpoint Image Synthesis for Multiple Camera Environments.	IV	2005	DBLP DOI BibTeX RDF
19	Leonardo Amorim, Raimundo S. Barreto, Paulo Romero Martins Maciel, Eduardo Tavares, Meuse N. Oliveira Jr., Arthur Bessa, Ricardo Massa Ferreira Lima	A Methodology for Software Synthesis of Embedded Real-Time Systems Based on TPN and LSC.	ICESS	2005	DBLP DOI BibTeX RDF
19	Leandro Tonietto, Marcelo Walter, Cláudio Rosito Jung	Patch-Based Texture Synthesis Using Wavelets.	SIBGRAPI	2005	DBLP DOI BibTeX RDF
19	Phil Corbishley, David G. Haigh	Rules for systematic synthesis of all-transistor analogue circuits by admittance matrix expansion.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
19	Laurent Pottier	Strategies for the Control of Microsound Synthesis Within the "GMU" Project.	CMMR	2005	DBLP DOI BibTeX RDF
19	Rui Zhang, Pallav Gupta, Niraj K. Jha	Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.	VLSI Design	2005	DBLP DOI BibTeX RDF
19	Geun Rae Cho, Tom Chen 0001	Synthesis of single/dual-rail mixed PTL/static logic for low-power applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey	Resource budgeting for Multiprocess High-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau	Using global code motions to improve the quality of results for high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim	Coupling-aware high-level interconnect synthesis [IC layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli	Synthesis for Manufacturability: A Sanity Check.	DATE	2004	DBLP DOI BibTeX RDF
19	Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen	Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.	DATE	2004	DBLP DOI BibTeX RDF
19	Francesco Bruschi, Massimo Bombana	A Design Methodology for the Exploitation of High Level Communication Synthesis.	DATE	2004	DBLP DOI BibTeX RDF
19	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.	ASP-DAC	2004	DBLP DOI BibTeX RDF
19	Chris Sullivan, Alex Wilson, Stephen P. G. Chappell	Using C based logic synthesis to bridge the productivity gap.	ASP-DAC	2004	DBLP DOI BibTeX RDF
19	Chris V. Jones 0001, Maja J. Mataric	Synthesis and Analysis of Non-Reactive Controllers for Multi-Robot Sequential Task Domains.	ISER	2004	DBLP DOI BibTeX RDF
19	Liang Xiao 0001, Huizhong Wu, Shuchun Tang, Yang Liu	Modeling and Simulation of Digital Scene Image Synthesis Using Image Intensified CCD Under Different Weathers in Scene Matching Simulation System.	AsiaSim	2004	DBLP DOI BibTeX RDF
19	Marcos Alonso, Günter Geiger, Sergi Jordà	An Internet Browser Plug-in for Real-time Audio Synthesis.	WEDELMUSIC	2004	DBLP DOI BibTeX RDF
19	Sina Balkir, Günhan Dündar, Güner Alpaydin	Evolution Based Synthesis of Analog Integrated Circuits and Systems.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
19	David A. Basin, Yves Deville, Pierre Flener, Andreas Hamfelt, Jørgen Fischer Nilsson	Synthesis of Programs in Computational Logic.	Program Development in Computational Logic	2004	DBLP DOI BibTeX RDF
19	William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski	Quantum logic synthesis by symbolic reachability analysis.	DAC	2004	DBLP DOI BibTeX RDF	model checking, formal verification, quantum computing, satisfiability, reversible logic
19	Kenneth Francken, Georges G. E. Gielen	A high-level simulation and synthesis environment for ΔΣ modulators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	Alex Doboli, Ranga Vemuri	Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	Ramy Iskander, Mohamed Dessouky, Maie Aly, Mahmoud Magdy, Noha Hassan, Noha Soliman, Sami Moussa	Synthesis of CMOS Analog Cells Using AMIGO.	DATE	2003	DBLP DOI BibTeX RDF
19	Lech Józwiak, Szymon Bieganski, Artur Chojnacki	Information-driven Library-based Circuit Synthesis.	DSD	2003	DBLP DOI BibTeX RDF
19	Anas Al-Rabadi	Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space.	ISMVL	2003	DBLP DOI BibTeX RDF
19	Kamal S. Khouri, Niraj K. Jha	Leakage power analysis and reduction during behavioral synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
19	Robert P. Goldman, David J. Musliner, Michael J. S. Pelican	Exploiting Implicit Representations in Timed Automaton Verification for Controller Synthesis.	HSCC	2002	DBLP DOI BibTeX RDF
19	Aneesh Koorapaty, Lawrence T. Pileggi	Modular, Fabric-Specific Synthesis for Programmable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
19	Chih-Wei Jim Chang, Malgorzata Marek-Sadowska	ATPG-based logic synthesis: an overview.	ICCAD	2002	DBLP DOI BibTeX RDF
19	Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim	Coupling-aware high-level interconnect synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
19	Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha	Input Space Adaptive Embedded Software Synthesis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
19	Elie Torbey, John P. Knight	Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
19	Andrew A. Duncan, David C. Hendry, Peter Gray	The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
19	Ki-Il Kum, Wonyong Sung	Combined word-length optimization and high-level synthesis ofdigital signal processing systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
19	Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk	Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis.	DSD	2001	DBLP DOI BibTeX RDF
19	Josep Carmona 0001, Jordi Cortadella, Enric Pastor	A structural encoding technique for the synthesis of asynchronous circuits.	ACSD	2001	DBLP DOI BibTeX RDF