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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 4301 publication records. Showing 4296 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
29 | Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh |
Differences in ASIC, COT and processor design (panel). |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
ASIC |
29 | F. G. Lorca, Lounis Kessal, Didier Demigny |
Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. |
ICIP (2) |
1997 |
DBLP DOI BibTeX RDF |
Deriche filter architecture, real time edge detection, optimal edge detectors, FGGA circuits, memory size reduction, scale parameter, first order recursive filter, algorithm, ASIC, CMOS, adders, hardware implementation, IIR filters, IIR filters, software implementation, real time implementation, computation cost reduction, 1.2 micron |
29 | Ronald Collet |
Which ASIC Technology Will Dominate the 1990's (Panel Abstract). |
DAC |
1992 |
DBLP BibTeX RDF |
ASIC |
27 | Wei Liu, Xuecong Lu, Yuxi Mao, Bing Li 0011 |
A 23.5 μA Ultra-Low Standby Power Microphone ASIC with the Voice Activity Detection Based on A Level-Crossing ADC. |
ASICON |
2023 |
DBLP DOI BibTeX RDF |
|
27 | Weiqi Zhi, Ting Yi, Zhiliang Hong |
A Review and Perspective on Electrode Patch-Based Fetal ECG Monitoring ASIC. |
ASICON |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Zhen Lu, Ting Yi, Zhiliang Hong |
A Review of PPG/NIRS Acquisition ASIC and System. |
ASICON |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Yulong Zhu, Futian Liang, Xinzhe Wang, Bo Feng, Chenxi Zhu, Ge Jin |
An ASIC for Discriminating Single Photon Detector Signal of High-Speed Quantum Key Distribution System. |
ASICON |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Conghui Zhao, Yingjian Yan, Wei Li |
An efficient ASIC Implementation of QARMA Lightweight Algorithm. |
ASICON |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Danyang Yang, Zibin Dai, Wei Li 0131, Tao Chen 0047 |
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit. |
ASICON |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Chun Cai, Hiromitsu Awano, Makoto Ikeda |
High-Speed ASIC Implementation of Paillier Cryptosystem with Homomorphism. |
ASICON |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin |
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Suoming Pu, Bo Yu, Xuan Zou |
Robustness and performance analysis on high speed ASIC design with canonical statistical timing model. |
ASICON |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Hongming Chen 0002, Xiaoyuan Chen, Tie Liu, Yuhua Cheng |
ASIC implementation of an OFDM baseband transceiver for HINOC. |
ASICON |
2011 |
DBLP DOI BibTeX RDF |
|
27 | David G. Chinnery, Kurt Keutzer |
Closing the Gap Between ASIC and Custom - Tools and Techniques for High-Performance ASIC Design. |
|
2004 |
DOI RDF |
|
27 | Jan Andersson |
A DSP ASIC design flow based on VHDL and ASIC-emulation. |
EURO-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel |
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. |
EDAC-ETC-EUROASIC |
1994 |
DBLP DOI BibTeX RDF |
|
27 | E. B. Patterson, P. G. Holmes, D. Morley |
Microprocessor/ASIC to total ASIC design for cycloconverter drives. |
Microprocess. Microsystems |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Robert Law |
Using student blogs for documentation in software development projects. |
ITiCSE |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton |
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
structured asics, via programmable fabric |
23 | Raimon Casanova, Ángel Dieguez, Anna Arbat, Oscar Alonso, Andreu Sanuy, Joan Canals, Jorde Colomer, Josep Samitier |
Integration of the control electronics for a mm3-sized autonomous microrobot into a single chip. |
ICRA |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Pedro Miguens Matutino, Leonel Sousa |
An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Ruchika Verma, Ali Akoglu |
A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Mary Lou Jepsen |
CAD for displays! |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Xingzhi Wen, Uzi Vishkin |
Fpga-based prototype of a pram-on-chip processor. |
Conf. Computing Frontiers |
2008 |
DBLP DOI BibTeX RDF |
ease-of-programming, explicit multi-threading, on-chip parallel processor, pram, parallel algorithms, xmt |
23 | Mohamad Rahal, Andreas Demosthenous |
An integrated design for the front-end of an inductive position sensor. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Mark Hammerquist, Roman L. Lysecky |
Design space exploration for application specific FPGAS in system-on-a-chip designs. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy 0001, Ranjani Narayan |
Synthesis of application accelerators on Runtime Reconfigurable Hardware. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Allen C. Cheng |
Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin |
Architectural implications of brick and mortar silicon manufacturing. |
ISCA |
2007 |
DBLP DOI BibTeX RDF |
chip assembly, design re-use, interconnect design |
23 | Jon Patrick |
The Scamseek Project - Text Mining for Financial Scams on the Internet. |
Selected Papers from AusDM |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann |
Design and implementation of a reconfigurable hardware for secure embedded systems. |
AsiaCCS |
2006 |
DBLP DOI BibTeX RDF |
secured embedded system, AES, RSA, reconfigurable architecture, DES, processing element |
23 | Uthman Alsaiari, Resve A. Saleh |
Testable and self-repairable structured logic design. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Hugo Hedberg, Thomas Lenart, Henrik Svensson |
A Complete MP3 Decoder on a Chip. |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo |
The design of dynamically reconfigurable datapath coprocessors. |
ACM Trans. Embed. Comput. Syst. |
2004 |
DBLP DOI BibTeX RDF |
coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis |
23 | David H. Goldberg, Andreas G. Andreou, Pedro Julián, Philippe O. Pouliquen, Laurence Riddle, Rich Rosasco |
A wake-up detector for an acoustic surveillance sensor network: algorithm and VLSI implementation. |
IPSN |
2004 |
DBLP DOI BibTeX RDF |
acoustic surveillance, wake-up detection, sensor networks, power management, maximum likelihood estimation, periodicity, VLSI implementation |
23 | André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica |
What is the right model for programming and using modern FPGAs? |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura 0002, Shigeto Inui, Takeshi Yoshimura |
Timing optimization by replacing flip-flops to latches. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh |
Innovate or perish: FPGA physical design. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
FPGA, partitioning, placement, physical design, floorplanning, delay estimation, routing architecture |
23 | Raymond Hoare, Shen Chih Tung, Katrina Werger |
An 88-Way Multiprocessor within an FPGA with Customizable Instructions. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Architecture, Parallelism, DSP, SIMD |
23 | Xizhi Li, Tiecai Li |
ECOMIPS: An Economic MIPS CPU Design on FPGA. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
23 | N. Venkateswaran 0002, C. Chandramouli |
General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies. |
ICES |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung |
Re-Using DFT Logic for Functional and Silicon Debugging Test. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Zhining Huang, Sharad Malik |
Exploiting operation level parallelism through dynamically reconfigurable datapaths. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
|
23 | M. Ernst, Steffen Klupsch, Oliver Hauck, Sorin A. Huss |
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems. |
IEEE International Workshop on Rapid System Prototyping |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Martin Speitel, Michael Schlicht, Martin Leyh |
Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
real-time rapid prototyping, behavioral synthesis, digital radio |
23 | Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking |
A Robust Solution to the Timing Convergence Problem in High-Performance Design. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
timing convergence, maximum capacitance, synthesis, placement, design-rules |
23 | John Poulton |
An Embedded DRAM for CMOS ASICs. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Herbert Dawid, Gerhard P. Fettweis, Heinrich Meyr |
A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. |
IEEE Trans. Very Large Scale Integr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Luc Desormeaux, Valek Szwarc, John H. Lodge |
A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi |
A hardware peripheral for Java bytecodes translation acceleration. |
SAC |
2010 |
DBLP DOI BibTeX RDF |
stack folding, ASIC, RISC, Java processor |
23 | Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su |
Via configurable three-input lookup-tables for structured ASICs. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
via-configurable, layout, look-up-table, vlsi, structured ASIC |
23 | P. Subramanian, Jagonda Patil, Manish Kumar Saxena |
FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications. |
IWCMC |
2009 |
DBLP DOI BibTeX RDF |
ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating |
23 | Jianwei Dong, Shi Zhang, Xiaonan Jia |
A Portable Intelligent ECG Monitor Based on Wireless Internet and Embedded System Technology. |
BMEI (2) |
2008 |
DBLP DOI BibTeX RDF |
ECG interpretation, ASIC, RTOS, ECG monitor |
23 | Jens-Peter Kaps |
Chai-Tea, Cryptographic Hardware Implementations of xTEA. |
INDOCRYPT |
2008 |
DBLP DOI BibTeX RDF |
symmetric key algorithms, TEA, XTEA, FPGA, ASIC, Efficient implementation |
23 | Nikos Chrysos, Giorgos Dimitrakopoulos |
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation. |
Hot Interconnects |
2008 |
DBLP DOI BibTeX RDF |
VOQ crossbar scheduler, backlog-aware, deterministic service guarantees, round-robin arbiters, ASIC design |
23 | Jianhua Liu, Yi Zhu 0002, Haikun Zhu, Chung-Kuan Cheng, John Lillis |
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder |
23 | Alireza Hodjat, Ingrid Verbauwhede |
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
crypto-processor, security, VLSI, cryptography, Advanced Encryption Standard (AES), ASIC, hardware architectures |
23 | Ian Kuon, Jonathan Rose |
Measuring the gap between FPGAs and ASICs. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
area comparison, delay comparison, power comparison, FPGA, ASIC |
23 | Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen |
Architecture for area-efficient 2-D transform in H.264/AVC. |
ICME |
2005 |
DBLP DOI BibTeX RDF |
architecture shrinking, 2-D transform, H.264-AVC, automatic volume control, very large scale integration, ASIC, application-specific integrated circuit, matrix multiplication, minimization, CMOS technology, VLSI technology |
23 | Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti |
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation |
23 | Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar |
Power Reduction Technique Using Multi-vt Libraries. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
High-Vt, Low-Vt, DFT, ASIC, Leakage power, DSM |
23 | Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer |
Hardware speech recognition for user interfaces in low cost, low power devices. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
TIER, tamil, low power, speech recognition, ASIC |
23 | Peter J. Osler |
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
synthesis, placement, application specific integrated circuit (ASIC), register transfer level (RTL), static timing analysis (STA), netlist |
23 | Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin |
A 2 Gb/s balanced AES crypto-chip implementation. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
AES, rijndael, ASIC implementation |
23 | Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan |
VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
Image Processing, VLSI, Watermarking, ASIC design |
23 | Daniela De Venuto, Michael J. Ohletz |
On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages. |
J. Electron. Test. |
2001 |
DBLP DOI BibTeX RDF |
mixed-signal ASIC, hardware conversion, GO/NOGO test, bias programming, DfT, power consumption, overhead |
23 | Lijun Gao, Keshab K. Parhi |
Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
QRD-RLS filter, block-weight-update, single-state-update parallel processing, low power, ASIC design |
23 | Kimihiro Ogawa, Michinari Kohno, Fusako Kitamura |
PASTEL: A Parameterized Memory Characterization System. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
automatic characterization, cell library, timing, power, ASIC, LSI, on-chip-memory |
23 | Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr |
Mapping multirate dataflow to complex RT level hardware models. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
multirate dataflow mapping, complex RT level hardware models, digital signal processing systems, algorithm development phase, data flow specification, RTL target architecture, HDL code generation, cycle based timing model, ASIC design complexity, multirate dataflow graphs, signal processing, hardware architecture |
23 | Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken |
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
semiconductor testing, stuck-fault testing, ASIC device, application specific integrated circuits, functional testing, IDDQ testing, delay-fault testing, scan testing |
23 | Jianzhong Shi, Akash Randhar, Dinesh Bhatia |
Macro Block Based FPGA Floorplanning. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design |
23 | Werner Brockmann, Thomas Kosch, Erik Maehle |
Rule-Based Routing in Massively Parallel Systems. |
PDP |
1996 |
DBLP DOI BibTeX RDF |
rule-based routing, rule-based specification, fixed rule-interpreter, interchangeable rule-base, universal routing chip, state-of-the-art VLSI-technologies, single-chip ASIC, parallel algorithms, interconnection network, knowledge based systems, multiprocessor interconnection networks, routing algorithms, network routing, massively parallel systems |
23 | Kevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens |
An Architectural Design For Parallel Fractal Compression. |
ASAP |
1996 |
DBLP DOI BibTeX RDF |
parallel fractal compression, quad-tree fractal encoding algorithm, ASIC parallel image processing, speed improvements, circuit levels, image processing, parallel architectures, data compression, image coding, encoding, application specific integrated circuits, fractals, architectural design, gray-scale images, archival storage, encoding algorithm |
23 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Low power realization of FIR filters using multirate architectures. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips |
23 | Eric W. Johnson, Jay B. Brockman |
Sensitivity analysis of iterative design processes. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Design Process Improvement, ASIC, Sensitivity Analysis |
23 | Stuart W. Daniel, Jennifer Rexford, James W. Dolter, Kang G. Shin |
A programmable routing controller for flexible communications in point-to-point networks. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
programmable routing controller, flexible communications, communication characteristics, custom ASIC, programmable processor, multiple routing-switching microcode routines, multiprocessor interconnection networks, packet switching, packet switching, application specific integrated circuits, wormhole switching, programmable controllers, firmware, performance requirements, virtual cut-through switching, point-to-point networks |
23 | Jean Paul Calvez, Olivier Pasquier |
Performance assessment of embedded Hw/Sw systems. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
embedded Hw/Sw systems, VLSI components, heterogeneous multiprocessor architectures, complex real-time applications, performance indexes, real-time event occurrences, software tasks, hardware functions, real-time performance analyzer, MCSE methodology, performance evaluation, real-time systems, VLSI, systems analysis, application specific integrated circuits, ASIC, performance assessment, event trace |
23 | Harry Hollander, Bradley S. Carlson, Toby D. Bennett |
Synthesis of SEU-tolerant ASICs using concurrent error correction. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
radiation hardening (electronics), SEU-tolerant ASIC synthesis, single error correction/double error detection Hamming code, delay overhead, memory element set partitioning, error correction codes, sequential circuits, sequential circuit, application specific integrated circuits, logic CAD, circuit layout CAD, single event upsets, logic partitioning, Hamming codes, fault tolerant design, area overhead, memory elements, design experiments, concurrent error correction |
23 | Puneet Sawhney, Haroon Rasheed |
Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators |
23 | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
Synchronization of communicating modules and processes in high level synthesis. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
communicating modules, object oriented design framework, nonblocking channel, real life image processing, synchronization, high level synthesis, high level synthesis, application specific integrated circuits, synchronisation, object-oriented methods, component reuse, ASIC designs, image processing equipment |
23 | Jay K. Adams, Donald E. Thomas |
Multiple-process behavioral synthesis for mixed hardware-software systems. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis |
21 | Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy 0001, Ranjani Narayan |
An Input Triggered Polymorphic ASIC for H.264 Decoding. |
ASAP |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Wagner Vieira Silvério, Janaína Domingues Costa, João Leonardo Fragoso, Julio Leão Silva Jr. |
Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
communication filters, digital communications, area optimization |
21 | Takeshi Sugawara 0001, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
High-performance ASIC implementations of the 128-bit block cipher CLEFIA. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Jalpa Shah, Houri Johari, Ajit Sharma, Farrokh Ayazi |
CMOS ASIC for MHz silicon BAW gyroscope. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Akashi Satoh |
ASIC hardware implementations for 512-bit hash function Whirlpool. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Simon Heinzle, Olivier Saurer, Sebastian Axmann, Diego Browarnik, Andreas Schmidt, Flavio Carbognani, Peter Luethi, Norbert Felber, Markus H. Gross |
A transform, lighting and setup ASIC for surface splatting. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Tong Gan, Kristof Denolf, Gauthier Lafruit, Iole Moccagatta, Antoine Dejonghe, Gregory Lenoir |
Modelling Energy Consumption of an ASIC MPEG-4 Simple Profile Encoder. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici |
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Bhavna Agrawal, Jeffrey G. Hemmett, Karl K. Moody, David B. White |
Techniques to address increased dimensionality of ASIC library design. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Mohammed Sayed, Ihab Amer, Wael M. Badawy |
Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Darshana Patel, Radu Muresan |
Triple-DES ASIC Module for a Power-Smart System-on-Chip Architecture. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Patrick de la Hamette, Gerhard Tröster |
FingerMouse - Architecture of an ASIC-based Mobile Stereovision Smart Camera. |
ISWC |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Siva Embanath, Ramakrishnan Venkata |
Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG). |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Leibo Liu, Hongying Meng, Milin Zhang 0001 |
An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Jin Park, Jeong-Tae Hwang, Young-Chul Kim 0001 |
FPGA and ASIC Implementation of ECC Processor for Security on Medical Embedded System. |
ICITA (2) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Tianpei Zhang, Sachin S. Sapatnekar |
Buffering global interconnects in structured ASIC design. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Joachim Neves Rodrigues, Matthias Kamuf, Hugo Hedberg, Viktor Öwall |
A Manual on ASIC Front to Back End Design Flow. |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton |
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon |
Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
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