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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 845 occurrences of 538 keywords
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Results
Found 5134 publication records. Showing 5134 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner |
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith |
An Application Specific Memory Characterization Technique for Co-processor Accelerators. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Angelos D. Keromytis, Jason L. Wright, Theo de Raadt, Matthew Burnside |
Cryptography as an operating system service: A case study. |
ACM Trans. Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
authentication, digital signatures, Encryption, hash functions, cryptographic protocols |
28 | Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, Johannes Wolkerstorfer |
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller. |
CHES |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Sunil Kim |
Pattern Matching Acceleration for Network Intrusion Detection Systems. |
SAMOS |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Young-Il Kim, Chong-Min Kyung |
Automatic translation of behavioral testbench for fully accelerated simulation. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Kenneth J. Turner, Qian Bing |
Protocol Techniques for Testing Radiotherapy Accelerators. |
FORTE |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein |
Reconfigurable Computing: A New Business Model and its Impact on SoC Design. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar |
Simulation of a Digital Neuro-Chip for Spiking Neural Networks. |
IJCNN (4) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001 |
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. |
CODES |
1997 |
DBLP DOI BibTeX RDF |
structural programmable co-processors, design space exploration, performance estimation |
28 | Jason Cong, John Peck |
On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002 |
Two-Level Hardware/Software Partitioning Using CoDe-X. |
ECBS |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002 |
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. |
CODES |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002, Helmut Reinig |
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Wen Su, Ling Wang, Menghao Su, Su Liu |
A Processor-DMA-Based Memory Copy Hardware Accelerator. |
NAS |
2011 |
DBLP DOI BibTeX RDF |
memory copy, accelerator, processor, DMA |
27 | John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank |
A Task-Centric Memory Model for Scalable Accelerator Architectures. |
IEEE Micro |
2010 |
DBLP DOI BibTeX RDF |
software coherence, parallel architecture, accelerator, memory model |
27 | Diem Tran, Thi To, Thuan Huynh, Phuong Nguyen |
Designing a Harware Accelerator for Face Recognition Using Vector Quantization and Principal Component Analysis as a Component of SoPC. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
DSP using FPGA, Face Recognition, PCA, Vector Quantization, Hardware Accelerator, SoPC |
27 | Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic |
MemTracker: An accelerator for memory debugging and monitoring. |
ACM Trans. Archit. Code Optim. |
2009 |
DBLP DOI BibTeX RDF |
memory access monitoring, debugging, Accelerator |
27 | Cui-Xia Li, Wei-Ming Liu 0003, Yi Tang |
A New 12-channel Hand-Held GPS Accelerator Design. |
NCM |
2009 |
DBLP DOI BibTeX RDF |
GPS accelerator, DCO, Correlator, PLL, LUT |
27 | Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing |
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
temporal parallelism, macro-pipeline, FPGA accelerator, matrix multiplication |
27 | Shay Horovitz, Danny Dolev |
Collabory: A Collaborative Throughput Stabilizer & Accelerator for P2P Protocols. |
WETICE |
2008 |
DBLP DOI BibTeX RDF |
Collabory, Stable, Collaboration, Stabilizer, P2P, Throughput, Bandwidth, Accelerator |
27 | Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq |
A Hardware Accelerator for Maze Routing. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
banked memory, three-stage pipelines, hardware accelerator, circuit layout CAD, maze routing |
27 | Paul Kenyon, Prathima Agrawal, Sharad C. Seth |
High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. |
MICRO |
1990 |
DBLP BibTeX RDF |
front-end DAG compiler, hand vs. compiled microcode, microcode compiler, programming environment for CAD, space/time overhead, code generation, hardware accelerator, performance data |
27 | Rami G. Melhem |
A Systolic Accelerator for the Iterative Solution of Sparse Linear Systems. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
stripe structures, preconditioned conjugate gradient, iterative solution, nonzero elements, systolic accelerator, computationally irregular problems, systolic networks, parallel processing, iterative methods, systolic arrays, matrix algebra, buffering, cellular arrays, sparse matrix, special purpose computers, sparse linear systems, data movement |
26 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
26 | Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke |
Modulo scheduling for highly customized datapaths to increase hardware reusability. |
CGO |
2008 |
DBLP DOI BibTeX RDF |
programmable asic, modulo scheduling, loop accelerator |
26 | Daniel Dietterle |
Embedded system protocol design flow based on SDL: from specification to hardware/software implementation. |
SimuTools |
2008 |
DBLP DOI BibTeX RDF |
protocol accelerator, embedded systems, SDL, protocol engineering, IEEE 802.15.3 |
26 | Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto |
A Coprocessor for the Final Exponentiation of the eta T Pairing in Characteristic Three. |
WAIFI |
2007 |
DBLP DOI BibTeX RDF |
final exponentiation, FPGA, hardware accelerator, ? T pairing, characteristic three |
26 | Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem |
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique |
26 | Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto |
An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation. |
IEEE Symposium on Computer Arithmetic |
2007 |
DBLP DOI BibTeX RDF |
nT pairing, FPGA, elliptic curve, hardware accelerator, Tate pairing, characteristic three |
26 | Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto |
Arithmetic Operators for Pairing-Based Cryptography. |
CHES |
2007 |
DBLP DOI BibTeX RDF |
FPGA, elliptic curve, hardware accelerator, finite field arithmetic, ? T pairing |
26 | Cristian Coarfa, Peter Druschel, Dan S. Wallach |
Performance analysis of TLS Web servers. |
ACM Trans. Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
RSA accelerator, secure Web servers, Internet, e-commerce, TLS |
26 | Kenneth J. Turner |
Test generation for radiotherapy accelerators. |
Int. J. Softw. Tools Technol. Transf. |
2005 |
DBLP DOI BibTeX RDF |
Lotos (Language Of Temporal Ordering Specification), Test generation, Accelerator, Radiotherapy |
26 | Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner |
Exploring the design space of LUT-based transparent accelerators. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
accelerator design, embedded processing, efficient computation |
26 | Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto |
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. |
CHES |
2005 |
DBLP DOI BibTeX RDF |
tower fields, hardware accelerator, Tate pairing, characteristic three |
26 | Guido Fioretti |
The investment acceleration principle revisited by means of a neural network. |
Neural Comput. Appl. |
2004 |
DBLP DOI BibTeX RDF |
Accelerator, Self-organising maps (SOM), Investment |
26 | Johann Großschädl |
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip. |
ACSAC |
2000 |
DBLP DOI BibTeX RDF |
RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency |
26 | Youngmin Hur, Stephen A. Szygenda |
Special purpose array processor for digital logic simulation. |
Annual Simulation Symposium |
1995 |
DBLP DOI BibTeX RDF |
special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost |
26 | Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda |
Statistics on concurrent fault and design error simulation. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
concurrent fault/design error simulation, design error simulation processes, c-sim, gate level concurrent simulator, event based statistics, gate evaluation statistics, simulator developers, hardware accelerator designers, design options, parallel algorithms, formal verification, circuit analysis computing, design verification, memory requirements, experimental data, concurrent simulators |
26 | Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang |
VLSI design of densely-connected array processors. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets |
26 | Dejan Raskovic, Emil Jovanov, Aleksandar Janicijevic, Veljko M. Milutinovic |
An implementation of hash based ATM router chip. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
ATM router chip, hash based, large size routing tables, hash-based hardware accelerator, standard RAM, asynchronous transfer mode, storage management, telecommunication network routing, file organisation, telecommunication computing, hardware support |
20 | Achraf El Bouazzaoui, Abdelkader Hadjoudja, Omar Mouhib, Nazha Cherkaoui |
FPGA-based ML adaptive accelerator: A partial reconfiguration approach for optimized ML accelerator utilization. |
Array |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Hyeong-Ju Kang, Byung-Do Yang |
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning. |
Sensors |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Jisu Kwon, Daejin Park |
Work-in-Progress: Micro-Accelerator-in-the-Loop Framework for MCU Integrated Accelerator Peripheral Fast Prototyping. |
EMSOFT |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Junfei Tang, Luming Zhang |
An Adaptive Feature Recognition Algorithm and Its Hardware Accelerator for Arc Fault Recognition: The hardware accelerator of the algorithm is improved from the discrete wavelet transform algorithm and is used for power grid arc fault detection. |
ICCAI |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Venkata Krishnan, Olivier Serres, Michael Blocksome |
COnfigurable Network Protocol Accelerator (COPA) † : An Integrated Networking/Accelerator Hardware/Software Framework. |
Hot Interconnects |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Zhengyu Chen 0002, Hai Zhou 0001, Jie Gu 0001 |
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Zhengyu Chen 0002, Hai Zhou 0001, Jie Gu 0001 |
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. |
ICCD |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Bain Syrowik, Blair Fort, Stephen Dean Brown |
Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. |
HEART |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano |
Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. |
FPL |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Jonas Hahnfeld, Christian Terboven, James Price, Hans-Joachim Pflug, Matthias S. Müller |
Evaluation of Asynchronous Offloading Capabilities of Accelerator Programming Models for Multiple Devices. |
WACCPD@SC |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Jan Gray |
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator. |
CoRR |
2016 |
DBLP BibTeX RDF |
|
20 | Jan Gray |
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator. |
FCCM |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Thilo Friedrich |
Conceptual reasoning in the development of particle accelerator control systems: A case study on controls for a novel accelerator design. |
SoSE |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Akihiro Hayashi, Jun Shirako, Ettore Tiotto, Robert Ho, Vivek Sarkar |
Exploring Compiler Optimization Opportunities for the OpenMP 4.× Accelerator Model on a POWER8+GPU Platform. |
WACCPD@SC |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Masahiro Nakao, Hitoshi Murai, Takenori Shimosaka, Akihiro Tabuchi, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato |
XcalableACC: extension of XcalableMP PGAS language using OpenACC for accelerator clusters. |
WACCPD@SC |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Seyong Lee, Jeffrey S. Vetter |
OpenARC: extensible OpenACC compiler framework for directive-based accelerator programming study. |
WACCPD@SC |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Vladimir Korkhov, A. Ivanov, Natalia V. Kulabukhova, Alexander V. Bogdanov, Serge N. Andrianov |
Virtual Accelerator: Distributed Environment for Modeling Beam Accelerator Control System. |
ICCSA (6) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Michael J. Lyons 0003, Mark Hempstead, Gu-Yeon Wei, David M. Brooks |
The accelerator store: A shared memory framework for accelerator-based systems. |
ACM Trans. Archit. Code Optim. |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Michael J. Lyons 0003, Mark Hempstead, Gu-Yeon Wei, David M. Brooks |
The Accelerator Store framework for high-performance, low-power accelerator-based systems. |
IEEE Comput. Archit. Lett. |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Luciano Burgazzi, Paolo Pierini |
Reliability studies of a high-power proton accelerator for accelerator-driven system applications for nuclear waste transmutation. |
Reliab. Eng. Syst. Saf. |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Zefu Dai, Nick Ni, Jianwen Zhu |
A 1 cycle-per-byte XML parsing accelerator. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
bart, schema validation, string comparison, xml parsing, ethernet, bloom filter, dom, tree construction |
19 | Pierre Michaud, Yiannakis Sazeides, André Seznec |
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
activity migration, sequential performance, power, multicore, temperature, cache misses, manycore |
19 | Michael Wolfe |
Implementing the PGI Accelerator model. |
GPGPU |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Jeffrey Allred, Jack Coyne, William Lynch, Vincent Natoli, Joseph Grecco, Joel Morrissette |
Smith-Waterman implementation on a FSB-FPGA module using the Intel Accelerator Abstraction Layer. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan |
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel |
Tradeoffs in designing accelerator architectures for visual computing. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic |
FlexiTaint: A programmable accelerator for dynamic taint propagation. |
HPCA |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Samar Yazdani, Joel Cambonie, Bernard Pottier |
Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems. |
ARC |
2008 |
DBLP DOI BibTeX RDF |
coarse-grain architecture, shared-memory programming model, embedded systems, multimedia applications |
19 | Samar Yazdani, Joel Cambonie, Bernard Pottier |
Reconfiguralbe multimedia accelerator for mobile systems. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Fernando Pardo, Paula López Martinez 0001, Diego Cabello |
FPGA-based hardware accelerator of the heat equation with applications on infrared thermography. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Patrick Akl, Andreas Moshovos |
Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. |
HiPEAC |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Azzedine Boukerche, Jan Mendonca Correa, Alba Cristina Magalhaes Alves de Melo, Ricardo P. Jacobi, Adson Ferreira da Rocha |
An FPGA-Based Accelerator for Multiple Biological Sequence Alignment with DIALIGN. |
HiPC |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Mariano Fons, Francisco Fons, Enrique Cantó, Mariano López |
Design of a hardware accelerator for fingerprint alignment. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Qing Wang 0045, Wenbo Shen, Yu Li, Zhenbo Zhu |
Design of IP Media Accelerator. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Guo-An Jian, Chih-Da Chien, Jiun-In Guo |
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Bruno Zatt, Valter Ferreira, Luciano Volcan Agostini, Flávio Rech Wagner, Altamiro Amadeu Susin, Sergio Bampi |
Motion Compensation Hardware Accelerator Architecture for H.264/AVC. |
PSIVT |
2007 |
DBLP DOI BibTeX RDF |
MPEG-4 AVC, Video Coding, H.264/AVC, Motion Compensation, Hardware Acceleration |
19 | Bart de Ruijsscher, Georgi Gaydadjiev, Jeroen Lichtenauer, Emile A. Hendriks |
FPGA accelerator for real-time skin segmentation. |
ESTIMedia |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-Ming Huang |
A cost-effective reconfigurable accelerator for platform-based SOC design. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Akila Gothandaraman, G. Lee Warren, Gregory D. Peterson, Robert J. Harrison |
Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Young-Su Kwon, Chong-Min Kyung |
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Joon Woo Cho, Hyun-Jin Choi, Seung-Ho Lim, Kyu Ho Park |
A Content Delivery Accelerator in Data-Intensive Servers. |
NPC |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Philippe Marchand, Purnendu Sinha |
A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems. |
SAMOS |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mona Safar, M. Watheq El-Kharashi, Ashraf Salem |
FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hongtu Jiang, Håkan Ardö, Viktor Öwall |
Hardware accelerator design for video segmentation with multi-modal background modelling. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Yan-Chen Lu, Chun-Fu Shen, Chi-Kuang Chen, Ju-Lung Fann |
Performance-driven optimization for video accelerator design [video coding]. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin |
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mona Safar, M. Watheq El-Kharashi, Ashraf Salem |
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
19 | William D. Smith, Austars R. Schnore |
Towards an RCC-Based Accelerator for Computational Fluid Dynamics Applications. |
J. Supercomput. |
2004 |
DBLP DOI BibTeX RDF |
re-configurable computing applications, computational fluid dynamics |
19 | John F. Keane, Christopher Bradley, Carl Ebeling |
A compiled accelerator for biological cell signaling simulations. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
simulation, reconfigurable hardware, cell, biology, reactions |
19 | Lie-Quan Lee, Lixin Ge, Marc Kowalski, Zenghai Li, Cho-Kuen Ng, Gregory L. Schussman, Michael Wolf, Kwok Ko |
Solving Large Sparse Linear Systems in End-to-end Accelerator Structure Simulations. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Binu K. Mathew, Al Davis |
A loop accelerator for low power embedded VLIW processors. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, low power design, VLIW |
19 | Giovanni Danese, Ivo De Lotto, Francesco Leporati, M. Scaricabarozzi, Alvaro Spelgatti |
An Accelerator for Double Precision Floating Point Operations. |
PDP |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Marco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti |
A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator. |
DSD |
2003 |
DBLP DOI BibTeX RDF |
|
19 | John A. Nestor |
FPGA Implementation of a Maze Routing Accelerator. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Binu K. Mathew, Al Davis, Zhen Fang 0002 |
A low-power accelerator for the SPHINX 3 speech recognition system. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
embedded systems, speech recognition, low power design, ASIC, special purpose hardware |
19 | Hong-Yi Huang, Shih-Lun Chen |
Threshold triggers and accelerator for deep submicron interconnection. |
APCCAS (2) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Edwin A. Hakkennes, Stamatis Vassiliadis |
Multimedia Execution Hardware Accelerator. |
J. VLSI Signal Process. |
2001 |
DBLP DOI BibTeX RDF |
multimedia architectures, multimedia instruction set, multimedia processors, compound instructions, multimedia, hardware accelerators, subword parallelism, SIMD processors, vector architectures |
19 | Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott |
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. |
ISC |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi |
Hardware Accelerator for Subgraph Isomorphism Problems. |
FCCM |
2000 |
DBLP DOI BibTeX RDF |
|
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