|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 664 occurrences of 364 keywords
|
|
|
Results
Found 985 publication records. Showing 985 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Tobias Eibach, Enrico Pilz, Gunnar Völkel |
Attacking Bivium Using SAT Solvers. |
SAT |
2008 |
DBLP DOI BibTeX RDF |
Rsat, Bivium, Gröbner Base, Cryptography, Application, Stream Cipher, BDD, SAT Solver, eSTREAM, Trivium |
27 | Constantinos Bartzis, Tevfik Bultan |
Efficient BDDs for bounded arithmetic constraints. |
Int. J. Softw. Tools Technol. Transf. |
2006 |
DBLP DOI BibTeX RDF |
Model checking, BDD, Integer arithmetic, SMV |
27 | Jianbin Tan, George S. Avrunin, Lori A. Clarke |
Managing space for finite-state verification. |
ICSE |
2006 |
DBLP DOI BibTeX RDF |
FLAVERS, ZDD, BDD, finite-state verification, LTSA |
27 | Toshiaki Miyazaki |
Boolean formulation for sensor allocation problem and its efficient solver. |
MidSens |
2006 |
DBLP DOI BibTeX RDF |
combinational optimization, BDD, dynamic allocation |
27 | Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain |
On Partitioning and Symbolic Model Checking. |
FM |
2005 |
DBLP DOI BibTeX RDF |
state partitioning, BDD, Symbolic Model Checking, CTL |
27 | Tuba Yavuz-Kahveci, Tevfik Bultan |
A symbolic manipulator for automated verification of reactive systems with heterogeneous data types. |
Int. J. Softw. Tools Technol. Transf. |
2003 |
DBLP DOI BibTeX RDF |
Composite representation, BDD, Symbolic model checking, Presburger arithmetic |
27 | Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi |
A Symbolic Approach for the Combined Solution of Scheduling and Allocation. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
scheduling, high-level synthesis, automata, BDD, allocation |
27 | Amir Pnueli, Ofer Strichman, Michael Siegel |
The Code Validation Tool CVT: Automatic Verification of a Compilation Process. |
Int. J. Softw. Tools Technol. Transf. |
1998 |
DBLP DOI BibTeX RDF |
Code validation, BDD, Industrial application, Compiler verification, Translation validation |
27 | Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
Logic synthesis for large pass transistor circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
logic synthesis, BDD, Pass transistor logic |
27 | Taisuke Sato |
Statistical Learning of Probabilistic BDDs. |
SAGA |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Eli Arbel, Oleg Rokhlenko, Karen Yorav |
SAT-based synthesis of clock gating functions using 3-valued abstraction. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Vadim Lyubashevsky, Daniele Micciancio |
On Bounded Distance Decoding, Unique Shortest Vectors, and the Minimum Distance Problem. |
CRYPTO |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Sa'ed Abed, Otmane Aït Mohamed, Ghiath Al Sammane |
Reachability analysis using multiway decision graphs in the HOL theorem prover. |
SAC |
2008 |
DBLP DOI BibTeX RDF |
reachability analysis, HOL, multiway decision graphs |
27 | Marcílio Mendonça, Andrzej Wasowski, Krzysztof Czarnecki 0001, Donald D. Cowan |
Efficient compilation techniques for large scale feature models. |
GPCE |
2008 |
DBLP DOI BibTeX RDF |
formal verification, model-driven development, software-product lines, configuration, feature modeling |
27 | P. W. Chandana Prasad, Bruce Mills, Ali Assi 0001, S. M. N. Arosha Senanayake, V. C. Prasad |
Evaluation time Estimation for Pass Transistor Logic circuits. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Gianpiero Cabodi, Sergio Nocco, Stefano Quer |
Are BDDs still alive within sequential verification? |
Int. J. Softw. Tools Technol. Transf. |
2005 |
DBLP DOI BibTeX RDF |
Approximate-reachability, Model checking, Binary Decision Diagrams, Satisfiability solvers |
27 | Enric Pastor, Marco A. Peña, Marc Solé |
TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems. |
CAV |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Richard Mark Downing |
Evolving binary decision diagrams using implicit neutrality. |
Congress on Evolutionary Computation |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill |
A New Reachability Algorithm for Symmetric Multi-processor Architecture. |
ATVA |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Viresh Paruthi, Christian Jacobi 0002, Kai Weber 0001 |
Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Wolfgang Lenders, Christel Baier |
Genetic Algorithms for the Variable Ordering Problem of Binary Decision Diagrams. |
FOGA |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Kairong Qian, Albert Nymeyer, Steven Susanto |
Abstraction-Guided Model Checking Using Symbolic IDA* and Heuristic Synthesis. |
FORTE |
2005 |
DBLP DOI BibTeX RDF |
model approximations, Formal verification, heuristic search, symbolic model checking, data abstractions |
27 | Shan-Tai Chen, Shun-Shii Lin, Li-Te Huang, Chun-Jen Wei |
Towards the Exact Minimization of BDDs-An Elitism-Based Distributed Evolutionary Algorithm. |
J. Heuristics |
2004 |
DBLP DOI BibTeX RDF |
DEBEA, EBEA, paralleled algorithm, evolutionary algorithm, Binary Decision Diagram, heuristic algorithm |
27 | Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler |
Disjoint Sum of Product Minimization by Evolutionary Algorithms. |
EvoWorkshops |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Rune Møller Jensen |
CLab: A C++ Library for Fast Backtrack-Free Interactive Product Configuration.. |
CP |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Hung-Yau Lin, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo |
An Efficient Perfect Algorithm for Memory Repair Problems. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Alan Mishchenko |
Fast computation of symmetries in Boolean functions. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
27 | E. Allen Emerson, Thomas Wahl |
On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking. |
CHARME |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Chao Wang 0001, Gary D. Hachtel, Fabio Somenzi |
The Compositional Far Side of Image Computation. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
Model checking, Binary Decision Diagrams, Symbolic, image computation |
27 | D. Michael Miller, Rolf Drechsler |
Augmented Sifting of Multiple-Valued Decision Diagrams. |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Nina Amla, Robert P. Kurshan, Kenneth L. McMillan, Ricardo H. Medel |
Experimental Analysis of Different Techniques for Bounded Model Checking. |
TACAS |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Aiqun Cao, Cheng-Kok Koh |
Non-Crossing OBDDs for Mapping to Regular Circuit Structures. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Bijan Alizadeh, Mohammad Reza Kakoee |
Using Integer Equations for High Level Formal Verification Property Checking. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Albert Nymeyer, Kairong Qian |
Heuristic Search Algorithms Based on Symbolic Data Structures. |
Australian Conference on Artificial Intelligence |
2003 |
DBLP DOI BibTeX RDF |
shortest path, Heuristic search, binary decision diagrams |
27 | Per Bjesse |
Industrial Model Checking Based on Satisfiability Solvers. |
SPIN |
2002 |
DBLP DOI BibTeX RDF |
|
27 | HyungWon Kim 0001, John P. Hayes |
Delay fault testing of IP-based designs via symbolic path modeling. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Jaco Geldenhuys, Antti Valmari |
Techniques for Smaller Intermediary BDDs. |
CONCUR |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Michael J. C. Gordon |
Reachability Programming in HOL98 Using BDDs. |
TPHOLs |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Christoph Scholl 0001, Bernd Becker 0001 |
On the Generation of Multiplexer Circuits for Pass Transistor Logic. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Aarti Gupta, Zijiang Yang 0006, Pranav Ashar, Anubhav Gupta 0001 |
SAT-Based Image Computation with Application in Reachability Analysis. |
FMCAD |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Xinyu Zang, Hairong Sun, Kishor S. Trivedi |
Dependability Analysis of Distributed Computer Systems with Imperfect Coverage. |
FTCS |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Modeling design constraints and biasing in simulation using BDDs. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha |
An Exact Input Encoding Algorithm for BDDs Representing FSMs. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
input encoding, finite state machines, binary decision diagrams, multi-valued decision diagrams |
27 | Gianpiero Cabodi, Paolo Camurati, Stefano Quer |
Improved reachability analysis of large finite state machines. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Sequential Logic Synthesis and Verification |
26 | Carsten Sinz, Wolfgang Küchlin, Dieter Feichtinger, Georg Görtler |
Checking Consistency and Completeness of On-Line Product Manuals. |
J. Autom. Reason. |
2006 |
DBLP DOI BibTeX RDF |
problem encoding, BDD-techniques, SAT, real-world applications |
26 | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
Incremental logic rectification. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
incremental logic rectification, incorrect combinational circuit, symbolic BDD techniques, sequence of partial corrections, circuits with multiple errors, general single-gate correction, structural correspondence, ISCAS85 benchmark circuits, error region pruning, specification, implementation, logic CAD, VLSI design, hybrid approach |
26 | Florian Krohm, Andreas Kuehlmann, Arjen Mets |
The use of random simulation in formal verification. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
random simulation, BDD-based verification, counter example pattern, design partitioning, Boolean reasoning, formal verification, formal verification, hardware designs, functional equivalence |
26 | Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò |
Reliability evaluation of combinational logic circuits by symbolic simulation. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability |
26 | Martin Dietzfelbinger, Stefan Edelkamp |
Perfect Hashing for State Spaces in BDD Representation. |
KI |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Andrei Rimsa, Luis E. Zárate, Mark A. J. Song |
Handling Large Formal Context Using BDD - Perspectives and Limitations. |
ICFCA |
2009 |
DBLP DOI BibTeX RDF |
Formal Concept Analysis, Binary Decision Diagrams, Formal Context, Formal Concept |
26 | Ken Friis Larsen |
A MuDDy Experience-ML Bindings to a BDD Library. |
DSL |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Ondrej Lhoták, Laurie J. Hendren |
Evaluating the benefits of context-sensitive points-to analysis using a BDD-based implementation. |
ACM Trans. Softw. Eng. Methodol. |
2008 |
DBLP DOI BibTeX RDF |
Interprocedural program analysis, cast safety analysis, Java, binary decision diagrams, context sensitivity, points-to analysis, call graph construction |
26 | Ondrej Lhoták, Laurie J. Hendren |
Relations as an abstraction for BDD-based program analysis. |
ACM Trans. Program. Lang. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Boolean formula satisfiability, physical domain assignment, Java, program analysis, Binary decision diagrams, language design, relations, points-to analysis |
26 | Vasilis Samoladas |
Improved BDD Algorithms for the Simulation of Quantum Circuits. |
ESA |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Xiangyu Luo, Kaile Su, Abdul Sattar 0001, Yan Chen |
Solving Sum and Product Riddle via BDD-Based Model Checking. |
Web Intelligence/IAT Workshops |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Peter Hawkins, Peter J. Stuckey |
A Hybrid BDD and SAT Finite Domain Constraint Solver. |
PADL |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Gopal Paul, Sambhu Nath Pradhan, Ajit Pal, Bhargab B. Bhattacharya |
Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Combining ordered best-first search with branch and bound for exact BDD minimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Junhao Shi, Görschwin Fey, Rolf Drechsler |
Bridging fault testability of BDD circuits. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Jaco van de Pol, Olga Tveretina |
A BDD-Representation for the Logic of Equality and Uninterpreted Functions. |
MFCS |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Sumio Morioka, Akashi Satoh |
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Farn Wang, Karsten Schmidt 0004, Fang Yu 0001, Geng-Dian Huang, Bow-Yaw Wang |
BDD-Based Safety-Analysis of Concurrent Software with Pointer Data Structures Using Graph Automorphism Symmetry Reduction. |
IEEE Trans. Software Eng. |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ondrej Lhoták, Laurie J. Hendren |
Jedd: a BDD-based relational extension of Java. |
PLDI |
2004 |
DBLP DOI BibTeX RDF |
boolean formula satisfiability, Java, program analysis, binary decision diagrams, language design, relations |
26 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
An improved branch and bound algorithm for exact BDD minimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Combination of Lower Bounds in Exact BDD Minimization. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
26 | John V. Franco, Michal Kouril, John S. Schlipf, Jeffrey Ward, Sean A. Weaver, Michael R. Dransfield, W. Mark Vanfleet |
SBSAT: a State-Based, BDD-Based Satisfiability Solver. |
SAT |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Guoqiang Pan, Ulrike Sattler, Moshe Y. Vardi |
BDD-Based Decision Procedures for K. |
CADE |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Sumio Morioka, Akashi Satoh |
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Rolf Drechsler, Wolfgang Günther 0001, Fabio Somenzi |
Using lower bounds during dynamic BDD minimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Wolfgang Günther 0001, Rolf Drechsler |
Implementation of Read- k-times BDDs on Top of Standard BDD Packages. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Rolf Drechsler, Nicole Drechsler, Wolfgang Günther 0001 |
Fast exact minimization of BDD's. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan |
Sibling-substitution-based BDD minimization using don't cares. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Holger Hermanns, Markus Siegle |
Bisimulation Algorithms for Stochastic Process Algebras and Their BDD-Based Implementation. |
ARTS |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Masahito Kurihara, Hisashi Kondo |
Heuristics and Experiments on BDD Representation of Boolean Functions for Expert Systems in Software Verification Domains. |
Australian Joint Conference on Artificial Intelligence |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Macha Nikolskaïa, Antoine Rauzy, David James Sherman |
Almana: A BDD Minimization Tool Integrating Heuristic and Rewriting Methods. |
FMCAD |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Abelardo Pardo, Gary D. Hachtel |
Incremental CTL Model Checking Using BDD Subsetting. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band |
26 | Nils Klarlund |
An n log n Algorithm for Online BDD Refinement. |
CAV |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Bwolen Yang, David R. O'Hallaron |
Parallel Breadth-First BDD Construction. |
PPoPP |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Ashvin Dsouza, Bard Bloom |
Generating BDD Models for Process Algebra Terms. |
CAV |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
A Comparison of Architectures for Various Decision Diagram Machines. |
ISMVL |
2010 |
DBLP DOI BibTeX RDF |
QDD, QRBDD, QRMDD, Heterogeneous MDD, Homogeneous MDD, Branching Machine, MDD, BDD |
18 | María Agustina Cibrán |
Translating BPMN Models into UML Activities. |
Business Process Management Workshops |
2008 |
DBLP DOI BibTeX RDF |
UML Activities, MDA, Model Transformations, BDD, MDE, BPMN, ATL |
18 | Felix Reimann, Michael Glaß, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich |
Symbolic voter placement for dependability-aware system synthesis. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
mttuf, bdd, system synthesis, voter, mean time to failure, mttf |
18 | Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda |
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. |
EvoWorkshops |
2008 |
DBLP DOI BibTeX RDF |
microprocessor, BDD, MOEA, path-delay testing |
18 | Scott W. Ambler |
Test-Driven Development of Relational Databases. |
IEEE Softw. |
2007 |
DBLP DOI BibTeX RDF |
database refactoring, test-driven database design, behavior-driven development, relational database, test-driven development, TDD, TDD, BDD, database testing |
18 | Rongjie Yan, Guangyuan Li, Wenliang Zhang, Yunquan Peng |
Improvements for the Symbolic Verification of Timed Automata. |
FORTE |
2007 |
DBLP DOI BibTeX RDF |
verification, BDD, timed systems, symbolic method |
18 | Chao Wang 0001, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi |
Compositional SCC Analysis for Language Emptiness. |
Formal Methods Syst. Des. |
2006 |
DBLP DOI BibTeX RDF |
language emptiness, model checking, BDD, LTL, abstraction refinement |
18 | Dirk Beyer 0001 |
Relational programming with CrocoPat. |
ICSE |
2006 |
DBLP DOI BibTeX RDF |
pattern matching, relational algebra, BDD, transitive closure, graph models, software analysis, predicate logic |
18 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri |
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
BDD, leakage, ADD |
18 | Yung-Ruei Chang, Suprasad V. Amari, Sy-Yen Kuo |
Computing System Failure Frequencies and Reliability Importance Measures Using OBDD. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Failure frequency, reliability importance measure, imperfect coverage, fault tolerance, BDD, system availability |
18 | Robert F. Damiano, James H. Kukula |
Checking satisfiability of a conjunction of BDDs. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
satisfiability, BDD |
18 | Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller |
Multi-Output Timed Shannon Circuits. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
Low Power, Logic Synthesis, BDD |
18 | Shin-ichi Minato |
Zero-suppressed BDDs and their applications. |
Int. J. Softw. Tools Technol. Transf. |
2001 |
DBLP DOI BibTeX RDF |
Boolean function, BDD, Combinatorial problem, VLSI CAD, ZBDD |
18 | Stefan Höreth |
A word-level graph manipulation package. |
Int. J. Softw. Tools Technol. Transf. |
2001 |
DBLP DOI BibTeX RDF |
Word-level, TUDD, BDD, Decision diagrams, BMD |
18 | Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho |
An Efficient Logic Equivalence Checker for Industrial Circuits. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
logic checking, ATPG, BDD, formal, combinational, functional verification, equivalence, MET |
18 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Automatic Vector Generation Using Constraints and Biasing. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
constraint, probability, partitioning, BDD, biasing, vector generation |
18 | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
Implementation of Multiple-Output Functions Using PQMDDs. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
Multiple-output logic function, PMDD, PQMDD, MDD, BDD |
18 | Frank Schmiedle, Wolfgang Günther 0001, Rolf Drechsler |
Dynamic Re-Encoding During MDD Minimization. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
variable grouping, MDD, BDD, sifting |
18 | Rolf Drechsler |
Preudo-Kronecker Expressions for Symmetric Functions. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
AND/EXOR, PSDKRO, 2-level minimization, Logic synthesis, BDD |
18 | Bernd Becker 0001, Martin Keim, Rolf Krieger |
Hybrid Fault Simulation for Synchronous Sequential Circuits. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
SOT, fault simulation, BDD, symbolic simulation, MOT |
18 | Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man |
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
supergate, prime-and-irredundant, ATPG, BDD |
Displaying result #101 - #200 of 985 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ >>] |
|