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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 664 occurrences of 364 keywords
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Results
Found 985 publication records. Showing 985 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Tobias Eibach, Enrico Pilz, Gunnar Völkel |
Attacking Bivium Using SAT Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing - SAT 2008, 11th International Conference, SAT 2008, Guangzhou, China, May 12-15, 2008. Proceedings, pp. 63-76, 2008, Springer, 978-3-540-79718-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Rsat, Bivium, Gröbner Base, Cryptography, Application, Stream Cipher, BDD, SAT Solver, eSTREAM, Trivium |
27 | Constantinos Bartzis, Tevfik Bultan |
Efficient BDDs for bounded arithmetic constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 8(1), pp. 26-36, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Model checking, BDD, Integer arithmetic, SMV |
27 | Jianbin Tan, George S. Avrunin, Lori A. Clarke |
Managing space for finite-state verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 28th International Conference on Software Engineering (ICSE 2006), Shanghai, China, May 20-28, 2006, pp. 152-161, 2006, ACM, 1-59593-375-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FLAVERS, ZDD, BDD, finite-state verification, LTSA |
27 | Toshiaki Miyazaki |
Boolean formulation for sensor allocation problem and its efficient solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MidSens ![In: Proceedings of the First International Workshop on Middleware for Sensor Networks, MidSens 2006, November 28, 2006, Melbourne, Australia, Co-located with Middleware 2006, pp. 49-54, 2006, ACM, 1-59593-424-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
combinational optimization, BDD, dynamic allocation |
27 | Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain |
On Partitioning and Symbolic Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FM ![In: FM 2005: Formal Methods, International Symposium of Formal Methods Europe, Newcastle, UK, July 18-22, 2005, Proceedings, pp. 497-511, 2005, Springer, 3-540-27882-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
state partitioning, BDD, Symbolic Model Checking, CTL |
27 | Tuba Yavuz-Kahveci, Tevfik Bultan |
A symbolic manipulator for automated verification of reactive systems with heterogeneous data types. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 5(1), pp. 15-33, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Composite representation, BDD, Symbolic model checking, Presburger arithmetic |
27 | Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi |
A Symbolic Approach for the Combined Solution of Scheduling and Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 237-242, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scheduling, high-level synthesis, automata, BDD, allocation |
27 | Amir Pnueli, Ofer Strichman, Michael Siegel |
The Code Validation Tool CVT: Automatic Verification of a Compilation Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 2(2), pp. 192-201, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Code validation, BDD, Industrial application, Compiler verification, Translation validation |
27 | Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
Logic synthesis for large pass transistor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 663-670, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
logic synthesis, BDD, Pass transistor logic |
27 | Taisuke Sato |
Statistical Learning of Probabilistic BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAGA ![In: Stochastic Algorithms: Foundations and Applications, 5th International Symposium, SAGA 2009, Sapporo, Japan, October 26-28, 2009. Proceedings, pp. 15, 2009, Springer, 978-3-642-04943-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Eli Arbel, Oleg Rokhlenko, Karen Yorav |
SAT-based synthesis of clock gating functions using 3-valued abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 198-204, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Vadim Lyubashevsky, Daniele Micciancio |
On Bounded Distance Decoding, Unique Shortest Vectors, and the Minimum Distance Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO 2009, 29th Annual International Cryptology Conference, Santa Barbara, CA, USA, August 16-20, 2009. Proceedings, pp. 577-594, 2009, Springer, 978-3-642-03355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Sa'ed Abed, Otmane Aït Mohamed, Ghiath Al Sammane |
Reachability analysis using multiway decision graphs in the HOL theorem prover. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 333-338, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reachability analysis, HOL, multiway decision graphs |
27 | Marcílio Mendonça, Andrzej Wasowski, Krzysztof Czarnecki 0001, Donald D. Cowan |
Efficient compilation techniques for large scale feature models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPCE ![In: Generative Programming and Component Engineering, 7th International Conference, GPCE 2008, Nashville, TN, USA, October 19-23, 2008, Proceedings, pp. 13-22, 2008, ACM, 978-1-60558-267-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
formal verification, model-driven development, software-product lines, configuration, feature modeling |
27 | P. W. Chandana Prasad, Bruce Mills, Ali Assi 0001, S. M. N. Arosha Senanayake, V. C. Prasad |
Evaluation time Estimation for Pass Transistor Logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 422-428, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Gianpiero Cabodi, Sergio Nocco, Stefano Quer |
Are BDDs still alive within sequential verification? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 7(2), pp. 129-142, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Approximate-reachability, Model checking, Binary Decision Diagrams, Satisfiability solvers |
27 | Enric Pastor, Marco A. Peña, Marc Solé |
TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 17th International Conference, CAV 2005, Edinburgh, Scotland, UK, July 6-10, 2005, Proceedings, pp. 424-428, 2005, Springer, 3-540-27231-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Richard Mark Downing |
Evolving binary decision diagrams using implicit neutrality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2005, 2-4 September 2005, Edinburgh, UK, pp. 2107-2113, 2005, IEEE, 0-7803-9363-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill |
A New Reachability Algorithm for Symmetric Multi-processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis, Third International Symposium, ATVA 2005, Taipei, Taiwan, October 4-7, 2005, Proceedings, pp. 26-38, 2005, Springer, 3-540-29209-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Viresh Paruthi, Christian Jacobi 0002, Kai Weber 0001 |
Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 114-128, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Wolfgang Lenders, Christel Baier |
Genetic Algorithms for the Variable Ordering Problem of Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOGA ![In: Foundations of Genetic Algorithms, 8th International Workshop, FOGA 2005, Aizu-Wakamatsu City, Japan, January 5-9, 2005, Revised Selected Papers, pp. 1-20, 2005, Springer, 3-540-27237-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Kairong Qian, Albert Nymeyer, Steven Susanto |
Abstraction-Guided Model Checking Using Symbolic IDA* and Heuristic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2005, 25th IFIP WG 6.1 International Conference, Taipei, Taiwan, October 2-5, 2005, Proceedings, pp. 275-289, 2005, Springer, 3-540-29189-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
model approximations, Formal verification, heuristic search, symbolic model checking, data abstractions |
27 | Shan-Tai Chen, Shun-Shii Lin, Li-Te Huang, Chun-Jen Wei |
Towards the Exact Minimization of BDDs-An Elitism-Based Distributed Evolutionary Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Heuristics ![In: J. Heuristics 10(3), pp. 337-355, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DEBEA, EBEA, paralleled algorithm, evolutionary algorithm, Binary Decision Diagram, heuristic algorithm |
27 | Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler |
Disjoint Sum of Product Minimization by Evolutionary Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal, April 5-7, 2004, Proceedings, pp. 198-207, 2004, Springer, 3-540-21378-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Rune Møller Jensen |
CLab: A C++ Library for Fast Backtrack-Free Interactive Product Configuration.. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CP ![In: Principles and Practice of Constraint Programming - CP 2004, 10th International Conference, CP 2004, Toronto, Canada, September 27 - October 1, 2004, Proceedings, pp. 816, 2004, Springer, 3-540-23241-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Hung-Yau Lin, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo |
An Efficient Perfect Algorithm for Memory Repair Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 306-313, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Alan Mishchenko |
Fast computation of symmetries in Boolean functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1588-1593, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | E. Allen Emerson, Thomas Wahl |
On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 216-230, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Chao Wang 0001, Gary D. Hachtel, Fabio Somenzi |
The Compositional Far Side of Image Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 334-341, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Model checking, Binary Decision Diagrams, Symbolic, image computation |
27 | D. Michael Miller, Rolf Drechsler |
Augmented Sifting of Multiple-Valued Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan, pp. 375-382, 2003, IEEE Computer Society, 0-7695-1918-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Nina Amla, Robert P. Kurshan, Kenneth L. McMillan, Ricardo H. Medel |
Experimental Analysis of Different Techniques for Bounded Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 9th International Conference, TACAS 2003, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003, Warsaw, Poland, April 7-11, 2003, Proceedings, pp. 34-48, 2003, Springer, 3-540-00898-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Aiqun Cao, Cheng-Kok Koh |
Non-Crossing OBDDs for Mapping to Regular Circuit Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 338-343, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Bijan Alizadeh, Mohammad Reza Kakoee |
Using Integer Equations for High Level Formal Verification Property Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 69-74, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Albert Nymeyer, Kairong Qian |
Heuristic Search Algorithms Based on Symbolic Data Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Conference on Artificial Intelligence ![In: AI 2003: Advances in Artificial Intelligence, 16th Australian Conference on Artificial Intelligence, Perth, Australia, December 3-5, 2003, Proceedings, pp. 966-979, 2003, Springer, 3-540-20646-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
shortest path, Heuristic search, binary decision diagrams |
27 | Per Bjesse |
Industrial Model Checking Based on Satisfiability Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking of Software, 9th International SPIN Workshop, Grenoble, France, April 11-13, 2002, Proceedings, pp. 240, 2002, Springer, 3-540-43477-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | HyungWon Kim 0001, John P. Hayes |
Delay fault testing of IP-based designs via symbolic path modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 661-678, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Jaco Geldenhuys, Antti Valmari |
Techniques for Smaller Intermediary BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR 2001 - Concurrency Theory, 12th International Conference, Aalborg, Denmark, August 20-25, 2001, Proceedings, pp. 233-247, 2001, Springer, 3-540-42497-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Michael J. C. Gordon |
Reachability Programming in HOL98 Using BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 13th International Conference, TPHOLs 2000, Portland, Oregon, USA, August 14-18, 2000, Proceedings, pp. 179-196, 2000, Springer, 3-540-67863-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Christoph Scholl 0001, Bernd Becker 0001 |
On the Generation of Multiplexer Circuits for Pass Transistor Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 372-378, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Aarti Gupta, Zijiang Yang 0006, Pranav Ashar, Anubhav Gupta 0001 |
SAT-Based Image Computation with Application in Reachability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings, pp. 354-371, 2000, Springer, 3-540-41219-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Xinyu Zang, Hairong Sun, Kishor S. Trivedi |
Dependability Analysis of Distributed Computer Systems with Imperfect Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 330-337, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Modeling design constraints and biasing in simulation using BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 584-590, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha |
An Exact Input Encoding Algorithm for BDDs Representing FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 294-300, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
input encoding, finite state machines, binary decision diagrams, multi-valued decision diagrams |
27 | Gianpiero Cabodi, Paolo Camurati, Stefano Quer |
Improved reachability analysis of large finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 354-360, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Sequential Logic Synthesis and Verification |
26 | Carsten Sinz, Wolfgang Küchlin, Dieter Feichtinger, Georg Görtler |
Checking Consistency and Completeness of On-Line Product Manuals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Autom. Reason. ![In: J. Autom. Reason. 37(1-2), pp. 45-66, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
problem encoding, BDD-techniques, SAT, real-world applications |
26 | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
Incremental logic rectification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 143-149, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
incremental logic rectification, incorrect combinational circuit, symbolic BDD techniques, sequence of partial corrections, circuits with multiple errors, general single-gate correction, structural correspondence, ISCAS85 benchmark circuits, error region pruning, specification, implementation, logic CAD, VLSI design, hybrid approach |
26 | Florian Krohm, Andreas Kuehlmann, Arjen Mets |
The use of random simulation in formal verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 371-376, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
random simulation, BDD-based verification, counter example pattern, design partitioning, Boolean reasoning, formal verification, formal verification, hardware designs, functional equivalence |
26 | Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò |
Reliability evaluation of combinational logic circuits by symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 235-243, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability |
26 | Martin Dietzfelbinger, Stefan Edelkamp |
Perfect Hashing for State Spaces in BDD Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KI ![In: KI 2009: Advances in Artificial Intelligence, 32nd Annual German Conference on AI, Paderborn, Germany, September 15-18, 2009. Proceedings, pp. 33-40, 2009, Springer, 978-3-642-04616-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Andrei Rimsa, Luis E. Zárate, Mark A. J. Song |
Handling Large Formal Context Using BDD - Perspectives and Limitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFCA ![In: Formal Concept Analysis, 7th International Conference, ICFCA 2009, Darmstadt, Germany, May 21-24, 2009, Proceedings, pp. 194-209, 2009, Springer, 978-3-642-01814-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Formal Concept Analysis, Binary Decision Diagrams, Formal Context, Formal Concept |
26 | Ken Friis Larsen |
A MuDDy Experience-ML Bindings to a BDD Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSL ![In: Domain-Specific Languages, IFIP TC 2 Working Conference, DSL 2009, Oxford, UK, July 15-17, 2009, Proceedings, pp. 45-57, 2009, Springer, 978-3-642-03033-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Ondrej Lhoták, Laurie J. Hendren |
Evaluating the benefits of context-sensitive points-to analysis using a BDD-based implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Softw. Eng. Methodol. ![In: ACM Trans. Softw. Eng. Methodol. 18(1), pp. 3:1-3:53, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Interprocedural program analysis, cast safety analysis, Java, binary decision diagrams, context sensitivity, points-to analysis, call graph construction |
26 | Ondrej Lhoták, Laurie J. Hendren |
Relations as an abstraction for BDD-based program analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 30(4), pp. 19:1-19:63, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Boolean formula satisfiability, physical domain assignment, Java, program analysis, Binary decision diagrams, language design, relations, points-to analysis |
26 | Vasilis Samoladas |
Improved BDD Algorithms for the Simulation of Quantum Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Algorithms - ESA 2008, 16th Annual European Symposium, Karlsruhe, Germany, September 15-17, 2008. Proceedings, pp. 720-731, 2008, Springer, 978-3-540-87743-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Xiangyu Luo, Kaile Su, Abdul Sattar 0001, Yan Chen |
Solving Sum and Product Riddle via BDD-Based Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web Intelligence/IAT Workshops ![In: Proceedings of the 2008 IEEE/WIC/ACM International Conference on Web Intelligence and International Conference on Intelligent Agent Technology - Workshops, 9-12 December 2008, Sydney, NSW, Australia, pp. 630-633, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Peter Hawkins, Peter J. Stuckey |
A Hybrid BDD and SAT Finite Domain Constraint Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADL ![In: Practical Aspects of Declarative Languages, 8th International Symposium, PADL 2006, Charleston, SC, USA, January 9-10, 2006, Proceedings, pp. 103-117, 2006, Springer, 3-540-30947-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Gopal Paul, Sambhu Nath Pradhan, Ajit Pal, Bhargab B. Bhattacharya |
Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1504-1507, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Combining ordered best-first search with branch and bound for exact BDD minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10), pp. 1515-1529, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Junhao Shi, Görschwin Fey, Rolf Drechsler |
Bridging fault testability of BDD circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 188-191, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Jaco van de Pol, Olga Tveretina |
A BDD-Representation for the Logic of Equality and Uninterpreted Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 2005, 30th International Symposium, MFCS 2005, Gdansk, Poland, August 29 - September 2, 2005, Proceedings, pp. 769-780, 2005, Springer, 3-540-28702-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Sumio Morioka, Akashi Satoh |
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(7), pp. 686-691, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Farn Wang, Karsten Schmidt 0004, Fang Yu 0001, Geng-Dian Huang, Bow-Yaw Wang |
BDD-Based Safety-Analysis of Concurrent Software with Pointer Data Structures Using Graph Automorphism Symmetry Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 30(6), pp. 403-417, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ondrej Lhoták, Laurie J. Hendren |
Jedd: a BDD-based relational extension of Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, Washington, DC, USA, June 9-11, 2004, pp. 158-169, 2004, ACM, 1-58113-807-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
boolean formula satisfiability, Java, program analysis, binary decision diagrams, language design, relations |
26 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
An improved branch and bound algorithm for exact BDD minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12), pp. 1657-1663, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Combination of Lower Bounds in Exact BDD Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10758-10763, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | John V. Franco, Michal Kouril, John S. Schlipf, Jeffrey Ward, Sean A. Weaver, Michael R. Dransfield, W. Mark Vanfleet |
SBSAT: a State-Based, BDD-Based Satisfiability Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing, 6th International Conference, SAT 2003. Santa Margherita Ligure, Italy, May 5-8, 2003 Selected Revised Papers, pp. 398-410, 2003, Springer, 3-540-20851-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Guoqiang Pan, Ulrike Sattler, Moshe Y. Vardi |
BDD-Based Decision Procedures for K. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CADE ![In: Automated Deduction - CADE-18, 18th International Conference on Automated Deduction, Copenhagen, Denmark, July 27-30, 2002, Proceedings, pp. 16-30, 2002, Springer, 3-540-43931-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Sumio Morioka, Akashi Satoh |
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 98-103, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Rolf Drechsler, Wolfgang Günther 0001, Fabio Somenzi |
Using lower bounds during dynamic BDD minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 51-57, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Wolfgang Günther 0001, Rolf Drechsler |
Implementation of Read- k-times BDDs on Top of Standard BDD Packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 173-178, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Rolf Drechsler, Nicole Drechsler, Wolfgang Günther 0001 |
Fast exact minimization of BDD's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3), pp. 384-389, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan |
Sibling-substitution-based BDD minimization using don't cares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 44-55, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Holger Hermanns, Markus Siegle |
Bisimulation Algorithms for Stochastic Process Algebras and Their BDD-Based Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARTS ![In: Formal Methods for Real-Time and Probabilistic Systems, 5th International AMAST Workshop, ARTS'99, Bamberg, Germany, May 26-28, 1999. Proceedings, pp. 244-264, 1999, Springer, 3-540-66010-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Masahito Kurihara, Hisashi Kondo |
Heuristics and Experiments on BDD Representation of Boolean Functions for Expert Systems in Software Verification Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Joint Conference on Artificial Intelligence ![In: Advanced Topics in Artificial Intelligence, 12th Australian Joint Conference on Artificial Intelligence, AI '99, Sydney, Australia, December 6-10, 1999, Proceedings, pp. 353-364, 1999, Springer, 3-540-66822-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Macha Nikolskaïa, Antoine Rauzy, David James Sherman |
Almana: A BDD Minimization Tool Integrating Heuristic and Rewriting Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Second International Conference, FMCAD '98, Palo Alto, California, USA, November 4-6, 1998, Proceedings, pp. 100-114, 1998, Springer, 3-540-65191-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Abelardo Pardo, Gary D. Hachtel |
Incremental CTL Model Checking Using BDD Subsetting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 457-462, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band |
26 | Nils Klarlund |
An n log n Algorithm for Online BDD Refinement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 107-118, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Bwolen Yang, David R. O'Hallaron |
Parallel Breadth-First BDD Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the Sixth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), Las Vegas, Nevada, USA, June 18-21, 1997, pp. 145-156, 1997, ACM, 0-89791-906-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Ashvin Dsouza, Bard Bloom |
Generating BDD Models for Process Algebra Terms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 16-30, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
18 | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
A Comparison of Architectures for Various Decision Diagram Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010, Barcelona, Spain, 26-28 May 2010, pp. 229-234, 2010, IEEE Computer Society, 978-0-7695-4024-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
QDD, QRBDD, QRMDD, Heterogeneous MDD, Homogeneous MDD, Branching Machine, MDD, BDD |
18 | María Agustina Cibrán |
Translating BPMN Models into UML Activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Business Process Management Workshops ![In: Business Process Management Workshops, BPM 2008 International Workshops, Milano, Italy, September 1-4, 2008. Revised Papers, pp. 236-247, 2008, Springer, 978-3-642-00327-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
UML Activities, MDA, Model Transformations, BDD, MDE, BPMN, ATL |
18 | Felix Reimann, Michael Glaß, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich |
Symbolic voter placement for dependability-aware system synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 237-242, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
mttuf, bdd, system synthesis, voter, mean time to failure, mttf |
18 | Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda |
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 224-234, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
microprocessor, BDD, MOEA, path-delay testing |
18 | Scott W. Ambler |
Test-Driven Development of Relational Databases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Softw. ![In: IEEE Softw. 24(3), pp. 37-43, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
database refactoring, test-driven database design, behavior-driven development, relational database, test-driven development, TDD, TDD, BDD, database testing |
18 | Rongjie Yan, Guangyuan Li, Wenliang Zhang, Yunquan Peng |
Improvements for the Symbolic Verification of Timed Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2007, 27th IFIP WG 6.1 International Conference, Tallinn, Estonia, June 27-29, 2007, Proceedings, pp. 196-210, 2007, Springer, 978-3-540-73195-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
verification, BDD, timed systems, symbolic method |
18 | Chao Wang 0001, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi |
Compositional SCC Analysis for Language Emptiness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 28(1), pp. 5-36, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
language emptiness, model checking, BDD, LTL, abstraction refinement |
18 | Dirk Beyer 0001 |
Relational programming with CrocoPat. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 28th International Conference on Software Engineering (ICSE 2006), Shanghai, China, May 20-28, 2006, pp. 807-810, 2006, ACM, 1-59593-375-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pattern matching, relational algebra, BDD, transitive closure, graph models, software analysis, predicate logic |
18 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri |
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 111-114, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
BDD, leakage, ADD |
18 | Yung-Ruei Chang, Suprasad V. Amari, Sy-Yen Kuo |
Computing System Failure Frequencies and Reliability Importance Measures Using OBDD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(1), pp. 54-68, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Failure frequency, reliability importance measure, imperfect coverage, fault tolerance, BDD, system availability |
18 | Robert F. Damiano, James H. Kukula |
Checking satisfiability of a conjunction of BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 818-823, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
satisfiability, BDD |
18 | Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller |
Multi-Output Timed Shannon Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA, pp. 47-52, 2002, IEEE Computer Society, 0-7695-1486-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Low Power, Logic Synthesis, BDD |
18 | Shin-ichi Minato |
Zero-suppressed BDDs and their applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(2), pp. 156-170, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Boolean function, BDD, Combinatorial problem, VLSI CAD, ZBDD |
18 | Stefan Höreth |
A word-level graph manipulation package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(2), pp. 182-192, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Word-level, TUDD, BDD, Decision diagrams, BMD |
18 | Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho |
An Efficient Logic Equivalence Checker for Industrial Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 91-106, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
logic checking, ATPG, BDD, formal, combinational, functional verification, equivalence, MET |
18 | Jun Yuan 0007, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
Automatic Vector Generation Using Constraints and Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 107-120, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
constraint, probability, partitioning, BDD, biasing, vector generation |
18 | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
Implementation of Multiple-Output Functions Using PQMDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 199-205, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Multiple-output logic function, PMDD, PQMDD, MDD, BDD |
18 | Frank Schmiedle, Wolfgang Günther 0001, Rolf Drechsler |
Dynamic Re-Encoding During MDD Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 239-244, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
variable grouping, MDD, BDD, sifting |
18 | Rolf Drechsler |
Preudo-Kronecker Expressions for Symmetric Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(9), pp. 987-990, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
AND/EXOR, PSDKRO, 2-level minimization, Logic synthesis, BDD |
18 | Bernd Becker 0001, Martin Keim, Rolf Krieger |
Hybrid Fault Simulation for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(3), pp. 219-238, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
SOT, fault simulation, BDD, symbolic simulation, MOT |
18 | Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man |
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(3), pp. 217-238, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
supergate, prime-and-irredundant, ATPG, BDD |
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