Search results for "Capacitance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Davide Pandini, Cristiano Forzan, Livio Baldi	Design Methodologies and Architecture Solutions for High-Performance Interconnects.	ICCD	2004	DBLP DOI BibTeX RDF
30	Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin	Delay and current estimation in a CMOS inverter with an RC load.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
30	Vasily G. Moshnyaga	Reducing cache engery through dual voltage supply.	ASP-DAC	2001	DBLP DOI BibTeX RDF
30	Mahadevamurty Nemani, Farid N. Najm	High-level area and power estimation for VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
30	Anand Raghunathan, Niraj K. Jha	SCALP: an iterative-improvement-based low-power data path synthesis system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
30	Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson	Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
30	Jan J. H. van der Biesen, Toru Toyabe	Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
30	Yu Chen, Yuchen Song, Jian Zhang	A Novel Principal Component Analysis Flow Pattern Identification Algorithm for Electrical Capacitance Tomography System.	MVHI	2010	DBLP DOI BibTeX RDF	electrical capacitance tomography, Symmetric subspace, neural network, principal component analysis
30	Lei Liu, Yu Chen, Yuchen Song	A Novel Barzilai-Borwein Image Reconstruction Algorithm for Electrical Capacitance Tomography System.	MVHI	2010	DBLP DOI BibTeX RDF	electrical capacitance tomography, Barzilai-Borwein, image reconstruction, Steepest Descent
30	Yinke Dou, Jianmin Qin, Xiaomin Chang	The Study of a Capacitance Sensor and its System Used in Measuring Ice Thickness, Sedimentation and Water Level of a Reservoir.	IFITA (3)	2009	DBLP DOI BibTeX RDF	Multi-electrode Capacitance, Ice thickness, water level, CPLD, Sedimentation
30	Xuemei Hu, Linhong Tian	Research and Analysis of Bias Voltage on Variable-Capacitance Micro-mechanical Accelerometer.	IIH-MSP	2008	DBLP DOI BibTeX RDF	Variable-Capacitance Accelerometer, Reliable operation condition, Bias voltage polarity
28	Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak	Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack.	VLSI Design	2009	DBLP DOI BibTeX RDF
28	Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel	A capacitance solver for incremental variation-aware extraction.	ICCAD	2008	DBLP DOI BibTeX RDF
28	Carlos Fernando Teodósio Soares, Antonio Petraglia	Capacitance ratio approximation in SC filters via genetic algorithm.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Tadashi Suetsugu, Marian K. Kazimierczuk	ZVS operating frequency versus duty ratio of class E amplifier with nonlinear shunt capacitance.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Sushmit Goswami, Tino Copani, Bert Vermeire, Hugh Bamaby	BW extension in shunt feedback transimpedance amplifiers using negative miller capacitance.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Jintao Xue, Dian Zhou	A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.	DATE	2007	DBLP DOI BibTeX RDF
28	Shilpa Bhoj, Dinesh Bhatia	Pre-route Interconnect Capacitance and Power Estimation in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
28	Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li 0004, Zhihua Wang 0001, Patrick Chiang 0001	Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Ning Lu, Judy H. McCullen	Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance.	ISQED	2007	DBLP DOI BibTeX RDF
28	Aditya Bansal, Bipul Chandra Paul, Kaushik Roy 0001	An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	James D. Ma, Rob A. Rutenbar	Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	Shu Yan, Vivek Sarin, Weiping Shi	Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	Elias Kougianos, Saraju P. Mohanty	Effective tunneling capacitance: a new metric to quantify transient gate leakage current.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman	On-die decoupling capacitance: frequency domain analysis of activity radius.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Usha Narasimha, Binu Abraham, N. S. Nagaraj	Statistical Analysis of Capacitance Coupling Effects on Delay and Noise.	ISQED	2006	DBLP DOI BibTeX RDF
28	Deyun Chen, Mouzun Li	Parameters Optimization and Simulation of Transducer Based on Finite Element Method in Electrical Capacitance Tomography System.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF
28	Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Dian Zhou	A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.	APCCAS	2006	DBLP DOI BibTeX RDF
28	Shu Yan, Vivek Sarin, Weiping Shi	Sparse transformations and preconditioners for 3-D capacitance extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
28	Nang-Ching Yeung, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-Fat Chan	Active RC filter with reduced capacitance by current division technique.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
28	Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda	Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.	ISQED	2005	DBLP DOI BibTeX RDF
28	Shabbir H. Batterywala, Madhav P. Desai	Variance Reduction in Monte Carlo Capacitance Extraction.	VLSI Design	2005	DBLP DOI BibTeX RDF
28	Zhenhai Zhu, Jacob K. White 0001, Alper Demir 0001	A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance.	ICCAD	2004	DBLP DOI BibTeX RDF
28	Shoji Suzuki, Yoshinori Adachi	Development of High-Precise and No-Contacting Capacitance Measuring System Using Dipmeter.	KES	2004	DBLP DOI BibTeX RDF
28	Jürgen Leeb, Johannes Knorr, Horst Zimmermann	Sensitivity-enhanced OEIC with capacitance multiplier for reduced lower-cutoff frequency.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
28	Ye Liu, Mei Xue, Zheng-Fan Li, Rui-Feng Xue	Efficient Capacitance Extraction for Periodic Structures by Shanks Transformation.	ISQED	2004	DBLP DOI BibTeX RDF
28	Jozef Adut, José Silva-Martínez	A high-Q, switched-capacitor filter with reduced capacitance spread using a randomized nonuniform sampling technique.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
28	Li Ding 0002, Pinaki Mazumder, David T. Blaauw	Crosstalk noise estimation using effective coupling capacitance.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
28	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
28	Woojin Jin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
28	Wenjian Yu, Zeyi Wang	An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF
28	Chung Kei Thomas Chan, Christofer Toumazou	Design of a class E power amplifier with non-linear transistor output capacitance and finite DC-feed inductance.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
28	Asim Husain	Models For Interconnect Capacitance Extraction.	ISQED	2001	DBLP DOI BibTeX RDF
28	Yanhong Yuan, Prithviraj Banerjee	Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors.	ICCD	2000	DBLP DOI BibTeX RDF
28	Jinsong Zhao	Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction.	DAC	2000	DBLP DOI BibTeX RDF
28	Sharad Kapur, David E. Long	Large-scale capacitance calculation.	DAC	2000	DBLP DOI BibTeX RDF
28	Youxin Gao, D. F. Wong 0001	Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model.	ASP-DAC	1999	DBLP DOI BibTeX RDF
28	Yanhong Yuan, Prithviraj Banerjee	ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
28	Jaewon Oh, Massoud Pedram	Gated Clock Routing Minimizing the Switched Capacitance.	DATE	1998	DBLP DOI BibTeX RDF	gated clock routing, low power
28	Weiping Shi, Jianguo Liu 0001, Naveen Kakani, Tiejun Yu	A Fast Hierarchical Algorithm for 3-D Capacitance Extraction.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
28	E. Aykut Dengi, Ronald A. Rohrer	Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
28	Chung-Ping Chen, D. F. Wong 0001	Optimal Wire-Sizing Function with Fringing Capacitance Consideration.	DAC	1997	DBLP DOI BibTeX RDF
28	Denis Martin, Nicholas C. Rumin	Delay prediction from resistance-capacitance models of general MOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
28	Hong June Park, Ping Keung Ko, Chenming Hu	A charge sheet capacitance model of short channel MOSFETs for SPICE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
28	Sanae Fukuda, Naoyuki Shigyo, Koichi Kato, Shin Nakamura	A ULSI 2-D capacitance simulator for complex structures based on actual processes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
28	Erich Barke	Line-to-ground capacitance calculation for VLSI: a comparison.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
26	Data Ram Bhaskar, Meghana Shrivastava, Ajishek Raj, Pragati Kumar	Floating parallel lossy inductance, parallel lossy capacitance, parallel C-D, and lossless capacitance multiplier circuits using current feedback operational amplifiers.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
26	Dingcheng Yang, Haoyuan Li, Wenjian Yu, Yuanbo Guo, Wenjie Liang	CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
26	Siheon Seong, Sewon Lee, Sunghyun Bae, Minjae Lee	Self Capacitance Mismatch Calibration Technique for Fully-Differential Touch Screen Panel Self Capacitance Sensing System.	Sensors	2023	DBLP DOI BibTeX RDF
26	Hyeyeon Lee, Changuk Lee, Inhee Lee, Youngcheol Chae	A 0.033-mm2 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
26	Raoul Joly, Stephanie Girod, Noureddine Adjeroud, Patrick Grysan, Jerome Polesel-Maris	Evidence of Negative Capacitance and Capacitance Modulation by Light and Mechanical Stimuli in Pt/ZnO/Pt Schottky Junctions.	Sensors	2021	DBLP DOI BibTeX RDF
26	Hyeyeon Lee, Changuk Lee, Jae-Youl Lee, Yoon-Kyung Choi, Youngcheol Chae	A 0.033-mm2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity up to 480pF.	A-SSCC	2021	DBLP DOI BibTeX RDF
26	Ngoc Thanh Mai Tran, Vincenzo D'Elia, Luca Callegaro, Massimo Ortolano	A Capacitance Build-Up Method to Determine LCR Meter Errors and Capacitance Transfer.	IEEE Trans. Instrum. Meas.	2020	DBLP DOI BibTeX RDF
26	Tianyu Yu, Weifeng Lü, Zhifeng Zhao, Peng Si, Kai Zhang	Effect of different capacitance matching on negative capacitance FDSOI transistors.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
26	Asif Islam Khan	Ferroelectrics, Negative Capacitance and Depolarization Field: What exactly is negative capacitance?	DRC	2019	DBLP DOI BibTeX RDF
26	Haoming Xin, Martin Andraud, Peter G. M. Baltus, Eugenio Cantatore, Pieter Harpe	A 0.1nW -1µW All-Dynamic Capacitance-to-Digital Converter with Power/Speed/Capacitance Scalability.	ESSCIRC	2018	DBLP DOI BibTeX RDF
26	Ali Saeidi, Farzan Jazaeri, Francesco Bellando, Igor Stolichnov, Christian C. Enz, Adrian M. Ionescu	Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation.	ESSDERC	2017	DBLP DOI BibTeX RDF
26	Dongdi Zhu, Jiongjiong Mo, Shiyi Xu, Yong-Heng Shang, Zhiyu Wang, Zheng-Liang Huang, Fa-Xin Yu	A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
26	Shunji Nakata, Hiroshi Makino, Yoshio Matsuda	A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance.	MWSCAS	2014	DBLP DOI BibTeX RDF
26	Susumu Kobayashi, Naoshi Doi	An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
26	Wuqiang Yang, A. L. Stott, J. C. Gamio	Analysis of the effect of stray capacitance on an ac-based capacitance tomography transducer.	IEEE Trans. Instrum. Meas.	2003	DBLP DOI BibTeX RDF
26	Deyun Chen, Guibin Zheng, Xiaoyang Yu, Yukun Wang, Tong Zhou	Analysis of capacitance sensitivity distributions and image reconstruction in electrical capacitance tomography.	Color Imaging: Device-Independent Color, Color Hardcopy, and Applications	2002	DBLP DOI BibTeX RDF
26	Dennis Sylvester, James C. Chen, Chenming Hu	Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
24	Samed Maltabas, Martin Margala, Ugur Çilingiroglu	Varicap threshold logic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	minnick tl network, variable capacitance, threshold logic, parallel counter
24	Chao Wang 0019, Ming Zhang, Xiangyu Wang, Dongyue Wu, Huaxiang Wang	Primary Study on Dielectric Property Detection for Cerebral Haematoma.	BMEI (2)	2008	DBLP DOI BibTeX RDF	Haematoma of brain, the permittivity of the organism, bioelectrical capacitance measuring technology
24	Peter Feldmann, Soroush Abbaspour	Towards a more physical approach to gate modeling for timing, noise, and power.	DAC	2008	DBLP DOI BibTeX RDF	current source model, effective capacitance
24	Agnes Sarolta Nagy, Alicia Polanco, Manuel Alvarez	Contributions to improve design accuracy of bipolar ics via physical effects.	SBCCI	2007	DBLP DOI BibTeX RDF	base-emitter capacitance model, emission coefficient, physical effects
24	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment.	CHES	2005	DBLP DOI BibTeX RDF	dual rail with precharge, wave dynamic differential logic (WDDL), differential routing, parasitic capacitance matching, side-channel attack (SCA), differential power analysis (DPA), countermeasure
24	Doug L. James, Dinesh K. Pai	Multiresolution green's function methods for interactive simulation of large-scale elastostatic objects.	ACM Trans. Graph.	2003	DBLP DOI BibTeX RDF	Capacitance matrix, elastostatic, fast summation, interactive real-time applications, real-time, wavelets, deformation, force feedback, updating, lifting scheme, Green's function
24	Yu Chen 0005, Puneet Gupta 0001, Andrew B. Kahng	Performance-impact limited area fill synthesis.	DAC	2003	DBLP DOI BibTeX RDF	VLSI manufacturability, coupling capacitance extraction, dummy fill problem, signal delay, linear programming, greedy method
24	Tae-young Oh, Zhiping Yu, Robert W. Dutton	AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections.	ISQED	2002	DBLP DOI BibTeX RDF	AC analysis, thin gate oxide, quantum mechanical correction, threshold voltage shift, transconductace, channel length reduction, density-gradient, quantum confinement, PROPHET, channel doping, transport theory, device parameter extraction, effective oxide thickness, capacitance
24	Nathan Kalyanasundharam, Nital Patwa	Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor.	ICCD	1999	DBLP DOI BibTeX RDF	multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance
24	Peter James Aldworth	System-on-a-Chip Bus Architecture for Embedded Applications.	ICCD	1999	DBLP DOI BibTeX RDF	architecture, interconnect, latency, infrastructure, system-on-a-chip, bus, capacitance, peripherals
24	Darko Kirovski, Johnson Kin, William H. Mangione-Smith	Procedure Based Program Compression.	MICRO	1997	DBLP DOI BibTeX RDF	cached procedures, compressed memory, consumer devices, design factors, directory structure, high-capacitance bus traffic, integrated data services, memory references, pagers, procedural reference resolution, procedure-based program compression, run-time performance overhead, smart telephones, transparent program compression, embedded systems, personal digital assistants, power consumption, cost, multimedia applications, source coding, RAM, performance requirements, battery life, communications applications, memory reduction
24	N. P. van der Meijs, T. Smedes	Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling
23	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
23	Kunal P. Ganeshpure, Sandip Kundu	An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.	VLSI Design	2009	DBLP DOI BibTeX RDF
23	Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang	A noniterative equivalent waveform model for timing analysis in presence of crosstalk.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	equivalent waveform, delay, noise, timing analysis, Deep sub micron
23	Changhui Liu, Chunmei Xu, Le Liu, Huahui He	Measure the Thickness of the Thin-Film Single-Slice-Capacitor.	ISIP	2008	DBLP DOI BibTeX RDF
23	Zheng Chen, Dawn R. Hedgepeth, Xiaobo Tan	A nonlinear, control-oriented model for ionic polymer-metal composite actuators.	CDC	2008	DBLP DOI BibTeX RDF
23	Yiling Zhang, Valencia M. Joyner, Ruida Yun, Sameer R. Sonkusale	A 700Mbit/s CMOS capacitive feedback front-end amplifier with automatic gain control for broadband optical wireless links.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Timothy G. Constandinou, Julius Georgiou, Chris Toumazou	A micropower front-end interface for differential-capacitive sensor systems.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Kunal P. Ganeshpure, Sandip Kundu	Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.	DATE	2007	DBLP DOI BibTeX RDF
23	Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang 0001	Coupling-aware Dummy Metal Insertion for Lithography.	ASP-DAC	2007	DBLP DOI BibTeX RDF	coupling-aware dummy metal insertion, integrated circuits manufacturing technology, resolution enhancement techniques, off-axis illumination, forbidden pitches, printability improvement, invisible dummy metal segments, lithography cost minimization, optimal algorithm, chemical mechanical polish
23	Rupesh S. Shelar	An efficent clustering algorithm for low power clock tree synthesis.	ISPD	2007	DBLP DOI BibTeX RDF	clustering, low power, clock tree synthesis
23	Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap	Fast Interconnect and Gate Timing Analysis for Performance Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
23	Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella	Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns.	HiPC	2006	DBLP DOI BibTeX RDF
23	Di Wu 0017, Jiang Hu, Rabi N. Mahapatra	Coupling aware timing optimization and antenna avoidance in layer assignment.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect
23	Liang Deng, Martin D. F. Wong	Energy optimization in memory address bus structure for application-specific systems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
23	Rafael Escovar, Roberto Suaya	Optimal design of clock trees for multigigahertz applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF