Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Massimo Alioto, Gaetano Palumbo	Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.	PATMOS	2002	DBLP DOI BibTeX RDF
27	Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev	Semi-modular Latch Chains for Asynchronous Circuit Design.	PATMOS	2000	DBLP DOI BibTeX RDF
27	Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, Javier Sosa	A Single Phase Latch for High Speed GaAs Domino Circuits.	DATE	2000	DBLP DOI BibTeX RDF
27	Nicola Nicolici, Bashir M. Al-Hashimi	Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.	DATE	2000	DBLP DOI BibTeX RDF
27	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
27	Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.	A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
27	Stephen B. Furber, Paul Day	Four-phase micropipeline latch control circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
27	Ellen Sentovich, Horia Toma, Gérard Berry	Latch optimization in circuits generated from high-level descriptions.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential optimisation, high-level synthesis, state assignment
27	Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun	Analysis and design of latch-controlled synchronous digital circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
27	Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun	Analysis and Design of Latch-Controlled Synchronous Digital Circuits.	DAC	1990	DBLP DOI BibTeX RDF
21	Lik Wong, Nimar S. Arora, Lei Gao, Thuvan Hoang, Jingwei Wu	Oracle Streams: A High Performance Implementation for Near Real Time Asynchronous Replication.	ICDE	2009	DBLP DOI BibTeX RDF
21	Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni	All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates.	OSC	2009	DBLP DOI BibTeX RDF	optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA)
21	Yibo Chen, Yuan Xie 0001	Tolerating process variations in high-level synthesis using transparent latches.	ASP-DAC	2009	DBLP DOI BibTeX RDF
21	Eli Arbel, Oleg Rokhlenko, Karen Yorav	SAT-based synthesis of clock gating functions using 3-valued abstraction.	FMCAD	2009	DBLP DOI BibTeX RDF
21	Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha	Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors.	DAC	2009	DBLP DOI BibTeX RDF	variability-aware design, robustness, micro-architecture
21	David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
21	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
21	Yanfeng Wang, Qiang Zhou 0001, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian	Low power clock buffer planning methodology in F-D placement for large scale circuit design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
21	David A. Papa, Tao Luo 0002, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li 0001, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.	ISPD	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
21	Jun Tomisawa, Kazuyasu Nishikawa, Satoshi Yamakawa	Low-current consumption CMOS comparator using charge-storage amplifier for A/D converters.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka	Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki	An automated runtime power-gating scheme.	ICCD	2007	DBLP DOI BibTeX RDF
21	Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani	High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Lih-Yih Chiou, Shien-Chun Luo	An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi	Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.	DFT	2007	DBLP DOI BibTeX RDF
21	Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein	Self-Resetting Latches for Asynchronous Micro-Pipelines.	DAC	2007	DBLP DOI BibTeX RDF
21	Ganesh Venkataraman, Jiang Hu, Frank Liu 0001, Cliff C. N. Sze	Integrated placement and skew optimization for rotary clocking.	DATE	2006	DBLP DOI BibTeX RDF
21	Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen	Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops.	ASP-DAC	2006	DBLP DOI BibTeX RDF
21	Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang	A probabilistic analysis of pipelined global interconnect under process variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
21	Jacqueline E. Rice	A new look at reversible memory elements.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Bhavna Agrawal, Jeffrey G. Hemmett, Karl K. Moody, David B. White	Techniques to address increased dimensionality of ASIC library design.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Fatemeh Aezinia, S. Najafzadeh, Ali Afzali-Kusha	Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops.	APCCAS	2006	DBLP DOI BibTeX RDF
21	Hemangee K. Kapoor	Formal Modelling and Verification of an Asynchronous DLX Pipeline.	SEFM	2006	DBLP DOI BibTeX RDF
21	Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra	A novel high-speed sense-amplifier-based flip-flop.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty	Untestable Multi-Cycle Path Delay Faults in Industrial Designs.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
21	Tomás Maul, Sapiyan Baba, Azwina M. Yusof	Dynamic Inputs and Attraction Force Analysis for Visual Invariance and Transformation Estimation.	ICNC (1)	2005	DBLP DOI BibTeX RDF
21	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Pre-capturing static pulsed flip-flops.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
21	Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov	A 0.35µm CMOS comparator circuit for high-speed ADC applications.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
21	Yijun Liu, Stephen B. Furber	Minimizing the Power Consumption of an Asynchronous Multiplier.	PATMOS	2004	DBLP DOI BibTeX RDF
21	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline Design Based on Self-Resetting Stage Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
21	Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura 0002, Shigeto Inui, Takeshi Yoshimura	Timing optimization by replacing flip-flops to latches.	ASP-DAC	2004	DBLP DOI BibTeX RDF
21	Minoru Watanabe, Fuminori Kobayashi	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.	FPL	2004	DBLP DOI BibTeX RDF
21	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
21	Victor V. Zyuban	Optimization of scannable latches for low energy.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
21	E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi	Power Comparison of Throughput Optimized IC Busses.	ISVLSI	2003	DBLP DOI BibTeX RDF
21	Omid Mirmotahari, Yngvar Berg	A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC.	ISMVL	2003	DBLP DOI BibTeX RDF
21	Yukiya Miura, Shuichi Seno	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis
21	Gianpiero Cabodi, Paolo Camurati, Stefano Quer	Dynamic Scheduling and Clustering in Symbolic Image Computation.	DATE	2002	DBLP DOI BibTeX RDF
21	Sang-Wook Kim, Wan Choi, Byoung-Ho Kim	Design and Implementation of the Concurrency Control Manager in the Main-Memory DBMS Tachyon.	COMPSAC	2002	DBLP DOI BibTeX RDF	main-memory DBMSs, concurrency control, DBMSs, locking, latching
21	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Comparative analysis of double-edge versus single-edge triggered clocked storage elements.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
21	Maryam Shojaei Baghini, Madhav P. Desai	Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	CMOS latches, Technology Scaling, Metastability
21	M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas	The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.	ISCA	2002	DBLP DOI BibTeX RDF	instruction queue clock rate, Pipelining
21	Kevin Stanley	High-Accuracy Flush-and-Scan Software Diagnostic.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
21	Xiaoqiang Shou, Michael M. Green	A family of CMOS latches with 3 stable operating points.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
21	Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami	Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies.	VLSI Design	2001	DBLP DOI BibTeX RDF
21	Mark Vesterbacka	A robust differential scan flip-flop.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
21	Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman	Logic Verification of Very Large Circuits Using Shark.	VLSI Design	1999	DBLP DOI BibTeX RDF
21	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states
21	Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto	Application of a Design for Delay Testability Approach to High Speed Logic LSIs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Delay Test Generation, Design for Testability, Delay Testing
21	Haiming Jin, Ravishankar K. Iyer, Mei-Chen Hsueh	FAMAS: FAult Modeling via Adaptive Simulation.	VLSI Design	1997	DBLP DOI BibTeX RDF
19	Steven M. Nowick, Montek Singh	High-Performance Asynchronous Pipelines: An Overview.	IEEE Des. Test Comput.	2011	DBLP DOI BibTeX RDF	elastic circuits, latch controllers, pipelines, asynchronous, dynamic logic, design and test, micropipelines
19	Martin Saint-Laurent, Animesh Datta	A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.	ISLPED	2010	DBLP DOI BibTeX RDF	clock gater, clock gating cell, local clock buffer, set-reset latch
19	Yongheng Guo, Wei Cai, Tiejun Lu, Zongmin Wang	A Novel 1GSPS Low Offset Comparator for High Speed ADC.	NCM	2009	DBLP DOI BibTeX RDF	high speed ADC, high speed comparator, preamplifier latch comparator, low offset comparator
19	Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri	A robust, fast pulsed flip-flop design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flip-flop, latch
19	Marc Blenkiron, D. K. Arvind 0001, Jamie A. Davies	Design of an irreversible DNA memory element.	Nat. Comput.	2007	DBLP DOI BibTeX RDF	DNA computing, Rotatable, Latch, Synthetic biology, Memory element
19	Mahmoud Lotfi Anhar, Mohammad Ali Jabraeil Jamali	The Optimum Location of Delay Latches Between Dynamic Pipeline Stages.	APPT	2007	DBLP DOI BibTeX RDF	Minimum, MAL, Pipeline, Latency, Collision, Table, Reservation, Latch, Average
19	Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel	Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	64-bit Power Architecture, design dependency solution, digital thermal sensor, flexible IO, hardware content protection, high-performance latch, linear sensor, local clock buffer, multi-operating system, synergistic processor, real-time system, modularity, power management, Linux, multi-core, multi-threading, SOC, thermal management, design environment, CELL Processor, clock distribution, virtualization technology, SOI, correct-by-construction, re-use, design hierarchy
19	Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty	Managing standby and active mode leakage power in deep sub-micron design.	ISLPED	2004	DBLP DOI BibTeX RDF	SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
19	Demos Anastasakis, Robert F. Damiano, Hi-Keung Tony Ma, Ted Stanion	A practical and efficient method for compare-point matching.	DAC	2002	DBLP DOI BibTeX RDF	combinational verification, latch mapping, equivalence checking
19	Samy Makar, Edward J. McCluskey	ATPG for scan chain latches and flip-flops.	VTS	1997	DBLP DOI BibTeX RDF	bistable element, scan chain circuit, combinational defect detection, algorithm, ATPG, automatic test pattern generation, automatic testing, stuck-at fault, flip-flop, latch, checking experiment
19	Suresh Rajgopal	Challenges in Low Power Microprocessor Design.	VLSI Design	1996	DBLP DOI BibTeX RDF	power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt
19	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
19	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
16	Jingfei Wang, Guishu Liang, Xiangyu Zhang 0004, Lei Qi 0005	A Refinement Multilevel Turn-off Method for Dynamic Latch-up and Tail Current Suppression in DC Breaker Ultra-High Current Switch Applications.	IEEE Trans. Ind. Electron.	2024	DBLP DOI BibTeX RDF
16	Jooyoung Bae, Wonsik Oh, Jahyun Koo 0003, Chengshuo Yu, Bongjin Kim	CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
16	Xingyu Wang, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara	A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
16	Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao 0007, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu	Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
16	Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao 0007, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu	Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
16	Aibin Yan, Litao Wang, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen	Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
16	Yuxin Bai, Chen Xin, Xinjie Zhou, Yanan Yin, Ying Zhang	Double-Node-Upset Self-Recoverable Latch Design for Wide Voltage Range Application.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
16	Suraj Kumar Prusty, V. K. Surya, Nijwm Wary	Energy Efficient Integrated Summer and Latch-Based DFE With Reduced Tap Loading.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Yan Zhang, Lei Ai, Huaguo Liang, Tianming Ni, Tai Song, Aibin Yan	Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
16	Hui Xu, Chaoming Liu, Ruijun Ma, Tai Song, Zhengfeng Huang, Jun Wang, Xuewei Qin, Yu Xia	Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
16	Kasi Bandla, Dipankar Pal	Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform.	CoRR	2024	DBLP DOI BibTeX RDF
16	Javad Bahrami, Mohammad Ebrahimabadi, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi	Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators.	COSADE	2024	DBLP DOI BibTeX RDF
16	Sun-A Jo, Ji-Won Seo, Min-Jae Seo	A Hardware-efficient Rate Encoding Hardware with Latch-based TRNG.	ICEIC	2024	DBLP DOI BibTeX RDF
16	Martín Gavilánez, Silvana Guitarra	A Calibrated Memristor Model Implementation for an SR-Latch Based on CMOS-Memristor Technology.	LASCAS	2024	DBLP DOI BibTeX RDF
16	Jooyoung Bae, Jahyun Koo 0003, Chaeyun Shim, Bongjin Kim	15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations.	ISSCC	2024	DBLP DOI BibTeX RDF
16	Massimo Giordano, Rohan Doshi, Qianyun Lu, Boris Murmann	TinyForge: A Design Space Exploration to Advance Energy and Silicon Area Trade-offs in tinyML Compute Architectures with Custom Latch Arrays.	ASPLOS (3)	2024	DBLP DOI BibTeX RDF
16	Yuan Guo, Qianqian Tong, Pengbo Zhao, Yuru Zhang, Dangxiao Wang	Electromagnetic-Actuated Soft Tactile Device Using a Pull-Push Latch Structure.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
16	Mohammad Gholami, Zaman Amirzadeh	Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study.	Frontiers Inf. Technol. Electron. Eng.	2023	DBLP DOI BibTeX RDF
16	Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu 0009, Lairong Yin	Four-input-C-element-based multiple-node-upset-self-recoverable latch designs.	Integr.	2023	DBLP DOI BibTeX RDF
16	Hui Xu, Jing Zhou, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Chaoming Liu	LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy.	Integr.	2023	DBLP DOI BibTeX RDF
16	Weizheng Wang, Jian Liang, Xiangqi Wang, Xianmin Pan, Shuo Cai	A secure scan architecture using parallel latch-based lock.	Integr.	2023	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Dongxing Ma, Runwu Ji, Huaguo Liang, Aibin Yan, Tai Song, Tianming Ni	Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix.	IEEE Trans. Aerosp. Electron. Syst.	2023	DBLP DOI BibTeX RDF
16	Zhengfeng Huang, Lanxi Duan, Yan Zhang, Tianming Ni, Aibin Yan	A Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch.	IEEE Trans. Aerosp. Electron. Syst.	2023	DBLP DOI BibTeX RDF
16	Seyedehsomayeh Hatefinasab, Alfredo Medina-Garcia, Diego Pedro Morales, Encarnación Castillo, Noel Rodriguez	Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch.	IEEE Access	2023	DBLP DOI BibTeX RDF
16	Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno	Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops.	IEEE Access	2023	DBLP DOI BibTeX RDF
16	Xin Chen, Yuxin Bai, Jianpeng Cao, Lei Wang, Xinjie Zhou, Ying Zhang, Weiqiang Liu 0001	Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Yan Liu, Yan Li 0084, Xu Cheng 0002, Jun Han 0003, Xiaoyang Zeng	A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF