Search results for "MPSoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
32	Ilya Issenin, Nikil D. Dutt	Using FORAY Models to Enable MPSoC Memory Optimizations.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	FORAY model, affine index expressions, Embedded systems, MPSoC, memory optimizations, scratch pad memory
32	Zai Jian Jia, Tomás Bautista, Antonio Núñez, Cayetano Guerra, Mario Hernández	Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoC.	ReConFig	2008	DBLP DOI BibTeX RDF	Design space exploration, platform-based design, tracking algorithm, heterogeneous MPSoC
32	Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya	A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications.	EMSOFT	2008	DBLP DOI BibTeX RDF	actor-oriented design, mpsoc scheduling, software synthesis
32	Ahsan Shabbir, Akash Kumar 0001, Bart Mesman, Henk Corporaal	Enabling MPSoC Design Space Exploration on FPGAs.	IMTIC	2008	DBLP DOI BibTeX RDF	FPGAs, MPSoC, FIFO, FSL
32	Márcio Oyamada, Flávio Rech Wagner, Marius Bonaciu, Wander O. Cesário, Ahmed Amine Jerraya	Software Performance Estimation in MPSoC Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF	cycle-accurate simulation model, software performance estimation, MPSoC design, software-dominated embedded systems, integrated methodology, bus-functional model, multiprocessor platform, MPEG4 encoder, neural networks, performance analysis, design space exploration, design validation
32	Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Ibrahim Kolcu	Tuning data replication for improving behavior of MPSoC applications.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	power consumption, cache coherence, MPSoC, data replication, optimizing compiler
31	Siavoosh Payandeh Azad, Gert Jervan, Michael Tempelmeier, Johanna Sepúlveda	CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones.	ISVLSI	2019	DBLP DOI BibTeX RDF
31	Oumaima Matoussi	Native simulation of MPSoC : instrumentation and modeling of non-functional aspects. (Simulation native des MPSoC : instrumentation et modélisation des aspects non fonctionnels).		2017	RDF
31	Christian Schöler	Novel scheduling strategies for future NoC and MPSoC architectures (Neue Scheduling Strategien für zukünftige NoC und MPSoC Architekturen)		2017	RDF
31	Philipp Wagner 0001, Lin Li 0046, Thomas Wild, Albrecht Mayer, Andreas Herkersdorf	What happens on an MPSoC stays on an MPSoC - unfortunately!	ISIC	2016	DBLP DOI BibTeX RDF
31	Paola Vallejo	Réutilisation de composants logiciels pour l'outillage de DSML dans le contexte des MPSoC. (Reuse of legacy code for DSML tools in the context of MPSoC).		2015	RDF
31	Narasinga Rao Miniskar	System Scenario Based Resource Management of Processing Elements on MPSoC (Systeemscenario-gebaseerd beheer van taken op multiprocessor systemen-op-chip (MPSoC)). (PDF / PS)		2012	RDF
31	Christopher Claus, Walter Stechele, Andreas Herkersdorf	Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme).	it Inf. Technol.	2007	DBLP DOI BibTeX RDF
28	Felipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo	On the energy-efficiency of software transactional memory.	SBCCI	2009	DBLP DOI BibTeX RDF	low power design, transactional memory, multi-core, MPSoC
28	Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou	Trace-driven workload simulation method for Multiprocessor System-On-Chips.	DAC	2009	DBLP DOI BibTeX RDF	MPSoC architecture exploration, simulation, performance estimation, workload model
28	Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian	Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	cosynthesis, energy, Real-time scheduling, MPSoC
28	Krutartha Patel, Sri Parameswaran	LOCS: a low overhead profiler-driven design flow for security of MPSoCs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	tensilica, architecture, mpsoc, execution profile, code injection
28	Salvatore Carta, Andrea Alimonda, Alessandro Pisano, Andrea Acquaviva, Luca Benini	A control theoretic approach to energy-efficient pipelined computation in MPSoCs.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	feedback-control techniques, parallel systems, MPSoC, DVFS
28	Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian	Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	cosynthesis, energy, real-time scheduling, MPSoC
28	Ana Lucia Varbanescu, Maik Nijhuis, Arturo González-Escribano, Henk J. Sips, Herbert Bos, Henri E. Bal	SP@CE - An SP-Based Programming Model for Consumer Electronics Streaming Applications.	LCPC	2006	DBLP DOI BibTeX RDF	SP@CE, MPSoC, programming models, consumer electronics, streaming applications, component-based framework
28	Taeweon Suh, Daehyun Kim 0001, Hsien-Hsin S. Lee	Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.	DAC	2005	DBLP DOI BibTeX RDF	heterogeneous, cache coherence, MPSoC, real-time and embedded systems, inter-processor communication
27	Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor	Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study.	SAMOS	2009	DBLP DOI BibTeX RDF
27	HaNeul Chon, Taewhan Kim	Timing variation-aware task scheduling and binding for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
27	Eric Cheung, Harry Hsieh, Felice Balarin	Partial order method for timed simulation of system-level MPSoC designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
27	Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Michela Milano, Luca Benini	A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	scheduling, Integer Programming, Constraint Programming, MPSoCs, allocation
27	Pramod Chandraiah, Rainer Dömer	Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
27	Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina	xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures.	PDP	2008	DBLP DOI BibTeX RDF	NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
27	Kimon Karras, Elias S. Manolakos	An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture.	FPL	2008	DBLP DOI BibTeX RDF
27	Feng Wang 0004, Yuan Xie 0001	Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations.	IPDPS	2008	DBLP DOI BibTeX RDF
27	Hao Shen, Frédéric Pétrot	MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method.	VLSI Design	2008	DBLP DOI BibTeX RDF
27	Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson	Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF	HW/SW, hardware space exploration, embedded system design, Multiprocessor System-on-Chip, real-time analysis, electrocardiogram algorithms
27	Youngmin Yi, Dohyung Kim 0007, Soonhoi Ha	Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Mirko Loghi, Luca Benini, Massimo Poncino	Power macromodeling of MPSoC message passing primitives.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	multiprocessor, system-on-chip, macromodeling, Communication primitives
27	Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin	MPSoC memory optimization using program transformation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, data cache, Data locality, compiler transformations
27	Jan Willem van den Brand, Marco Bekooij	Streaming consistency: a model for efficient MPSoC design.	DSD	2007	DBLP DOI BibTeX RDF
27	Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin	MPSoC memory optimization for digital camera applications.	DSD	2007	DBLP DOI BibTeX RDF
27	Soonhoi Ha	Model-based Programming Environment of Embedded Software for MPSoC.	ASP-DAC	2007	DBLP DOI BibTeX RDF
27	Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis 0001, Soo-Ik Chae, Ahmed Amine Jerraya	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.	SCOPES	2007	DBLP DOI BibTeX RDF
27	Marcio F. da S. Oliveira, Eduardo Wenzel Brião, Francisco Assis Moreira do Nascimento, Flávio Rech Wagner	Model driven engineering for MPSOC design space exploration.	SBCCI	2007	DBLP DOI BibTeX RDF	model driven engineering, design space exploration, multi-processor system-on-chip
27	Chengmo Yang, Alex Orailoglu	Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	multiprocessor task schedulihng, reconfiguration, adaptive execution
27	Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie 0001, Narayanan Vijaykrishnan	Variation-aware task allocation and scheduling for MPSoC.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Jason Schlessman, Mark Lodato, I. Burak Özer, Wayne H. Wolf	Heterogeneous MPSoC Architectures for Embedded Computer Vision.	ICME	2007	DBLP DOI BibTeX RDF
27	Gilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Architectural Issues in Homogeneous NoC-Based MPSoC.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
27	Youcef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu	Two-level tiling for MPSoC architecture.	ASAP	2007	DBLP DOI BibTeX RDF
27	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Constraint-driven bus matrix synthesis for MPSoC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
27	Heikki Kariniemi, Jari Nurmi	On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips.	FPL	2006	DBLP DOI BibTeX RDF
27	Ilya Issenin, Nikil D. Dutt	Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	customized memory hierarchy, hierarchical TDMA buses, data reuse, multiprocessor system-on-chip, communication synthesis
27	Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur	Application-Level Memory Optimization for MPSoC.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
27	Balal Ahmad, Ahmet T. Erdogan, Sami Khawam	Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC.	AHS	2006	DBLP DOI BibTeX RDF
27	Sergio Tota, Mario R. Casu, Luca Macchiarulo	Implementation analysis of NoC: a MPSoC trace-driven approach.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	networks on chip, wormhole routing, multiprocessor systems-on-chip, deflection routing
27	Kai Richter 0001, Marek Jersak, Rolf Ernst	A Formal Approach to MpSoC Performance Verification.	Computer	2003	DBLP DOI BibTeX RDF
23	Lin Huang 0002, Qiang Xu 0001	Performance yield-driven task allocation and scheduling for MPSoCs under process variation.	DAC	2010	DBLP DOI BibTeX RDF	performance yield, process variation, task scheduling
23	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Abstraction of RTL IPs into embedded software.	DAC	2010	DBLP DOI BibTeX RDF	RTL IP reuse, embedded software generation
23	Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar	Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	vlsi design, task allocation, multiprocessor systems-on-chip
23	Hassan A. Salamy, J. Ramanujam	A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip.	HiPEAC	2009	DBLP DOI BibTeX RDF
23	Xiang Xiao, Jaehwan John Lee	A Novel O(1) Deadlock Detection Methodology for Multiunit Resource Systems and Its Hardware Implementation for System-on-Chip.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF
23	Nader Bagherzadeh, Masaru Matsuura	Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip.	ITNG	2008	DBLP DOI BibTeX RDF	System-on-Chip, Network-on Chip, communication protocol
23	Diana Göhringer, Michael Hübner 0001, Volker Schatz, Jürgen Becker 0001	Runtime adaptive multi-processor system-on-chip: RAMPSoC.	IPDPS	2008	DBLP DOI BibTeX RDF
23	Simon Schliecker, Mircea Negrean, Gabriela Nicolescu, Pierre G. Paulin, Rolf Ernst	Reliable performance analysis of a multicore multithreaded system-on-chip.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	performance analysis, case study, multiprocessor, shared memory
23	Ying Yi, Wei Han 0001, Adam Major, Ahmet T. Erdogan, Tughrul Arslan	Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer.	SoCC	2008	DBLP DOI BibTeX RDF
23	Krutartha Patel, Sri Parameswaran	SHIELD: a software hardware design methodology for security and reliability of MPSoCs.	DAC	2008	DBLP DOI BibTeX RDF	bit flips, tensilica, architecture, multiprocessors, code injection
23	Srinivasan Murali, Luca Benini, Giovanni De Micheli	An Application-Specific Design Methodology for On-Chip Crossbar Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta 0001, Stephen P. Boyd, Giovanni De Micheli	Temperature-aware processor frequency assignment for MPSoCs using convex optimization.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	temperature-aware, MPSoCs, convex optimization, thermal
23	Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luca Benini	Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	realtime analysis, design space exploration, multiprocessor system-on-chip, biomedical, electrocardiogram algorithms
23	Parth Malani, Ying Tan, Qinru Qiu	Resource-aware High Performance Scheduling for Embedded MPSoCs With the Application of MPEG Decoding.	ICME	2007	DBLP DOI BibTeX RDF
23	Ewerson Carvalho, Ney Calazans, Fernando Moraes 0001	Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
23	Lochi Yu, Samar Abdi	Automatic SystemC TLM generation for custom communication platforms.	ICCD	2007	DBLP DOI BibTeX RDF
23	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	SiPS	2006	DBLP DOI BibTeX RDF
23	Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes 0001	Infrastructure for dynamic reconfigurable systems: choices and trade-offs.	SBCCI	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, NoCs, configuration controllers
23	Benaoumeur Senouci, Aimen Bouchhima, Frédéric Rousseau 0001, Frédéric Pétrot, Ahmed Amine Jerraya	Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: "Hardware-Dependent Software Oriented Approach".	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
23	Daewook Kim, Manho Kim, Gerald E. Sobelman	DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Mirko Loghi, Massimo Poncino	Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions.	DATE	2005	DBLP DOI BibTeX RDF
23	Mirko Loghi, Luca Benini, Massimo Poncino	Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor.	ICCD	2004	DBLP DOI BibTeX RDF
23	Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.	DAC	2004	DBLP DOI BibTeX RDF	data transfer architecture, memory server, message passing, network on chip, network interface, multiprocessor SoC
17	Chao Wang 0003, Junneng Zhang, Xuehai Zhou, Xiaojing Feng, Aili Wang 0003	A Flexible High Speed Star Network Based on Peer to Peer Links on FPGA.	ISPA	2011	DBLP DOI BibTeX RDF	FPGA, Network on Chip, MPSoC, Star Network, Programming Interfaces
17		CEDA Currents.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	EDAA Lifetime Achievement Award, FMCAD, GLSVLSI, IEEE Embedded Systems Letter, MEMOCODE, VLSI-SoC, MPSOC, NOCS, DAC
17	Pavel Ghosh, Arunabha Sen	Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints.	SAC	2010	DBLP DOI BibTeX RDF	greedy randomized heuristic, multi-processor system-on-chip (MPSoC), integer linear program, network-on-chip (NoC), voltage islanding
17	David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii	Thermal-aware floorplanning exploration for 3D multi-core architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	3D, floorplanning, MPSoC, temperature
17	Bastian Ristau, Torsten Limberg, Gerhard P. Fettweis	A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Performance evaluation, Mapping, Design space exploration, MPSoC, Packing
17	Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur	Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multiprocessors System on Chip (MPSoC), Optimizations, Multimedia, Parallelism, Memory, Multi-threading
17	Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest	Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
17	Laurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier, Stéphanie Chauvet	Multiprocessor Task Migration Implementation in a Reconfigurable Platform.	ReConFig	2009	DBLP DOI BibTeX RDF	RTOS for embedded platforms, Dynamic and partial reconfigurable systems, FPGA, MPSoC, Task migration
17	Taho Dorta, Jaime Jimenez, José Luis Martín 0001, Unai Bidarte, Armando Astarloa	Overview of FPGA-Based Multiprocessor Systems.	ReConFig	2009	DBLP DOI BibTeX RDF	MPoPC, Soft Multiprocessor, FPGA, MPSoC
17	Chenjie Yu, Xiangrong Zhou, Peter Petrov	Low-power inter-core communication through cache partitioning in embedded multiprocessors.	SBCCI	2009	DBLP DOI BibTeX RDF	low-power cache architectures, low-power cache coherence, MPSoC, on-chip communication
17	Peng Liu 0016, Chunchang Xiang, Xiaohang Wang 0001, Bingjie Xia, Yangfan Liu, Weidong Wang, Qingdong Yao	A NoC Emulation/Verification Framework.	ITNG	2009	DBLP DOI BibTeX RDF	multiprocessor systems-on-chip (MPSoC), FPGA, emulation, networks-on-chip (NoC)
17	Sjoerd Meijer, Hristo Nikolov, Todor P. Stefanov	On compile-time evaluation of process partitioning transformations for Kahn process networks.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	programming of MPSoC, transformations, Kahn process networks
17	Jason Wu, John Williams 0004, Neil W. Bergmann, Peter Sutton	Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, MPSoC, JPEG
17	Cesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino	Energy-optimal synchronization primitives for single-chip multi-processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	synchronization, mpsoc, power optimization
17	Hiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees A. Vissers, Marc Serughetti	The wild west: conquest of complex hardware-dependent software design.	DAC	2009	DBLP DOI BibTeX RDF	hardware-dependent software, heterogeneous/homogenous multi-core, symmetric/asymmetric multi-core, virtualization, multiprocessors, multi-core, MPSoC, programming model, virtual prototyping, many-core, ESL, virtual platform
17	Wayne H. Wolf	Middleware Architectures for Distributed Embedded Systems.	ISORC	2008	DBLP DOI BibTeX RDF	MPSoC, smart camera, middleware architecture
17	Philipp Mahr, Christian Lorchner, Harold Ishebabi, Christophe Bobda	SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGA, communication, networks, MPI, MPSoC
17	Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh	A Generic Network Interface Architecture for a Networked Processor Array (NePA).	ARCS	2008	DBLP DOI BibTeX RDF	Networked Processor Array (NePA), Multiprocessor System-on-Chip (MPSoC), Interconnection Network, Network Interface, Network-on-Chip (NoC)
17	Alain Pegatoquet, Filip Thoen, Denis Paterson	Virtual Reality for 2.5 G Wireless Communication Modem Software Development.	COMPSAC	2008	DBLP DOI BibTeX RDF	EGPRS, simulation, MPSoC, GSM, GPRS, Virtual platform
17	Giovanni Beltrame, Luca Fossati, Donatella Sciuto	Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	ReSP, Operating System, Emulation, OpenMP, MPSoC, codesign
17	Khaled Z. Ibrahim, François Bodin	Implementing Wilson-Dirac operator on the cell broadband engine.	ICS	2008	DBLP DOI BibTeX RDF	SIMD computer architecture, lattice qcd calculations, multi-core, MPSoC, cell broadband engine, data-parallel computing
17	Ümit Y. Ogras, Radu Marculescu, Diana Marculescu	Variation-adaptive feedback control for networks-on-chip with multiple clock domains.	DAC	2008	DBLP DOI BibTeX RDF	dynamic voltage-frequency scaling, voltage-frequency island, networks-on-chip, MPSoC, feedback control, parameter variation
17	Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf	Roundtable: Envisioning the Future for Multiprocessor SoC.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	multiprocessor, SoC, multicore, MPSoC, CPU, chip
17	Christophe Bobda, Thomas Haller, Felix Mühlbauer, Dennis Rech, Simon Jung	Design of adaptive multiprocessor on chip systems.	SBCCI	2007	DBLP DOI BibTeX RDF	FPGA, reconfigurability, MPSoC, NoC
17	Daniel Barcelos, Eduardo Wenzel Brião, Flávio Rech Wagner	A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	energy, MPSoC, NoC, task migration, memory organization
17	Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano	A data protection unit for NoC-based architectures.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	multiprocessor system-on-chip (MPSoC), security, embedded systems, data protection, network-on-chip (NoC)