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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 350 occurrences of 190 keywords
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Results
Found 312 publication records. Showing 312 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Wenxun Huang, Yujuan Quan, Deming Chen |
Improving broadcast efficiency in wireless sensor network time synchronization protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 48-55, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ran Manevich, Israel Cidon, Avinoam Kolodny |
Handling global traffic in future CMP NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 40-47, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Mario Paolone |
Towards the power networks of the future: needs, challenges and tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 20, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ümit Y. Ogras, Yunus Emre, Jianping Xu, Timothy Kam, Michael Kishinevsky |
Energy-guided exploration of on-chip network design for exa-scale computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 24-31, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | William Swartz, Yang-Yang Li, Amin Farshidi, Laleh Behjat |
Analysis of post-placement length estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 23, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Hongbo Zhang 0001, Yunfei Deng, Jongwook Kye, Martin D. F. Wong |
Impact of lithography retargeting process on low level interconnect in 20nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 3-10, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Xiangyu Chen, Jiale Liang, H.-S. Philip Wong |
Interconnect scaling into the sub-10nm regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 2, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ganapati Srinivasa |
Heterogeneity and interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 1, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Tuhina Samanta, Raka Sardar, Hafizur Rahaman 0001, Parthasarathi Dasgupta, Bhargab B. Bhattacharya |
A heuristic method for obstacle avoiding group Steiner tree construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 21, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Guang Sun, Shih-Hung Weng, Chung-Kuan Cheng, Bill Lin 0001, Lieguang Zeng |
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 11-18, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny |
Optimizing heterogeneous NoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 32-39, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ümit Y. Ogras, Michael Kishinevsky |
Design and optimization of communication fabrics: an industrial perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 19, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | |
International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012 ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 978-1-4503-1437-4 The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
1 | Ankit More, Baris Taskin |
A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 22, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang |
A SAT-based routing algorithm for cross-referencing biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-7, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Kwangok Jeong, Andrew B. Kahng |
Toward PDN resource estimation: A law of general power density. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-6, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Hung Viet Nguyen, Myunghwan Ryu, Youngmin Kim |
Performance and power analysis of through silicon via based 3D IC integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Janet Meiling Wang, Deming Chen (eds.) |
2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011 ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![IEEE Computer Society, 978-1-4577-1240-1 The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
1 | Selçuk Köse, Eby G. Friedman |
Distributed power network co-design with on-chip power supplies and decoupling capacitors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-5, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Chen Dong 0003, Chen Chen 0018, Subhasish Mitra, Deming Chen |
Architecture and performance evaluation of 3D CMOS-NEM FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-8, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Daehyun Kim 0004, Suyoun Kim, Sung Kyu Lim |
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-8, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu |
Stability and scalability in global routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-6, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Tilo Meister, Jens Lienig, Gisbert Thomke |
Interface optimization for improved routability in chip-package-board co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-8, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Yang-Yang Li, Logan M. Rakai, Laleh Behjat, Bill Swartz |
Wirelength and congestion estimation for routability-driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Ankit More, Baris Taskin |
Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Chen-Ling Chou, Radu Marculescu, Ümit Y. Ogras, Satrajit Chatterjee, Michael Kishinevsky, Dmitrii Loukianov |
System interconnect design exploration for embedded MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-8, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | George B. P. Bezerra, Stephanie Forrest, Payman Zarkesh-Ha |
Reducing energy and increasing performance with traffic optimization in many-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-7, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Andrew B. Kahng, Vaishnav Srinivas |
Mobile system considerations for SDRAM interface trends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-8, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Walter James Condley, Xuchu Hu, Matthew R. Guthaus |
Analysis of high-performance clock networks with RLC and transmission line effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 51-58, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani |
Worst-case performance prediction under supply voltage and temperature variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 91-96, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | George B. P. Bezerra, Stephanie Forrest, Melanie Forrest, Al Davis, Payman Zarkesh-Ha |
Modeling NoC traffic locality and energy consumption with rent's communication probability distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 3-8, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Peter Ramyalal Suaris |
Application of 3-D ICs to FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 15-16, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Di-An Li, Malgorzata Marek-Sadowska, Bill Lee |
On-chip em-sensitive interconnect structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 43-50, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Shekhar Y. Borkar |
Future of interconnect fabric: a contrarian view. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 1-2, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Rasit Onur Topaloglu |
3-2-1 contact: an experimental approach to the analysisof contacts in 45 nm and below. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 59-66, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Martin D. F. Wong |
Advances in PCB routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 33-34, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yulei Zhang 0002, James F. Buckwalter, Chung-Kuan Cheng |
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 69-76, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Hu Xu 0002, Vasilis F. Pavlidis, Giovanni De Micheli |
Process-induced skew variation for scaled 2-D and 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 17-24, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Patrick Groeneveld, Louis Scheffer, Dirk Stroobandt |
SLIP: 10 years ago and 10 years from now. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 67-68, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Koh Yamanaga, Kazuya Masu, Takashi Sato |
Application of generalized scattering matrix for prediction of power supply noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 83-90, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Daehyun Kim 0004, Sung Kyu Lim |
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 25-32, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Payman Zarkesh-Ha, George B. P. Bezerra, Stephanie Forrest, Melanie E. Moses |
Hybrid network on chip (HNoC): local buses with a global mesh architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 9-14, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ankit More, Baris Taskin |
Simulation based study of wireless RF interconnects for practical CMOs implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 35-42, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Jinhai Qiu, Sherief Reda, Soha Hassoun |
Fast, accurate a priori routing delay estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 77-82, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sherief Reda, Janet Meiling Wang (eds.) |
International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010 ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 978-1-4503-0037-7 The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
1 | Bahareh Fathi, Laleh Behjat, Logan M. Rakai |
A pre-placement net length estimation technique for mixed-size circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 45-52, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wire length estimation, placement, physical design, hypergraph clustering |
1 | Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng |
Predicting the worst-case voltage violation in a 3D power network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 93-98, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
worst case violation prediction, integer linear programming, leakage, clock gating, power networks |
1 | Saroj K. Nayak |
Carbon nanotube, graphene and atomic wires as next generation interconnects: current status and future promise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 109-110, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
quantum simulation, performance, design, reliability |
1 | Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam |
Multiband RF-interconnect for reconfigurable network-on-chip communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 107-108, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor |
1 | Yulei Zhang 0002, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng |
Prediction of high-performance on-chip global interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 61-68, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip global interconnection, performance prediction, transmission line |
1 | Kaustav Banerjee |
Graphene based nanomaterials for VLSI interconnect and energy-storage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 105-106, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
carbon nanomaterials, graphene nano-ribbons, interconnects, carbon nanotubes, passives |
1 | Duo Ding, David Z. Pan |
OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 11-18, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic networks-on-chip, low power, computer aided design, high performance |
1 | Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu |
Is overlay error more important than interconnect variations in double patterning? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 3-10, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
double patterning lithography, interconnect variations, overlay |
1 | Krishna Saraswat |
Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 111-112, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
copper, energy per bit, power, latency, bandwidth, optical interconnect, carbon nanotube |
1 | Chung-Kuan Cheng, Sherief Reda (eds.) |
The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 978-1-60558-576-5 The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
1 | Xiang Hu, Wenbo Zhao 0001, Peng Du, Yulei Zhang 0002, Amirali Shayan Arani, Christopher Pan, A. Ege Engin, Chung-Kuan Cheng |
On the bound of time-domain power supply noise based on frequency-domain target impedance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 69-76, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
target impedance, voltage noise, power distribution network |
1 | Joseph B. Cessna, Thomas R. Bewley |
Honeycomb-structured computational interconnects and their scalable extension to spherical domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 27-36, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
switchless interconnect, graph theory |
1 | Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic |
Floorplan-based FPGA interconnect power estimation in DSP circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 53-60, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, low power, interconnects, power estimation |
1 | Robert Fischbach, Jens Lienig, Tilo Meister |
From 3D circuit technologies and data structures to interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 77-84, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3d floorplanning, three-dimensional circuits, data structures, 3d integration, interconnect prediction |
1 | Bill R. Bottoms |
Interconnect solutions for TeraScale computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 1-2, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interconnect |
1 | Peng Sun, Rong Luo |
Closed-form solution for timing analysis of process variations on SWCNT interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 19-26, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interconnect, process variation, timing analysis, carbon nanotube, closed-form |
1 | Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto |
Integrated interlayer via planning and pin assignment for 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 99-104, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim |
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 85-92, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via |
1 | Sherief Reda |
Using circuit structural analysis techniques for networks in systems biology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 37-44, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
networks, systems biology, rent's rule |
1 | Wim Heirman, Joni Dambre, Dirk Stroobandt, Jan M. Van Campenhout |
Rent's rule and parallel programs: characterizing network traffic behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 87-94, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
network traffic behavior, locality, network-on-chip, characterization, Rent's rule |
1 | Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal |
Multi-core architectures and streaming applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 35-42, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC design, multi-core SoC design, system design, streaming applications |
1 | Simon W. Moore, Daniel Greenfield |
The next resource war: computation vs. communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 81-86, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fractal structure, temporal interconnect, tera-scale, networks-on-chip, CMP, communication complexity, Rent's rule |
1 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Interconnection lengths and delays estimation for communication links in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 1-10, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
communciation link, interconnection length prediction, FPGA |
1 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Global interconnections in FPGAs: modeling and performance analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 51-58, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, throughput, interconnection, wave-pipelined |
1 | Ion I. Mandoiu, Andrew A. Kennings (eds.) |
The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 978-1-59593-918-0 The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
1 | Duraid Madina, Makoto Taiji |
Circuit and physical design of the MDGRAPE-4 on-chip network links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 59-64, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
capacitive signalling, on-chip network links, periodic routing, quadrature |
1 | Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar |
Parallel vs. serial on-chip communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 43-50, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dual-rail, long-range interconnect serial link, parallel link, asynchronous circuits |
1 | Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger |
Efficient tiling patterns for reconfigurable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 11-18, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
octagonal, FPGA, tiling, hexagonal |
1 | Jin Hu, Jarrod A. Roy, Igor L. Markov |
Sidewinder: a scalable ILP-based router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 73-80, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
integer linear programming, global routing |
1 | Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny |
Timing optimization in logic with interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 19-26, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
interconnect, logic circuits, timing optimization, repeaters, logical effort |
1 | Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman 0001, Parthasarathi Dasgupta |
Revisiting fidelity: a case of elmore-based Y-routing trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 27-34, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
routing, Steiner trees, fidelity, rank correlation |
1 | Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell 0002 |
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 65-72, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cross-talk, interconnect, variability, Bit Error Rate(BER) |
1 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Impact of interconnect length changes on effective materials properties (dielectric constant). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 73-80, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, routing, interconnect, cycle time, interconnect model, rent, path delay |
1 | Wim Heirman, Joni Dambre, Jan Van Campenhout |
Synthetic traffic generation as a tool for dynamic interconnect evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 65-72, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dynamic interconnect requirements, reconfigurable interconnect, synthetic traffic generation |
1 | David Yeager, Darius Chiu, Guy G. Lemieux |
Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 33-40, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
congestion estimation, congestion localization, interconnect prediction, FPGA routing, FPGA interconnect |
1 | I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang |
Statistical circuit optimization considering device andinterconnect process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 47-54, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate and wire sizing, statistical optimization |
1 | Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma |
An accurate and efficient probabilistic congestion estimation model in x architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 25-32, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
congestion estimation, dynamic resource assignment, the X architecture, routability |
1 | Andrew A. Kennings, Ion I. Mandoiu (eds.) |
The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 978-1-59593-622-6 The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
1 | Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li 0001, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz |
The nuts and bolts of physical synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 89-94, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang |
Principle hessian direction based parameter reduction for interconnect networks with process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 41-46, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
principle Hessian directions, process variation, timing analysis |
1 | Avinoam Kolodny |
Networks on chips: keeping up with Rent's rule and Moore's law. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 55-56, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
routing, timing, interconnect, power, on-chip network, wires |
1 | Yu Hu 0002, King Ho Tam, Tong Jing, Lei He 0001 |
Fast dual-vdd buffering based on interconnect prediction and sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 95-102, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
routing, low power, interconnect, buffer insertion, dual-Vdd |
1 | Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh |
Tutorial on congestion prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 15-24, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
algorithm, prediction, delay, congestion, wirelength |
1 | Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli |
Early wire characterization for predictable network-on-chip global interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 57-64, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
early wire characterization, design methodology, NoCs, global interconnects |
1 | Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, Krishna Saraswat |
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 81-88, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Cu, bandwidth density, power, latency, optics, carbon nanotube, Global interconnects |
1 | Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu |
Exploiting on-chip data behavior for delay minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 103-110, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
coding, crosstalk, deep-submicron |
1 | Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu |
Adaptable wire-length distribution with tunable occupation probability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 1-8, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
wire-length distribution, rent's rule |
1 | Payman Zarkesh-Ha, Ken Doniger |
Stochastic interconnect layout sensitivity model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 9-14, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density |
1 | Prashant Saxena |
The scaling of interconnect buffer needs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 109-112, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect, scaling, buffers, repeaters |
1 | J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne |
Constant impedance scaling paradigm for interconnect synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 99-105, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transmission lines, interconnect optimization, global interconnects |
1 | Andrew B. Kahng, Rasit Onur Topaloglu |
Generation of design guarantees for interconnect matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 29-34, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
design guarantee generation, interconnect matching |
1 | Andrew B. Kahng, Sherief Reda |
A tale of two nets: studies of wirelength progression in physical design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 17-24, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
placer suboptimality, benchmarking, consistency, similarity, wirelength |
1 | Chandu Visweswariah |
Statistical analysis and optimization in the presence of gate and interconnect delay variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 37, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
variability, robust optimization, statistical timing |
1 | Wenyi Feng, Jonathan W. Greene |
Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 41-48, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
switching requirement, FPGAs, lower bound, entropy, interconnect, placement, rent's rule, programmable interconnect |
1 | Pranav Anbalagan, Jeffrey A. Davis |
A priori prediction of tightly clustered connections based on heuristic classification trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 9-15, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
wire length prediction |
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