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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3961 occurrences of 1777 keywords
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Results
Found 46124 publication records. Showing 46122 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh |
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 1025-1040, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP |
36 | Xi Huang 0002, Ze Zhao, Li Cui |
EasiSOC: Towards Cheaper and Smaller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSN ![In: Mobile Ad-hoc and Sensor Networks, First International Conference, MSN 2005, Wuhan, China, December 13-15, 2005, Proceedings, pp. 229-238, 2005, Springer, 3-540-30856-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SOC (System on Chip), wireless sensor network, embedded system, sensor node |
36 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 192-195, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
BFT, scalability, pipelining, bus, MP-SoC |
36 | Yunsi Fei, Niraj K. Jha |
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 274-281, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SOC synthesis, genetic algorithm, functional partitioning |
36 | Yuanbin Guo, Joseph R. Cavallaro |
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 44(3), pp. 195-217, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive, VLSI, low power, SoC, CDMA, interference cancellation |
36 | Hsin-hung Lin, Chih-wen Hsueh |
COS: A Configurable OS for Embedded SoC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia, pp. 242-245, 2006, IEEE Computer Society, 0-7695-2676-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Configurable OS, Embedded OS, Service-Oriented Architecture, SoC |
36 | Slo-Li Chu |
An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 281-290, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
EOPRS, SAGE II, SoC, Power Reduction, Processor-in-Memory |
35 | Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
Power-aware SoC test planning for effective utilization of port-scalable testers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 53:1-53:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
port-scalable testers, test access architecture, integer linear programming, SoC test |
35 | Eun-Tack Oh, Kwang-Sung Jung, Sung-Min Lee, Cheol-Hong Moon |
An Embedded SoC System IP to Trace Object and Distance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (1) ![In: Advanced Intelligent Computing Theories and Applications. With Aspects of Theoretical and Methodological Issues, 4th International Conference on Intelligent Computing, ICIC 2008, Shanghai, China, September 15-18, 2008, Proceedings, pp. 1214-1221, 2008, Springer, 978-3-540-87440-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Embedded SoC, IP Develop, Image Process, CCD Cameras |
35 | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
A System-layer Infrastructure for SoC Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 389-404, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SoC diagnosis, Processor and UDL logic self-testing, Memory, Infrastructure-IP |
35 | Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, WooKyeong Jeong, Tae-Jin Kim, Sung-Bae Park |
Performance monitor unit design for an AXI-based multi-core SoC platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007, pp. 1565-1572, 2007, ACM, 1-59593-480-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SOC platform, performance monitor, architecture exploration, AMBA, AXI |
35 | Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee, Hoi-Jun Yoo |
A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 238-243, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mobile multimedia SoC, programmable 3D graphics, low power design |
35 | Myeong-Chul Park, Young-Joo Kim, Ingeol Chun, Seok-Wun Ha, Yong-Kee Jun |
A GDB-Based Real-Time Tracing Tool for Remote Debugging of SoC Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Advances in Hybrid Information Technology, First International Conference, ICHIT 2006, Jeju Island, Korea, November 9-11, 2006, Revised Selected Papers, pp. 490-499, 2006, Springer, 978-3-540-77367-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SoC Program, GDB, Remote Debugging, Real-time Tracing, JTAG |
35 | Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel |
Retargetable generation of TLM bus interfaces for MP-SoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 249-254, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC |
35 | Yuan-Hsiu Chen, Pao-Ann Hsiung |
Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 489-498, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Operating System for Reconfigurable SoC, Hardware Scheduling, Placement, Dynamic Partial Reconfiguration |
35 | Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo |
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 352-357, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Bus Configuration, genetic algorithm, Optimization, Platform-based design, SoC design |
35 | Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya |
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 250-255, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
data transfer architecture, memory server, message passing, network on chip, network interface, multiprocessor SoC |
35 | Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka |
A SoC Test Strategy Based on a Non-Scan DFT Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 305-310, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
non-scan DFT, high level design and test, SoC test |
35 | Cristian Mateos, Marco Crasso, Alejandro Zunino, Marcelo R. Campo |
Separation of concerns in service-oriented applications based on pervasive design patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 849-853, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
contract-last service consumption, dependency injection, web services, service-oriented computing, separation of concerns |
35 | Yinong Chen, Ashutosh Sabnis, Marcos Garcia-Acosta |
Design and Performance Evaluation of a Service-Oriented Robotics Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 29th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2009 Workshops), 22-26 June 2009, Montreal, Québec, Canada, pp. 292-299, 2009, IEEE Computer Society, 978-0-7695-3660-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Zhengwei Chang, Guangze Xiong |
Hardware/Software Partitioning of Core-Based Systems Using Pulse Coupled Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (3) ![In: Advances in Neural Networks - ISNN 2007, 4th International Symposium on Neural Networks, ISNN 2007, Nanjing, China, June 3-7, 2007, Proceedings, Part III, pp. 1015-1023, 2007, Springer, 978-3-540-72394-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar |
A design methodology for application-specific networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 263-280, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
regular topology, architecture, methodology, networks-on-chip, Application-specific |
35 | Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis |
Networks on chips for high-end consumer-electronics TV system architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 148-153, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Anuja Sehgal, Krishnendu Chakrabarty |
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 422-427, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Rainer Andergassen, Peter Nijkamp, Aura Reggiani |
Analysis of regional labour market dynamics: In search of indications for self-organised criticality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Geogr. Syst. ![In: J. Geogr. Syst. 5(3), pp. 275-290, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
JEL classification C82, E32, R11, R23 |
35 | Tony Givargis, Frank Vahid |
Platune: a tuning framework for system-on-a-chip platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), pp. 1317-1327, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Mohamed Shalan, Vincent John Mooney III |
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 79-84, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management |
33 | Floriberto A. Lima |
Integration of Power Management Units onto the SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 458, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Lukasz Masko, Marek Tudruj |
Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 1-5 July 2008, Krakow, Poland, pp. 99-106, 2008, IEEE Computer Society, 978-0-7695-3472-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | KyungHo Kim |
Best ways to use billions of devices on a wireless mobile SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 810, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Shuang-shuang Han, Wan-zhong Chen |
The Algorithm of Dynamic Battery SOC Based on Mamdani Fuzzy Reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD (1) ![In: Fifth International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2008, 18-20 October 2008, Jinan, Shandong, China, Proceedings, Volume 1, pp. 439-443, 2008, IEEE Computer Society, 978-0-7695-3305-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Quming Zhou, Kedarnath J. Balakrishnan |
Test cost reduction for SoC using a combined approach to test data compression and test scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 39-44, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Reliability-Aware SOC Voltage Islands Partition and Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 343-348, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund |
PAM-SoC: A Toolchain for Predicting MPSoC Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 111-123, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
Floorplan driven leakage power aware IP-based SoC design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 118-123, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
floorplan, leakage power, temperature |
33 | Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout |
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 876-881, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan |
A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 751-756, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty |
SOC test planning using virtual test access architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(12), pp. 1263-1276, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Mark Litterick, Joachim Geishauser |
Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 64-78, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang |
RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 242-247, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee |
An SOC Test Integration Platform and Its Industrial Realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1213-1222, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |
Automatic interconnection rectification for SoC design verification based on the port order fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1), pp. 104-114, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Grant Martin |
Industry Needs and Expectations of SoC Design Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 146-147, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Mojy C. Chian |
Driving forces behind SOC development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 81, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Luca Benini, Giovanni De Micheli |
Networks on Chips: A New SoC Paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 35(1), pp. 70-78, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Sandeep Koranne, Vikram Iyengar |
On the Use of k-tuples for SoC Test Schedule Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 539-548, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan |
A systematic approach to synthesis of verification test-suites for modular SoC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 91-96, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Hongjiang Song |
Novel mixed domain VLSI signal processing circuits for high performance, low power and area penalty SOC signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 309-312, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Dipanjan Sengupta, Resve A. Saleh |
Supply voltage selection in Voltage Island based SoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 219-222, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Justin Xu, Cheng-Chew Lim |
Modelling Heterogeneous Interactions in SoC Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 98-103, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Alain J. Martin |
Can Asynchronous Techniques Help the SoC Designer? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 7-11, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Erik Larsson, Stina Edbom |
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 221-244, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Awalin Sopan, Matthew Berninger, Murali Mulakaluri, Raj Katakam |
Building a Machine Learning Model for the SOC, by the Input from the SOC, and Analyzing it for the SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VizSEC ![In: 15th IEEE Symposium on Visualization for Cyber Security, VizSec 2018, Berlin, Germany, October 22, 2018, pp. 1-8, 2018, IEEE, 978-1-5386-8194-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
31 | Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou |
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006, pp. 137-140, 2006, IEEE, 0-7803-9781-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Bing Guo, Dianhui Wang, Yan Shen, Zhishu Li |
A Hopfield neural network approach for power optimization of real-time operating systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 17(1), pp. 11-17, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SoC, Power optimization, RTOS, Hopfield neural network, Hardware-software partitioning |
31 | Miguel Matos, António Luís Sousa |
Dependable distributed OSGi environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MW4SOC ![In: Proceedings of the 3rd Workshop on Middleware for Service Oriented Computing, MW4SOC 2008, Leuven, Belgium, December 1-5, 2008, pp. 1-6, 2008, ACM, 978-1-60558-368-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
JAVA, virtualization, OSGi, SOC |
31 | |
FSA SiP Market and Patent Analysis Report. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 184-192, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
patent analysis, SiP market, SoC, packaging, SiP, system in package |
31 | Bing Guo, Dianhui Wang, Yan Shen, Zhishu Li |
Neurocomputing for Minimizing Energy Consumption of Real-Time Operating System in the System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (3) ![In: Neural Information Processing, 13th International Conference, ICONIP 2006, Hong Kong, China, October 3-6, 2006, Proceedings, Part III, pp. 1189-1198, 2006, Springer, 3-540-46484-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SoC, Power optimization, RTOS, Hopfield neural network, Hardware-software partitioning |
30 | Roger F. Woods, John V. McCanny, John G. McWhirter |
From Bit Level Systolic Arrays to HDTV Processor Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 35-49, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SoC architectures, DSP systems, pipelining, systolic arrays |
30 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 274-279, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs |
30 | Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar |
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 823-828, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mixed-signal cores, wafer-level defect screening, packaging cost reduction, big-D/small-A mixed-signal system-on-chip designs, mixed-signal SoC, consumer electronics market, wafer-level testing, correlation-based signature analysis, low-cost digital testers, generic cost model, mixed-signal test, digital logic, test cost reduction |
30 | Zahra Sadat Ebadi, André Ivanov |
Time Domain Multiplexed TAM: Implementation and Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10732-10737, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Time domain multiplexed TAM, Optimal test time, Test Access Mechanism (TAM), SoC testing, Embedded core testing |
30 | Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu |
Diagonal Test and Diagnostic Schemes for Flash Memorie. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 37-46, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
built-in self-diagnosis (BISD), memory diagnosis, built-in self-test (BIST), flash memory, memory testing, system-on-chip (SOC) |
30 | XuBang Shen |
Evolution of MPP SoC architecture techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(6), pp. 756-764, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
architecture, SoC, array processor, MPP |
30 | Kee Sup Kim, Ming Zhang 0017 |
Hierarchical Test Compression for SoC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 142-148, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SoC, hierarchical, test compression |
30 | Alicia Strang, David Potts, Shankar Hemmady |
A Holistic Approach to SoC Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 417-422, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
holistic verification, verification management, right-brained thinking, verification, debug, SoC, visualization environments |
30 | Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel |
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 871-878, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
64-bit Power Architecture, design dependency solution, digital thermal sensor, flexible IO, hardware content protection, high-performance latch, linear sensor, local clock buffer, multi-operating system, synergistic processor, real-time system, modularity, power management, Linux, multi-core, multi-threading, SOC, thermal management, design environment, CELL Processor, clock distribution, virtualization technology, SOI, correct-by-construction, re-use, design hierarchy |
30 | Defeng Sun, Jie Sun 0001 |
Strong Semismoothness of the Fischer-Burmeister SDC and SOC Complementarity Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 103(3), pp. 575-581, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Fischer-Burmeister function, strong semismoothness, SVD, SOC, SDC |
30 | Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee |
Zero-Skew Driven for RLC Clock Tree Construction in SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICITA (1) ![In: Third International Conference on Information Technology and Applications (ICITA 2005), 4-7 July 2005, Sydney, Australia, pp. 561-566, 2005, IEEE Computer Society, 0-7695-2316-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RLC delay model, Upward propagation, SoC, Clock tree, Zero skew |
30 | Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung |
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 499-502, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SoC, systemc, transaction-level modeling, TLM, simulation acceleration |
30 | Slo-Li Chu |
PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 10th International Conference on Parallel and Distributed Systems, ICPADS 2004, Newport Beach, CA, USA, July 7-9, 2004, pp. 690-, 2004, IEEE Computer Society, 0-7695-2152-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Pair-Selection Scheduling, Statement Analysis, SoC, Processor-in-Memory, SAGE |
30 | Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura |
Power analysis techniques for SoC with improved wiring models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 259-262, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
custom wire load model, SoC, power analysis, gate-level |
29 | Tseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho |
Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 365-374, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Platform based SoC, HW/SW co-simulation, verification |
29 | Patrice Gerin, Hao Shen, A. Chureau, Aimen Bouchhima, Ahmed Amine Jerraya |
Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 390-395, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
transaction accurate level, hardware/software interface modeling, multiprocessor SoC design, automatic generation tools, system-on-chip, SystemC, abstraction level, architecture exploration |
29 | Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara |
TAM Design and Optimization for Transparency-Based SoC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 381-388, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
TAM design, transparency, ILP, SoC test |
29 | Holger Blume, Thorsten von Sydow, Tobias G. Noll |
A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 43(2-3), pp. 223-233, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SoC communication, Petri nets, performance modeling, design space exploration, performance estimation |
29 | Umar Farooq 0009, Muhammad Saleem, Habibullah Jamal |
Parameterized FIR Filtering IP Cores for Reusable SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 554-559, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Finite Impulse Response (FIR) filter, Unfolded Direct Form (UDF), Folded Direct Form (FDF), Parameterized, SoC design, IP Core, Synthesis tools |
29 | Cheong-Ghil Kim, Dae-Young Jeong, Byung-Gil Kim, Shin-Dug Kim |
Reconfigurable Microarchitecture Based System-Level Dynamic Power Management SoC Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 39-49, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
quarter-pel interpolation, multimedia SoC, low-power, system architecture, H.264/AVC, motion compensation, memory access |
29 | Qiang Xu 0001, Nicola Nicolici |
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 2-7, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Multi-frequency Virtual TAM, SOC testing |
29 | Erik Larsson, Zebo Peng |
An Integrated Framework for the Design and Optimization of SOC Test Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 385-400, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
test access mechanism design, test resource placement, test conflicts, power consumption, test scheduling, SOC test, test resource partitioning |
29 | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
Embedded software-based self-testing for SoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 355-360, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
functional test, SoC test, VLSI test, microprocessor test |
29 | Bingjun Xiao, Yiyu Shi 0001, Lei He 0001 |
A universal state-of-charge algorithm for batteries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 687-692, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
state of charge, modeling, battery, circuit analysis |
29 | Subhomoy Chattopadhyay |
Low power design techniques for nanometer design processes: 65 nm and smaller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 5, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
65 nm, low power, embedded design |
29 | Éric Piel, Philippe Marquet, Jean-Luc Dekeyser |
Model Transformations for the Compilation of Multi-processor Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GTTSE ![In: Generative and Transformational Techniques in Software Engineering II, International Summer School, GTTSE 2007, Braga, Portugal, July 2-7, 2007. Revised Papers, pp. 459-473, 2007, Springer, 978-3-540-88642-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Praveen Bhojwani, Rabi N. Mahapatra |
An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 867-872, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan |
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 883-886, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Gabor Madl, Sudeep Pasricha, Luis Angel D. Bathen, Nikil D. Dutt, Qiang Zhu 0008 |
Formal performance evaluation of AMBA-based system-on-chip designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 6th ACM & IEEE International conference on Embedded software, EMSOFT 2006, October 22-25, 2006, Seoul, Korea, pp. 311-320, 2006, ACM, 1-59593-542-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
performance evaluation, model checking, system-on-chip |
29 | Lukasz Masko |
Task Scheduling for Dynamic SMP Clusters with Communication on the Fly for Bounded Number of Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: 4th International Symposium on Parallel and Distributed Computing (ISPDC 2005), 4-6 July 2005, Lille, France, pp. 13-20, 2005, IEEE Computer Society, 0-7695-2434-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Youhui Zhang, Liu Dong, Yu Gu 0005, Dongsheng Wang 0002 |
Exploring Design Space Using Transaction Level Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 589-599, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Lukasz Masko |
Scheduling Task Graphs for Execution in Dynamic SMP Clusters with Bounded Number of Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 6th International Conference, PPAM 2005, Poznan, Poland, September 11-14, 2005, Revised Selected Papers, pp. 871-878, 2005, Springer, 3-540-34141-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Zhihui Xiong, Sikun Li, Jihua Chen, Maojun Zhang |
Hardware/Software Co-design Environment for Hierarchical Platform-Based Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD (Selected papers) ![In: Computer Supported Cooperative Work in Design I, 8th International Conference, CSCWD 2004, Xiamen, China, May 26-28, 2004, Revised Selected Papers, pp. 242-251, 2004, Springer, 3-540-29400-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Ozgur Sinanoglu, Alex Orailoglu |
Partial Core Encryption for Performance-Efficient Test of SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 91-94, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri |
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 419-427, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Sandeep Kumar Goel, Erik Jan Marinissen |
Effective and Efficient Test Architecture Design for SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 529-538, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan |
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 11-13, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Srivaths Ravi 0001, Niraj K. Jha |
Synthesis of System-on-a-chip for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 149-156, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Reinaldo A. Bergamaschi, William R. Lee |
Designing systems-on-chip using cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 420-425, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong 0001, Xu Cheng 0001 |
FPGA prototyping of an amba-based windows-compatible SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 13-22, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, microsoft windows, amba, x86 |
28 | Michael Leuschel, Marisa Llorens, Javier Oliver 0001, Josep Silva, Salvador Tamarit |
SOC: a slicer for CSP specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PEPM ![In: Proceedings of the 2009 ACM SIGPLAN Symposium on Partial Evaluation and Semantics-based Program Manipulation, PEPM 2009, Savannah, GA, USA, January 19-20, 2009, pp. 165-168, 2009, ACM, 978-1-60558-327-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
software engineering, program slicing |
28 | Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka |
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 535-539, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
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