Search results for "SoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
36	Xi Huang 0002, Ze Zhao, Li Cui	EasiSOC: Towards Cheaper and Smaller.	MSN	2005	DBLP DOI BibTeX RDF	SOC (System on Chip), wireless sensor network, embedded system, sensor node
36	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BFT, scalability, pipelining, bus, MP-SoC
36	Yunsi Fei, Niraj K. Jha	Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	SOC synthesis, genetic algorithm, functional partitioning
36	Yuanbin Guo, Joseph R. Cavallaro	A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	adaptive, VLSI, low power, SoC, CDMA, interference cancellation
36	Hsin-hung Lin, Chih-wen Hsueh	COS: A Configurable OS for Embedded SoC Systems.	RTCSA	2006	DBLP DOI BibTeX RDF	Configurable OS, Embedded OS, Service-Oriented Architecture, SoC
36	Slo-Li Chu	An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture.	EUC	2005	DBLP DOI BibTeX RDF	EOPRS, SAGE II, SoC, Power Reduction, Processor-in-Memory
35	Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Power-aware SoC test planning for effective utilization of port-scalable testers.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	port-scalable testers, test access architecture, integer linear programming, SoC test
35	Eun-Tack Oh, Kwang-Sung Jung, Sung-Min Lee, Cheol-Hong Moon	An Embedded SoC System IP to Trace Object and Distance.	ICIC (1)	2008	DBLP DOI BibTeX RDF	Embedded SoC, IP Develop, Image Process, CCD Cameras
35	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	A System-layer Infrastructure for SoC Diagnosis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	SoC diagnosis, Processor and UDL logic self-testing, Memory, Infrastructure-IP
35	Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, WooKyeong Jeong, Tae-Jin Kim, Sung-Bae Park	Performance monitor unit design for an AXI-based multi-core SoC platform.	SAC	2007	DBLP DOI BibTeX RDF	SOC platform, performance monitor, architecture exploration, AMBA, AXI
35	Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee, Hoi-Jun Yoo	A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices.	ISLPED	2007	DBLP DOI BibTeX RDF	mobile multimedia SoC, programmable 3D graphics, low power design
35	Myeong-Chul Park, Young-Joo Kim, Ingeol Chun, Seok-Wun Ha, Yong-Kee Jun	A GDB-Based Real-Time Tracing Tool for Remote Debugging of SoC Programs.	ICHIT	2006	DBLP DOI BibTeX RDF	SoC Program, GDB, Remote Debugging, Real-time Tracing, JTAG
35	Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel	Retargetable generation of TLM bus interfaces for MP-SoC platforms.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC
35	Yuan-Hsiu Chen, Pao-Ann Hsiung	Hardware Task Scheduling and Placement in Operating Systems for Dynamically Reconfigurable SoC.	EUC	2005	DBLP DOI BibTeX RDF	Operating System for Reconfigurable SoC, Hardware Scheduling, Placement, Dynamic Partial Reconfiguration
35	Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design.	DATE	2004	DBLP DOI BibTeX RDF	Bus Configuration, genetic algorithm, Optimization, Platform-based design, SoC design
35	Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.	DAC	2004	DBLP DOI BibTeX RDF	data transfer architecture, memory server, message passing, network on chip, network interface, multiprocessor SoC
35	Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka	A SoC Test Strategy Based on a Non-Scan DFT Method.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	non-scan DFT, high level design and test, SoC test
35	Cristian Mateos, Marco Crasso, Alejandro Zunino, Marcelo R. Campo	Separation of concerns in service-oriented applications based on pervasive design patterns.	SAC	2010	DBLP DOI BibTeX RDF	contract-last service consumption, dependency injection, web services, service-oriented computing, separation of concerns
35	Yinong Chen, Ashutosh Sabnis, Marcos Garcia-Acosta	Design and Performance Evaluation of a Service-Oriented Robotics Application.	ICDCS Workshops	2009	DBLP DOI BibTeX RDF
35	Zhengwei Chang, Guangze Xiong	Hardware/Software Partitioning of Core-Based Systems Using Pulse Coupled Neural Networks.	ISNN (3)	2007	DBLP DOI BibTeX RDF
35	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	A design methodology for application-specific networks-on-chip.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	regular topology, architecture, methodology, networks-on-chip, Application-specific
35	Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis	Networks on chips for high-end consumer-electronics TV system architectures.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
35	Anuja Sehgal, Krishnendu Chakrabarty	Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures.	DATE	2004	DBLP DOI BibTeX RDF
35	Rainer Andergassen, Peter Nijkamp, Aura Reggiani	Analysis of regional labour market dynamics: In search of indications for self-organised criticality.	J. Geogr. Syst.	2003	DBLP DOI BibTeX RDF	JEL classification C82, E32, R11, R23
35	Tony Givargis, Frank Vahid	Platune: a tuning framework for system-on-a-chip platforms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
35	Mohamed Shalan, Vincent John Mooney III	Hardware support for real-time embedded multiprocessor system-on-a-chip memory management.	CODES	2002	DBLP DOI BibTeX RDF	Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management
33	Floriberto A. Lima	Integration of Power Management Units onto the SoC.	PATMOS	2008	DBLP DOI BibTeX RDF
33	Lukasz Masko, Marek Tudruj	Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly.	ISPDC	2008	DBLP DOI BibTeX RDF
33	KyungHo Kim	Best ways to use billions of devices on a wireless mobile SoC.	ASP-DAC	2008	DBLP DOI BibTeX RDF
33	Shuang-shuang Han, Wan-zhong Chen	The Algorithm of Dynamic Battery SOC Based on Mamdani Fuzzy Reasoning.	FSKD (1)	2008	DBLP DOI BibTeX RDF
33	Quming Zhou, Kedarnath J. Balakrishnan	Test cost reduction for SoC using a combined approach to test data compression and test scheduling.	DATE	2007	DBLP DOI BibTeX RDF
33	Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001	Reliability-Aware SOC Voltage Islands Partition and Floorplan.	ISVLSI	2006	DBLP DOI BibTeX RDF
33	Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund	PAM-SoC: A Toolchain for Predicting MPSoC Performance.	Euro-Par	2006	DBLP DOI BibTeX RDF
33	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Floorplan driven leakage power aware IP-based SoC design space exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	floorplan, leakage power, temperature
33	Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout	A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.	DATE	2005	DBLP DOI BibTeX RDF
33	Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan	A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
33	Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty	SOC test planning using virtual test access architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
33	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
33	Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang	RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
33	Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee	An SOC Test Integration Platform and Its Industrial Realization.	ITC	2004	DBLP DOI BibTeX RDF
33	Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou	Automatic interconnection rectification for SoC design verification based on the port order fault model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
33	Grant Martin	Industry Needs and Expectations of SoC Design Education.	MSE	2003	DBLP DOI BibTeX RDF
33	Mojy C. Chian	Driving forces behind SOC development.	CODES+ISSS	2003	DBLP DOI BibTeX RDF
33	Luca Benini, Giovanni De Micheli	Networks on Chips: A New SoC Paradigm.	Computer	2002	DBLP DOI BibTeX RDF
33	Sandeep Koranne, Vikram Iyengar	On the Use of k-tuples for SoC Test Schedule Representation.	ITC	2002	DBLP DOI BibTeX RDF
32	Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan	A systematic approach to synthesis of verification test-suites for modular SoC designs.	SoCC	2008	DBLP DOI BibTeX RDF
32	Hongjiang Song	Novel mixed domain VLSI signal processing circuits for high performance, low power and area penalty SOC signal processing.	SoCC	2008	DBLP DOI BibTeX RDF
32	Dipanjan Sengupta, Resve A. Saleh	Supply voltage selection in Voltage Island based SoC design.	SoCC	2008	DBLP DOI BibTeX RDF
31	Justin Xu, Cheng-Chew Lim	Modelling Heterogeneous Interactions in SoC Verification.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
31	Alain J. Martin	Can Asynchronous Techniques Help the SoC Designer?	VLSI-SoC	2006	DBLP DOI BibTeX RDF
31	Erik Larsson, Stina Edbom	Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
31	Awalin Sopan, Matthew Berninger, Murali Mulakaluri, Raj Katakam	Building a Machine Learning Model for the SOC, by the Input from the SOC, and Analyzing it for the SOC.	VizSEC	2018	DBLP DOI BibTeX RDF
31	Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou	Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.	SoCC	2006	DBLP DOI BibTeX RDF
31	Bing Guo, Dianhui Wang, Yan Shen, Zhishu Li	A Hopfield neural network approach for power optimization of real-time operating systems.	Neural Comput. Appl.	2008	DBLP DOI BibTeX RDF	SoC, Power optimization, RTOS, Hopfield neural network, Hardware-software partitioning
31	Miguel Matos, António Luís Sousa	Dependable distributed OSGi environment.	MW4SOC	2008	DBLP DOI BibTeX RDF	JAVA, virtualization, OSGi, SOC
31		FSA SiP Market and Patent Analysis Report.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	patent analysis, SiP market, SoC, packaging, SiP, system in package
31	Bing Guo, Dianhui Wang, Yan Shen, Zhishu Li	Neurocomputing for Minimizing Energy Consumption of Real-Time Operating System in the System-on-a-Chip.	ICONIP (3)	2006	DBLP DOI BibTeX RDF	SoC, Power optimization, RTOS, Hopfield neural network, Hardware-software partitioning
30	Roger F. Woods, John V. McCanny, John G. McWhirter	From Bit Level Systolic Arrays to HDTV Processor Chips.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	SoC architectures, DSP systems, pipelining, systolic arrays
30	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
30	Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar	AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	mixed-signal cores, wafer-level defect screening, packaging cost reduction, big-D/small-A mixed-signal system-on-chip designs, mixed-signal SoC, consumer electronics market, wafer-level testing, correlation-based signature analysis, low-cost digital testers, generic cost model, mixed-signal test, digital logic, test cost reduction
30	Zahra Sadat Ebadi, André Ivanov	Time Domain Multiplexed TAM: Implementation and Comparison.	DATE	2003	DBLP DOI BibTeX RDF	Time domain multiplexed TAM, Optimal test time, Test Access Mechanism (TAM), SoC testing, Embedded core testing
30	Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu	Diagonal Test and Diagnostic Schemes for Flash Memorie.	ITC	2002	DBLP DOI BibTeX RDF	built-in self-diagnosis (BISD), memory diagnosis, built-in self-test (BIST), flash memory, memory testing, system-on-chip (SOC)
30	XuBang Shen	Evolution of MPP SoC architecture techniques.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	architecture, SoC, array processor, MPP
30	Kee Sup Kim, Ming Zhang 0017	Hierarchical Test Compression for SoC Designs.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	SoC, hierarchical, test compression
30	Alicia Strang, David Potts, Shankar Hemmady	A Holistic Approach to SoC Verification.	ISQED	2008	DBLP DOI BibTeX RDF	holistic verification, verification management, right-brained thinking, verification, debug, SoC, visualization environments
30	Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel	Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	64-bit Power Architecture, design dependency solution, digital thermal sensor, flexible IO, hardware content protection, high-performance latch, linear sensor, local clock buffer, multi-operating system, synergistic processor, real-time system, modularity, power management, Linux, multi-core, multi-threading, SOC, thermal management, design environment, CELL Processor, clock distribution, virtualization technology, SOI, correct-by-construction, re-use, design hierarchy
30	Defeng Sun, Jie Sun 0001	Strong Semismoothness of the Fischer-Burmeister SDC and SOC Complementarity Functions.	Math. Program.	2005	DBLP DOI BibTeX RDF	Fischer-Burmeister function, strong semismoothness, SVD, SOC, SDC
30	Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee	Zero-Skew Driven for RLC Clock Tree Construction in SoC.	ICITA (1)	2005	DBLP DOI BibTeX RDF	RLC delay model, Upward propagation, SoC, Clock tree, Zero skew
30	Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung	Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	SoC, systemc, transaction-level modeling, TLM, simulation acceleration
30	Slo-Li Chu	PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture.	ICPADS	2004	DBLP DOI BibTeX RDF	Pair-Selection Scheduling, Statement Analysis, SoC, Processor-in-Memory, SAGE
30	Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura	Power analysis techniques for SoC with improved wiring models.	ISLPED	2002	DBLP DOI BibTeX RDF	custom wire load model, SoC, power analysis, gate-level
29	Tseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho	Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC.	SAMOS	2007	DBLP DOI BibTeX RDF	Platform based SoC, HW/SW co-simulation, verification
29	Patrice Gerin, Hao Shen, A. Chureau, Aimen Bouchhima, Ahmed Amine Jerraya	Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transaction accurate level, hardware/software interface modeling, multiprocessor SoC design, automatic generation tools, system-on-chip, SystemC, abstraction level, architecture exploration
29	Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara	TAM Design and Optimization for Transparency-Based SoC Test.	VTS	2007	DBLP DOI BibTeX RDF	TAM design, transparency, ILP, SoC test
29	Holger Blume, Thorsten von Sydow, Tobias G. Noll	A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	SoC communication, Petri nets, performance modeling, design space exploration, performance estimation
29	Umar Farooq 0009, Muhammad Saleem, Habibullah Jamal	Parameterized FIR Filtering IP Cores for Reusable SoC Design.	ITNG	2006	DBLP DOI BibTeX RDF	Finite Impulse Response (FIR) filter, Unfolded Direct Form (UDF), Folded Direct Form (FDF), Parameterized, SoC design, IP Core, Synthesis tools
29	Cheong-Ghil Kim, Dae-Young Jeong, Byung-Gil Kim, Shin-Dug Kim	Reconfigurable Microarchitecture Based System-Level Dynamic Power Management SoC Platform.	ICESS	2005	DBLP DOI BibTeX RDF	quarter-pel interpolation, multimedia SoC, low-power, system architecture, H.264/AVC, motion compensation, memory access
29	Qiang Xu 0001, Nicola Nicolici	Multi-Frequency Test Access Mechanism Design for Modular SOC Testing.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	Multi-frequency Virtual TAM, SOC testing
29	Erik Larsson, Zebo Peng	An Integrated Framework for the Design and Optimization of SOC Test Solutions.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test access mechanism design, test resource placement, test conflicts, power consumption, test scheduling, SOC test, test resource partitioning
29	Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey	Embedded software-based self-testing for SoC design.	DAC	2002	DBLP DOI BibTeX RDF	functional test, SoC test, VLSI test, microprocessor test
29	Bingjun Xiao, Yiyu Shi 0001, Lei He 0001	A universal state-of-charge algorithm for batteries.	DAC	2010	DBLP DOI BibTeX RDF	state of charge, modeling, battery, circuit analysis
29	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
29	Éric Piel, Philippe Marquet, Jean-Luc Dekeyser	Model Transformations for the Compilation of Multi-processor Systems-on-Chip.	GTTSE	2007	DBLP DOI BibTeX RDF
29	Praveen Bhojwani, Rabi N. Mahapatra	An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs.	ISQED	2007	DBLP DOI BibTeX RDF
29	Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan	Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.	DAC	2007	DBLP DOI BibTeX RDF
29	Gabor Madl, Sudeep Pasricha, Luis Angel D. Bathen, Nikil D. Dutt, Qiang Zhu 0008	Formal performance evaluation of AMBA-based system-on-chip designs.	EMSOFT	2006	DBLP DOI BibTeX RDF	performance evaluation, model checking, system-on-chip
29	Lukasz Masko	Task Scheduling for Dynamic SMP Clusters with Communication on the Fly for Bounded Number of Resources.	ISPDC	2005	DBLP DOI BibTeX RDF
29	Youhui Zhang, Liu Dong, Yu Gu 0005, Dongsheng Wang 0002	Exploring Design Space Using Transaction Level Models.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
29	Lukasz Masko	Scheduling Task Graphs for Execution in Dynamic SMP Clusters with Bounded Number of Resources.	PPAM	2005	DBLP DOI BibTeX RDF
29	Zhihui Xiong, Sikun Li, Jihua Chen, Maojun Zhang	Hardware/Software Co-design Environment for Hierarchical Platform-Based Design.	CSCWD (Selected papers)	2004	DBLP DOI BibTeX RDF
29	Ozgur Sinanoglu, Alex Orailoglu	Partial Core Encryption for Performance-Efficient Test of SOCs.	ICCAD	2003	DBLP DOI BibTeX RDF
29	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.	DFT	2002	DBLP DOI BibTeX RDF
29	Sandeep Kumar Goel, Erik Jan Marinissen	Effective and Efficient Test Architecture Design for SOCs.	ITC	2002	DBLP DOI BibTeX RDF
29	Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan	Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
29	Srivaths Ravi 0001, Niraj K. Jha	Synthesis of System-on-a-chip for Testability.	VLSI Design	2001	DBLP DOI BibTeX RDF
29	Reinaldo A. Bergamaschi, William R. Lee	Designing systems-on-chip using cores.	DAC	2000	DBLP DOI BibTeX RDF
28	Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong 0001, Xu Cheng 0001	FPGA prototyping of an amba-based windows-compatible SoC.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, microsoft windows, amba, x86
28	Michael Leuschel, Marisa Llorens, Javier Oliver 0001, Josep Silva, Salvador Tamarit	SOC: a slicer for CSP specifications.	PEPM	2009	DBLP DOI BibTeX RDF	software engineering, program slicing
28	Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka	A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management.	ASP-DAC	2009	DBLP DOI BibTeX RDF