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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 845 occurrences of 538 keywords
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Results
Found 5134 publication records. Showing 5134 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner |
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 216-227, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith |
An Application Specific Memory Characterization Technique for Co-processor Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007, pp. 353-358, 2007, IEEE Computer Society, 978-1-4244-1026-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Angelos D. Keromytis, Jason L. Wright, Theo de Raadt, Matthew Burnside |
Cryptography as an operating system service: A case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 24(1), pp. 1-38, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
authentication, digital signatures, Encryption, hash functions, cryptographic protocols |
28 | Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, Johannes Wolkerstorfer |
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 430-444, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Sunil Kim |
Pattern Matching Acceleration for Network Intrusion Detection Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 289-298, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Young-Il Kim, Chong-Min Kyung |
Automatic translation of behavioral testbench for fully accelerated simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 218-221, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Kenneth J. Turner, Qian Bing |
Protocol Techniques for Testing Radiotherapy Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2002, 22nd IFIP WG 6.1 International Conference Houston, Texas, USA, November 11-14, 2002, Proceedings, pp. 81-96, 2002, Springer, 3-540-00141-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein |
Reconfigurable Computing: A New Business Model and its Impact on SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 103-111, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar |
Simulation of a Digital Neuro-Chip for Spiking Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (4) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 4, pp. 490-498, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001 |
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Fifth International Workshop on Hardware/Software Codesign, CODES/CASHE 1997, March 24-26, 1997, Braunschweig, Germany, pp. 141-145, 1997, IEEE Computer Society, 0-8186-7895-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
structural programmable co-processors, design space exploration, performance estimation |
28 | Jason Cong, John Peck |
On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 246-248, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002 |
Two-Level Hardware/Software Partitioning Using CoDe-X. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), March 11-15, 1996, Friedrichshafen, Germany., pp. 395-, 1996, IEEE Computer Society, 0-8186-7355-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002 |
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Forth International Workshop on Hardware/Software Codesign, CODES 1996, Pittsburgh, PA, USA, March 18-20, 1996, pp. 77-84, 1996, IEEE Computer Society, 0-8186-7243-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002, Helmut Reinig |
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 81-84, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
27 | Wen Su, Ling Wang, Menghao Su, Su Liu |
A Processor-DMA-Based Memory Copy Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: Sixth International Conference on Networking, Architecture, and Storage, NAS 2011, Dalian, China, 28-30 July, 2011, pp. 225-229, 2011, IEEE Computer Society, 978-1-4577-1172-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
memory copy, accelerator, processor, DMA |
27 | John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank |
A Task-Centric Memory Model for Scalable Accelerator Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(1), pp. 29-39, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
software coherence, parallel architecture, accelerator, memory model |
27 | Diem Tran, Thi To, Thuan Huynh, Phuong Nguyen |
Designing a Harware Accelerator for Face Recognition Using Vector Quantization and Principal Component Analysis as a Component of SoPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 82-86, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
DSP using FPGA, Face Recognition, PCA, Vector Quantization, Hardware Accelerator, SoPC |
27 | Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic |
MemTracker: An accelerator for memory debugging and monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(2), pp. 5:1-5:33, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
memory access monitoring, debugging, Accelerator |
27 | Cui-Xia Li, Wei-Ming Liu 0003, Yi Tang |
A New 12-channel Hand-Held GPS Accelerator Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCM ![In: International Conference on Networked Computing and Advanced Information Management, NCM 2009, Fifth International Joint Conference on INC, IMS and IDC: INC 2009: International Conference on Networked Computing, IMS 2009: International Conference on Advanced Information Management and Service, IDC 2009: International Conference on Digital Content, Multimedia Technology and its Applications, Seoul, Korea, August 25-27, 2009, pp. 1705-1708, 2009, IEEE Computer Society, 978-0-7695-3769-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
GPS accelerator, DCO, Correlator, PLL, LUT |
27 | Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing |
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 48-53, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
temporal parallelism, macro-pipeline, FPGA accelerator, matrix multiplication |
27 | Shay Horovitz, Danny Dolev |
Collabory: A Collaborative Throughput Stabilizer & Accelerator for P2P Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WETICE ![In: 17th IEEE International Workshops on Enabling Technologies: Infrastructures for Collaborative Enterprises, WETICE 2008, Rome, Italy, June 23-25, 2008, Proceedings, pp. 115-120, 2008, IEEE Computer Society, 978-0-7695-3315-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Collabory, Stable, Collaboration, Stabilizer, P2P, Throughput, Bandwidth, Accelerator |
27 | Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq |
A Hardware Accelerator for Maze Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(1), pp. 141-145, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
banked memory, three-stage pipelines, hardware accelerator, circuit layout CAD, maze routing |
27 | Paul Kenyon, Prathima Agrawal, Sharad C. Seth |
High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 97-106, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
front-end DAG compiler, hand vs. compiled microcode, microcode compiler, programming environment for CAD, space/time overhead, code generation, hardware accelerator, performance data |
27 | Rami G. Melhem |
A Systolic Accelerator for the Iterative Solution of Sparse Linear Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(11), pp. 1591-1595, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
stripe structures, preconditioned conjugate gradient, iterative solution, nonzero elements, systolic accelerator, computationally irregular problems, systolic networks, parallel processing, iterative methods, systolic arrays, matrix algebra, buffering, cellular arrays, sparse matrix, special purpose computers, sparse linear systems, data movement |
26 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 51-60, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
26 | Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke |
Modulo scheduling for highly customized datapaths to increase hardware reusability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 124-133, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
programmable asic, modulo scheduling, loop accelerator |
26 | Daniel Dietterle |
Embedded system protocol design flow based on SDL: from specification to hardware/software implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SimuTools ![In: Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, Networks and Systems & Workshops, SimuTools 2008, Marseille, France, March 3-7, 2008, pp. 59, 2008, ICST/ACM, 978-963-9799-20-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
protocol accelerator, embedded systems, SDL, protocol engineering, IEEE 802.15.3 |
26 | Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto |
A Coprocessor for the Final Exponentiation of the eta T Pairing in Characteristic Three. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WAIFI ![In: Arithmetic of Finite Fields, First International Workshop, WAIFI 2007, Madrid, Spain, June 21-22, 2007, Proceedings, pp. 25-39, 2007, Springer, 978-3-540-73073-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
final exponentiation, FPGA, hardware accelerator, ? T pairing, characteristic three |
26 | Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem |
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 230-241, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique |
26 | Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto |
An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 97-104, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nT pairing, FPGA, elliptic curve, hardware accelerator, Tate pairing, characteristic three |
26 | Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto |
Arithmetic Operators for Pairing-Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 239-255, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, elliptic curve, hardware accelerator, finite field arithmetic, ? T pairing |
26 | Cristian Coarfa, Peter Druschel, Dan S. Wallach |
Performance analysis of TLS Web servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 24(1), pp. 39-69, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RSA accelerator, secure Web servers, Internet, e-commerce, TLS |
26 | Kenneth J. Turner |
Test generation for radiotherapy accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 7(4), pp. 361-375, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Lotos (Language Of Temporal Ordering Specification), Test generation, Accelerator, Radiotherapy |
26 | Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner |
Exploring the design space of LUT-based transparent accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 11-21, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
accelerator design, embedded processing, efficient computation |
26 | Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto |
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 412-426, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
tower fields, hardware accelerator, Tate pairing, characteristic three |
26 | Guido Fioretti |
The investment acceleration principle revisited by means of a neural network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 13(1), pp. 16-23, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Accelerator, Self-organising maps (SOM), Investment |
26 | Johann Großschädl |
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 384-393, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency |
26 | Youngmin Hur, Stephen A. Szygenda |
Special purpose array processor for digital logic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 28st Annual Simulation Symposium (SS '95), April 25-28, 1995, Santa Barbara, California, USA, pp. 297-302, 1995, IEEE Computer Society, 0-8186-7091-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost |
26 | Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda |
Statistics on concurrent fault and design error simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 622-627, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
concurrent fault/design error simulation, design error simulation processes, c-sim, gate level concurrent simulator, event based statistics, gate evaluation statistics, simulator developers, hardware accelerator designers, design options, parallel algorithms, formal verification, circuit analysis computing, design verification, memory requirements, experimental data, concurrent simulators |
26 | Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang |
VLSI design of densely-connected array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 492-497, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets |
26 | Dejan Raskovic, Emil Jovanov, Aleksandar Janicijevic, Veljko M. Milutinovic |
An implementation of hash based ATM router chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 32-40, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ATM router chip, hash based, large size routing tables, hash-based hardware accelerator, standard RAM, asynchronous transfer mode, storage management, telecommunication network routing, file organisation, telecommunication computing, hardware support |
20 | Achraf El Bouazzaoui, Abdelkader Hadjoudja, Omar Mouhib, Nazha Cherkaoui |
FPGA-based ML adaptive accelerator: A partial reconfiguration approach for optimized ML accelerator utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Array ![In: Array 21, pp. 100337, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Hyeong-Ju Kang, Byung-Do Yang |
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 23(19), pp. 8104, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Jisu Kwon, Daejin Park |
Work-in-Progress: Micro-Accelerator-in-the-Loop Framework for MCU Integrated Accelerator Peripheral Fast Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: International Conference on Embedded Software, EMSOFT 2023, Hamburg, Germany, September 17-22, 2023, pp. 15-16, 2023, ACM / IEEE, 979-8-4007-0291-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Junfei Tang, Luming Zhang |
An Adaptive Feature Recognition Algorithm and Its Hardware Accelerator for Arc Fault Recognition: The hardware accelerator of the algorithm is improved from the discrete wavelet transform algorithm and is used for power grid arc fault detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAI ![In: ICCAI '22: 8th International Conference on Computing and Artificial Intelligence, Tianjin, China, March 18 - 21, 2022, pp. 375-379, 2022, ACM, 978-1-4503-9611-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
20 | Venkata Krishnan, Olivier Serres, Michael Blocksome |
COnfigurable Network Protocol Accelerator (COPA) † : An Integrated Networking/Accelerator Hardware/Software Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: IEEE Symposium on High-Performance Interconnects, HOTI 2020, Piscataway, NJ, USA, August 19-21, 2020, pp. 17-24, 2020, IEEE, 978-1-7281-9589-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Zhengyu Chen 0002, Hai Zhou 0001, Jie Gu 0001 |
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(11), pp. 2655-2667, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Zhengyu Chen 0002, Hai Zhou 0001, Jie Gu 0001 |
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018, pp. 163-170, 2018, IEEE Computer Society, 978-1-5386-8477-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Bain Syrowik, Blair Fort, Stephen Dean Brown |
Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018, Toronto, ON, Canada, June 20-22, 2018, pp. 12:1-12:6, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano |
Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, September 4-8, 2017, pp. 1-4, 2017, IEEE, 978-9-0903-0428-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Jonas Hahnfeld, Christian Terboven, James Price, Hans-Joachim Pflug, Matthias S. Müller |
Evaluation of Asynchronous Offloading Capabilities of Accelerator Programming Models for Multiple Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WACCPD@SC ![In: Accelerator Programming Using Directives - 4th International Workshop, WACCPD 2017, Held in Conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2017, Denver, CO, USA, November 13, 2017, Proceedings, pp. 160-182, 2017, Springer, 978-3-319-74895-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Jan Gray |
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1606.01037, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
20 | Jan Gray |
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Washington, DC, USA, May 1-3, 2016, pp. 17-20, 2016, IEEE Computer Society, 978-1-5090-2356-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Thilo Friedrich |
Conceptual reasoning in the development of particle accelerator control systems: A case study on controls for a novel accelerator design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoSE ![In: 11th System of Systems Engineering Conference, SoSE 2016, Kongsberg, Norway, June 12-16, 2016, pp. 1-6, 2016, IEEE, 978-1-4673-8727-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Akihiro Hayashi, Jun Shirako, Ettore Tiotto, Robert Ho, Vivek Sarkar |
Exploring Compiler Optimization Opportunities for the OpenMP 4.× Accelerator Model on a POWER8+GPU Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WACCPD@SC ![In: Third Workshop on Accelerator Programming Using Directives, WACCPD@SC 2016, Salt Lake City, UT, USA, November 14, 2016, pp. 68-78, 2016, IEEE Computer Society, 978-1-5090-6152-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Masahiro Nakao, Hitoshi Murai, Takenori Shimosaka, Akihiro Tabuchi, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato |
XcalableACC: extension of XcalableMP PGAS language using OpenACC for accelerator clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WACCPD@SC ![In: Proceedings of the First Workshop on Accelerator Programming using Directives, WACCPD '14, New Orleans, Louisiana, USA, November 16-21, 2014, pp. 27-36, 2014, IEEE Computer Society, 978-1-4799-7023-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Seyong Lee, Jeffrey S. Vetter |
OpenARC: extensible OpenACC compiler framework for directive-based accelerator programming study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WACCPD@SC ![In: Proceedings of the First Workshop on Accelerator Programming using Directives, WACCPD '14, New Orleans, Louisiana, USA, November 16-21, 2014, pp. 1-11, 2014, IEEE Computer Society, 978-1-4799-7023-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Vladimir Korkhov, A. Ivanov, Natalia V. Kulabukhova, Alexander V. Bogdanov, Serge N. Andrianov |
Virtual Accelerator: Distributed Environment for Modeling Beam Accelerator Control System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (6) ![In: Computational Science and Its Applications - ICCSA 2013 - 13th International Conference, Ho Chi Minh City, Vietnam, June 24-27, 2013, Proceedings, Part VI, pp. 166-169, 2013, IEEE Computer Society, 978-0-7695-5045-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Michael J. Lyons 0003, Mark Hempstead, Gu-Yeon Wei, David M. Brooks |
The accelerator store: A shared memory framework for accelerator-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 8(4), pp. 48:1-48:22, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Michael J. Lyons 0003, Mark Hempstead, Gu-Yeon Wei, David M. Brooks |
The Accelerator Store framework for high-performance, low-power accelerator-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 9(2), pp. 53-56, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Luciano Burgazzi, Paolo Pierini |
Reliability studies of a high-power proton accelerator for accelerator-driven system applications for nuclear waste transmutation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Reliab. Eng. Syst. Saf. ![In: Reliab. Eng. Syst. Saf. 92(4), pp. 449-463, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Zefu Dai, Nick Ni, Jianwen Zhu |
A 1 cycle-per-byte XML parsing accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 199-208, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bart, schema validation, string comparison, xml parsing, ethernet, bloom filter, dom, tree construction |
19 | Pierre Michaud, Yiannakis Sazeides, André Seznec |
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 237-246, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
activity migration, sequential performance, power, multicore, temperature, cache misses, manycore |
19 | Michael Wolfe |
Implementing the PGI Accelerator model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPGPU ![In: Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2010, Pittsburgh, Pennsylvania, USA, March 14, 2010, pp. 43-50, 2010, ACM, 978-1-60558-935-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Jeffrey Allred, Jack Coyne, William Lynch, Vincent Natoli, Joseph Grecco, Joel Morrissette |
Smith-Waterman implementation on a FSB-FPGA module using the Intel Accelerator Abstraction Layer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-4, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan |
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 287-292, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel |
Tradeoffs in designing accelerator architectures for visual computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 164-175, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic |
FlexiTaint: A programmable accelerator for dynamic taint propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 173-184, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Samar Yazdani, Joel Cambonie, Bernard Pottier |
Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 15-26, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coarse-grain architecture, shared-memory programming model, embedded systems, multimedia applications |
19 | Samar Yazdani, Joel Cambonie, Bernard Pottier |
Reconfiguralbe multimedia accelerator for mobile systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 287-290, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Fernando Pardo, Paula López Martinez 0001, Diego Cabello |
FPGA-based hardware accelerator of the heat equation with applications on infrared thermography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 179-184, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Patrick Akl, Andreas Moshovos |
Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 258-272, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Azzedine Boukerche, Jan Mendonca Correa, Alba Cristina Magalhaes Alves de Melo, Ricardo P. Jacobi, Adson Ferreira da Rocha |
An FPGA-Based Accelerator for Multiple Biological Sequence Alignment with DIALIGN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 71-82, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Mariano Fons, Francisco Fons, Enrique Cantó, Mariano López |
Design of a hardware accelerator for fingerprint alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 485-488, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Qing Wang 0045, Wenbo Shen, Yu Li, Zhenbo Zhu |
Design of IP Media Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China, pp. 1195-1198, 2007, IEEE Computer Society, 1-4244-1017-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Guo-An Jian, Chih-Da Chien, Jiun-In Guo |
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1569-1572, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Bruno Zatt, Valter Ferreira, Luciano Volcan Agostini, Flávio Rech Wagner, Altamiro Amadeu Susin, Sergio Bampi |
Motion Compensation Hardware Accelerator Architecture for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PSIVT ![In: Advances in Image and Video Technology, Second Pacific Rim Symposium, PSIVT 2007, Santiago, Chile, December 17-19, 2007, Proceedings, pp. 24-35, 2007, Springer, 978-3-540-77128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MPEG-4 AVC, Video Coding, H.264/AVC, Motion Compensation, Hardware Acceleration |
19 | Bart de Ruijsscher, Georgi Gaydadjiev, Jeroen Lichtenauer, Emile A. Hendriks |
FPGA accelerator for real-time skin segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2006, October 26-27, 2006, Seoul, Korea, conjunction with CODES+ISSS 2006, pp. 93-97, 2006, IEEE Computer Society, 0-7803-9783-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-Ming Huang |
A cost-effective reconfigurable accelerator for platform-based SOC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Akila Gothandaraman, G. Lee Warren, Gregory D. Peterson, Robert J. Harrison |
Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 177, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Young-Su Kwon, Chong-Min Kyung |
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1444-1456, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Joon Woo Cho, Hyun-Jin Choi, Seung-Ho Lim, Kyu Ho Park |
A Content Delivery Accelerator in Data-Intensive Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NPC ![In: Network and Parallel Computing, IFIP International Conference, NPC 2005, Beijing, China, November 30 - December 3, 2005, Proceedings, pp. 387-395, 2005, Springer, 3-540-29810-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Philippe Marchand, Purnendu Sinha |
A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 279-288, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mona Safar, M. Watheq El-Kharashi, Ashraf Salem |
FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 384-387, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hongtu Jiang, Håkan Ardö, Viktor Öwall |
Hardware accelerator design for video segmentation with multi-modal background modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1142-1145, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Yan-Chen Lu, Chun-Fu Shen, Chi-Kuang Chen, Ju-Lung Fann |
Performance-driven optimization for video accelerator design [video coding]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4521-4524, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin |
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4525-4528, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mona Safar, M. Watheq El-Kharashi, Ashraf Salem |
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 419-424, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | William D. Smith, Austars R. Schnore |
Towards an RCC-Based Accelerator for Computational Fluid Dynamics Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 30(3), pp. 239-261, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
re-configurable computing applications, computational fluid dynamics |
19 | John F. Keane, Christopher Bradley, Carl Ebeling |
A compiled accelerator for biological cell signaling simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 233-241, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
simulation, reconfigurable hardware, cell, biology, reactions |
19 | Lie-Quan Lee, Lixin Ge, Marc Kowalski, Zenghai Li, Cho-Kuen Ng, Gregory L. Schussman, Michael Wolf, Kwok Ko |
Solving Large Sparse Linear Systems in End-to-end Accelerator Structure Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Binu K. Mathew, Al Davis |
A loop accelerator for low power embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 6-11, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, low power design, VLIW |
19 | Giovanni Danese, Ivo De Lotto, Francesco Leporati, M. Scaricabarozzi, Alvaro Spelgatti |
An Accelerator for Double Precision Floating Point Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 11th Euromicro Workshop on Parallel, Distributed and Network-Based Processing (PDP 2003), 5-7 February 2003, Genova, Italy, pp. 57-, 2003, IEEE Computer Society, 0-7695-1875-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Marco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti |
A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey, pp. 173-179, 2003, IEEE Computer Society, 0-7695-2003-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | John A. Nestor |
FPGA Implementation of a Maze Routing Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 992-995, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Binu K. Mathew, Al Davis, Zhen Fang 0002 |
A low-power accelerator for the SPHINX 3 speech recognition system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 210-219, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
embedded systems, speech recognition, low power design, ASIC, special purpose hardware |
19 | Hong-Yi Huang, Shih-Lun Chen |
Threshold triggers and accelerator for deep submicron interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 143-146, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Edwin A. Hakkennes, Stamatis Vassiliadis |
Multimedia Execution Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(3), pp. 221-234, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
multimedia architectures, multimedia instruction set, multimedia processors, compound instructions, multimedia, hardware accelerators, subword parallelism, SIMD processors, vector architectures |
19 | Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott |
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 4th International Conference, ISC 2001, Malaga, Spain, October 1-3, 2001, Proceedings, pp. 220-234, 2001, Springer, 3-540-42662-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi |
Hardware Accelerator for Subgraph Isomorphism Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 283-284, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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