Search results for "boundary-scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
21	Oliver F. Haberl, Thomas Kropf	HIST: A hierarchical self test methodology for chips, boards, and systems.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	Boundary-scan architecture, hierarchical self test, self test synthesis, built-in self test (BIST), system test
21	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
21	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
21	Hao Zheng, Kewal K. Saluja, Rajiv Jain	Test application time reduction for scan based sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
21	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
21	Ajay Khoche, Erik Brunvand	A partial scan methodology for testing self-timed circuits.	VTS	1995	DBLP DOI BibTeX RDF	partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
21	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
21	Bapiraju Vinnakota, Nicholas J. Stessman	Reducing test application time in scan design schemes.	VTS	1995	DBLP DOI BibTeX RDF	scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques
21	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
21	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
21	Sridhar Narayanan, Melvin A. Breuer	Asynchronous multiple scan chain.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time
21	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
21	Bulent I. Dervisoglu	Features of a Scan and Clock Resource chip for providing access to board-level test functions.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	diagnostics bus, design-for-testability, scan, boundary scan, pseudorandom testing
19	Saman Adham, Sanjay Gupta	DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
18	Shih-Yu Yang, Christos A. Papachristou	A method for detecting interconnect DSM defects in systems on chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil G. Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts	Status of IEEE Testability Standards 1149.4, 1532 and 1149.6.	DATE	2004	DBLP DOI BibTeX RDF
18	Saghir A. Shaikh	IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver.	ITC	2004	DBLP DOI BibTeX RDF
18	Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung	Testing and Remote Field Update of Distributed Base Stations in a Wireless Network.	ITC	2004	DBLP DOI BibTeX RDF
18	Andrzej Rucinski 0002, Barrett Stetson, S. T. P. Brundavani	A DOT1 & DOT4 MOSIS - Compatible Library.	MSE	2003	DBLP DOI BibTeX RDF
18	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	MTDT	2002	DBLP DOI BibTeX RDF
18	Farzin Karimi, Fabrizio Lombardi	A Scan-Bist Environment for Testing Embedded Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
18	Sungbae Hwang, Jacob A. Abraham	Selective-run built-in self-test using an embedded processor.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	processor-based testing, built-in self-test, design for testability, SOC testing, pseudo-random number generator
18	Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi	Data Compression for System-on-Chip Testing Using ATE.	DFT	2002	DBLP DOI BibTeX RDF
18	Subhasish Mitra, Edward J. McCluskey, Samy Makar	Design for Testability and Testing of IEEE 1149.1 Tap Controller.	VTS	2002	DBLP DOI BibTeX RDF
18	Chun-Keung Lo, Philip C. H. Chan	An Efficient Structural Approach to Board Interconnect Diagnosis.	ASP-DAC	1999	DBLP DOI BibTeX RDF
18	Vladimír Székely, Cs. Márta, Zsolt Kohári, Márta Rencz	CMOS sensors for on-line thermal monitoring of VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
18	Al Bailey, Tim Lada, Jim Preston	Collateral ASIC Test.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
18	Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau	Lessons Learned from Practical Applications of BIST/B-S Technology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
16	Zhiwei Li, Zhongliang Pan	Research of the Automatic Testing Software on Boundary-scan Test.	ICMLC	2023	DBLP DOI BibTeX RDF
16	Libao Deng, Ning Sun, Ning Fu	Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs.	Integr.	2020	DBLP DOI BibTeX RDF
16	Asma Ben Ahmed, Olfa Mosbahi, Mohamed Khalgui, Zhiwu Li 0001	Boundary Scan Extension for Testing Distributed Reconfigurable Hardware Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
16	Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume	On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection.	3DIC	2019	DBLP DOI BibTeX RDF
16	Shuya Kikuchi, Hiroyuki Yotsuyanagi, Masaki Hashizume	On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC.	ITC-Asia	2019	DBLP DOI BibTeX RDF
16	Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume	Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design.	ATS	2018	DBLP DOI BibTeX RDF
16	Pok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong	An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages.	ATS	2017	DBLP DOI BibTeX RDF
16	Farnaz Fotovatikhah, Bahareh Naraghi, Fatemeh Tavakoli, Mahdiar Ghadiry	A New Approach to Model the Effect of Topology on Testing Using Boundary Scan.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
16	André V. Fidalgo, Andre Couto, Manuel C. Felgueiras, Gustavo R. Alves	Low cost boundary scan controller for didactic applications (IEEE 1149.1).	exp.at	2015	DBLP DOI BibTeX RDF
16	Terry Borroz	Considerations in the design of a boundary scan runtime library.	IEEE Instrum. Meas. Mag.	2014	DBLP DOI BibTeX RDF
16	Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya, Masaki Hashizume	On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan.	IEICE Trans. Inf. Syst.	2013	DBLP DOI BibTeX RDF
16	Louis Y. Ungar	Boundary scan as a system-level diagnostic tool.	IEEE Instrum. Meas. Mag.	2013	DBLP DOI BibTeX RDF
16	Geng-Ming Chiu, James Chien-Mo Li	A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
16	Bill Eklow	Managing Complex Boundary-Scan Operations.	IEEE Des. Test Comput.	2012	DBLP DOI BibTeX RDF
16	Stephen K. Sunter, Aubin Roy	Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan.	IEEE Des. Test Comput.	2012	DBLP DOI BibTeX RDF
16	João Carlos Cunha, Ricardo Barbosa 0003, Gilberto Rodrigues	On the Use of Boundary Scan for Code Coverage of Critical Embedded Software.	ISSRE	2012	DBLP DOI BibTeX RDF
16	Chun-Ming Huang, Chih-Chyau Yang, Chien-Ming Wu, Chih-Hsing Lin, Chun-Chieh Chiu, Yi-Jun Liu, Chun-Chieh Chu, Chun-Ping Lin, Wei-De Chien	Boundary scan test solution for MorPACK platform.	ISPACS	2012	DBLP DOI BibTeX RDF
16	Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume	A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
16	Stephen K. Sunter, Aubin Roy	Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan.	ITC	2011	DBLP DOI BibTeX RDF
16	Bashar Al-Khalifa	A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs.	Int. Arab J. Inf. Technol.	2010	DBLP BibTeX RDF
16	Shengjian Chen, Lei Xu	A boundary-scan test bus controller design for mixed-signal test.	WCNIS	2010	DBLP DOI BibTeX RDF
16	Stephen K. Sunter, Matthias Tilmann	BIST of I/O circuit parameters via standard boundary scan.	ITC	2010	DBLP DOI BibTeX RDF
16	Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón	A New Algorithm for the Selection of Control Cells in Boundary-Scan Interconnect Test.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF
16	Marcos Barcellos Hervé, Érika F. Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski	NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time.	LATW	2009	DBLP DOI BibTeX RDF
16	Adam W. Ley	Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture.	ITC	2009	DBLP DOI BibTeX RDF
16	Chwee Liong Tee, Tzyy Haw Tan, Chin Chuan Ng	Augmenting board test coverage with new intel powered opens boundary scan instruction.	ITC	2009	DBLP DOI BibTeX RDF
16	Steve Sunter, Kenneth P. Parker	Testing bridges to nowhere - combining Boundary Scan and capacitive sensing.	ITC	2009	DBLP DOI BibTeX RDF
16	Philip B. Geiger, Steve Butkovich	Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry.	ITC	2009	DBLP DOI BibTeX RDF
16	Dave F. Dubberke, James J. Grealish, Bill Van Dick	Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application.	ITC	2008	DBLP DOI BibTeX RDF
16	Dayton Norrgard, Kenneth P. Parker	Augmenting Boundary-Scan Tests for Enhanced Defect Coverage.	ITC	2008	DBLP DOI BibTeX RDF
16	Kenneth P. Parker, Neil G. Jacobson	Boundary-Scan Testing of Power/Ground Pins.	ITC	2008	DBLP DOI BibTeX RDF
16	Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker	Problems Using Boundary-Scan for Memory Cluster Tests.	ITC	2008	DBLP DOI BibTeX RDF
16	Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren	A practical approach to comprehensive system test & debug using boundary scan based test architecture.	ITC	2007	DBLP DOI BibTeX RDF
16	Ing. M. F. Breeuwsma	Forensic imaging of embedded systems using JTAG (boundary-scan).	Digit. Investig.	2006	DBLP DOI BibTeX RDF
16	Brian Foutz, Vivek Chickermane, Bing Li, Harry Linzer, Gary Kunselman	Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology.	ATS	2006	DBLP DOI BibTeX RDF
16	Bambang Suparjo, Adam W. Ley, Adam Cron, Heiko Ehrenberg	Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test.	ITC	2006	DBLP DOI BibTeX RDF
16	Heiko Ehrenberg	IEEE P1581 - Getting More Board Test Out of Boundary Scan.	ITC	2006	DBLP DOI BibTeX RDF
16	Ilka Reis, Peter Collins, Marc van Houcke	On-line Boundary-Scan Testing in Service of Extended Products.	ITC	2006	DBLP DOI BibTeX RDF
16	Yu-Cheng Fan, Hen-Wai Tsao	Boundary Scan Test Scheme for IP Core Identification via Watermarking.	IEICE Trans. Inf. Syst.	2005	DBLP DOI BibTeX RDF
16	David Bäckström, Gunnar Carlsson, Erik Larsson	Remote boundary-scan system test control for the ATCA standard.	ITC	2005	DBLP DOI BibTeX RDF
16	Peter Collins, Ilka Reis, Mikko Simonen, Marc van Houcke	A transparent solution for providing remote wired or wireless communication to board and system level boundary-scan architectures.	ITC	2005	DBLP DOI BibTeX RDF
16	Peter J. Ashenden	Boundary Scan Test Standards.	IEEE Des. Test Comput.	2003	DBLP BibTeX RDF
16	Hamimi Chemali, Abdelhakim Latoui, Chouki Aktouf	An Optical Boundary Scan Cell for On Line Testing of Embedded Systems.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
16	Uros Kac, R. Sedevcic, Franc Novak, Anton Biasizzo	Linux-based experimental boundary scan environment.	Microprocess. Microsystems	2002	DBLP DOI BibTeX RDF
16	William Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo	Unsafe board states during PC-based boundary-scan testing.	ITC	2001	DBLP DOI BibTeX RDF
16	Alan Albee	A practical guide to combining ICT & boundary scan testing.	ITC	2001	DBLP DOI BibTeX RDF
16	Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick	Frequency detection-based boundary-scan testing of AC coupled nets.	ITC	2001	DBLP DOI BibTeX RDF
16	Shih-Yu Yang, Christos A. Papachristou, Massood Tabib-Azar	Improving Bus Test Via IDDT and Boundary Scan.	DAC	2001	DBLP DOI BibTeX RDF
16	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A system level boundary scan controller board for VME applications [to CERN experiments].	ETW	2000	DBLP DOI BibTeX RDF
16	Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace	End-to-end testing for boards and systems using boundary scan.	ITC	2000	DBLP DOI BibTeX RDF
16	Stephen Harrison, Peter Collins, Greg Noeninckx	The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment.	ITC	2000	DBLP DOI BibTeX RDF
16	Kenneth P. Parker	System issues in boundary-scan board test.	ITC	2000	DBLP DOI BibTeX RDF
16	Michael S. Heutmaker, D. K. Le	An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan.	IEEE Commun. Mag.	1999	DBLP DOI BibTeX RDF
16	Jongchul Shin, Hyunjin Kim, Sungho Kang 0001	At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks.	DATE	1999	DBLP DOI BibTeX RDF
16	Adam W. Ley	The integration of boundary-scan test methods to a mixed-signal environment.	ITC	1999	DBLP DOI BibTeX RDF
16	Yasunori Sameshima, Tomoo Fukazawa	A DFT Methodology for High-Speed MCM Based on Boundary-Scan Techniques.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
16	Amitava Majumdar 0002, Michio Komoda, Tim Ayres	Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan.	VTS	1998	DBLP DOI BibTeX RDF
16	T. A. García, Antonio J. Acosta 0001, José L. Huertas, J. M. Mora, J. Ramos	Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.	VTS	1998	DBLP DOI BibTeX RDF
16	Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen	Boundary scan BIST methodology for reconfigurable systems.	ITC	1998	DBLP DOI BibTeX RDF
16	William J. Hughes III	System-Level Boundary-Scan in a Highly Integrated Switch.	ITC	1997	DBLP DOI BibTeX RDF
16	Matthew Boutin, Peter Dziel	Application of Boundary Scan in a Fault Tolerant Computer System.	ITC	1996	DBLP DOI BibTeX RDF
16	Keith Lofstrom	Early Capture for Boundary Scan Timing Measurements.	ITC	1996	DBLP DOI BibTeX RDF
16	Wuudiann Ke	Backplane Interconnect Test in a Boundary-Scan Environment.	ITC	1996	DBLP DOI BibTeX RDF
16	D. Eugene Wedge, Tom Conner	A Roadmap for Boundary-Scan Test Reuse.	ITC	1996	DBLP DOI BibTeX RDF
16	Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee	A New Architecture for Analog Boundary Scan.	ISCAS	1995	DBLP DOI BibTeX RDF
16	Yoon-Hwa Choi, Chul Kim, Edward Jung	Configuring Multiple Boundary Scan Chains for Board Testing.	ISCAS	1995	DBLP DOI BibTeX RDF
16	Douglas Reed, Jason Doege, Antonio Rubio 0001	Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ.	ITC	1995	DBLP DOI BibTeX RDF
16	Gary O'Donnell	It's DFT, Boundary Scan and Life Cycle Benefits.	ITC	1995	DBLP DOI BibTeX RDF
16	Lee Whetsel	Improved Boundary Scan Design.	ITC	1995	DBLP DOI BibTeX RDF
16	Theodoros Antonakopoulos 0001, Nick Kanopoulos	Multiple boundary scan-paths for minimizing circuit-board test-application time.	Microprocess. Microprogramming	1994	DBLP DOI BibTeX RDF
16	Chauchin Su	Random Testing of Interconnects in A Boundary Scan Environment.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF