|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 406 occurrences of 170 keywords
|
|
|
Results
Found 306 publication records. Showing 306 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | Subhrajit Bhattacharya, Sujit Dey |
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 74-80, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology |
21 | Oliver F. Haberl, Thomas Kropf |
HIST: A hierarchical self test methodology for chips, boards, and systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 85-106, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Boundary-scan architecture, hierarchical self test, self test synthesis, built-in self test (BIST), system test |
21 | Jacob Savir |
Module level weighted random patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 274-278, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register |
21 | Jacob Savir |
Generator choices for delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 214-221, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test |
21 | Hao Zheng, Kewal K. Saluja, Rajiv Jain |
Test application time reduction for scan based sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 188-191, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time |
21 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
21 | Ajay Khoche, Erik Brunvand |
A partial scan methodology for testing self-timed circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 283-289, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits |
21 | Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel |
Cyclic stress tests for full scan circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 89-94, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits |
21 | Bapiraju Vinnakota, Nicholas J. Stessman |
Reducing test application time in scan design schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 367-373, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques |
21 | Udo Mahlstedt, Jürgen Alt, Matthias Heinitz |
CURRENT: a test generation system for IDDQ testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 317-323, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults |
21 | O. A. Petlin, Stephen B. Furber |
Scan testing of micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines |
21 | Sridhar Narayanan, Melvin A. Breuer |
Asynchronous multiple scan chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 270-276, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time |
21 | Kwang-Ting Cheng |
Partial scan designs without using a separate scan clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 277-282, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock |
21 | Bulent I. Dervisoglu |
Features of a Scan and Clock Resource chip for providing access to board-level test functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(1), pp. 107-115, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
diagnostics bus, design-for-testability, scan, boundary scan, pseudorandom testing |
19 | Saman Adham, Sanjay Gupta |
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 205-212, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Shih-Yu Yang, Christos A. Papachristou |
A method for detecting interconnect DSM defects in systems on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1), pp. 197-204, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil G. Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts |
Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1184-1191, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Saghir A. Shaikh |
IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 543-550, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung |
Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 711-718, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Andrzej Rucinski 0002, Barrett Stetson, S. T. P. Brundavani |
A DOT1 & DOT4 MOSIS - Compatible Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 83-84, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Farzin Karimi, Fabrizio Lombardi |
A Scan-Bist Environment for Testing Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 17-, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Farzin Karimi, Fabrizio Lombardi |
A Scan-Bist Environment for Testing Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 211-, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Sungbae Hwang, Jacob A. Abraham |
Selective-run built-in self-test using an embedded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 124-129, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
processor-based testing, built-in self-test, design for testability, SOC testing, pseudo-random number generator |
18 | Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi |
Data Compression for System-on-Chip Testing Using ATE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 166-176, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Subhasish Mitra, Edward J. McCluskey, Samy Makar |
Design for Testability and Testing of IEEE 1149.1 Tap Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 247-252, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Chun-Keung Lo, Philip C. H. Chan |
An Efficient Structural Approach to Board Interconnect Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 307-310, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Vladimír Székely, Cs. Márta, Zsolt Kohári, Márta Rencz |
CMOS sensors for on-line thermal monitoring of VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(3), pp. 270-276, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Al Bailey, Tim Lada, Jim Preston |
Collateral ASIC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 14(1), pp. 55-63, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau |
Lessons Learned from Practical Applications of BIST/B-S Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 251-257, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Zhiwei Li, Zhongliang Pan |
Research of the Automatic Testing Software on Boundary-scan Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMLC ![In: Proceedings of the 15th International Conference on Machine Learning and Computing, ICMLC 2023, Zhuhai, China, February 17-20, 2023, pp. 464-468, 2023, ACM, 978-1-4503-9841-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Libao Deng, Ning Sun, Ning Fu |
Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 72, pp. 171-182, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Asma Ben Ahmed, Olfa Mosbahi, Mohamed Khalgui, Zhiwu Li 0001 |
Boundary Scan Extension for Testing Distributed Reconfigurable Hardware Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7), pp. 2699-2708, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Toshiaki Satoh, Hiroyuki Yotsuyanagi, Masaki Hashizume |
On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan, October 8-10, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-4870-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Shuya Kikuchi, Hiroyuki Yotsuyanagi, Masaki Hashizume |
On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019, pp. 169-174, 2019, IEEE, 978-1-7281-4718-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume |
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018, pp. 7-12, 2018, IEEE, 978-1-5386-9466-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Pok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong |
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017, pp. 5-10, 2017, IEEE Computer Society, 978-1-5386-2437-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Farnaz Fotovatikhah, Bahareh Naraghi, Fatemeh Tavakoli, Mahdiar Ghadiry |
A New Approach to Model the Effect of Topology on Testing Using Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 31(3), pp. 301-310, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | André V. Fidalgo, Andre Couto, Manuel C. Felgueiras, Gustavo R. Alves |
Low cost boundary scan controller for didactic applications (IEEE 1149.1). ![Search on Bibsonomy](Pics/bibsonomy.png) |
exp.at ![In: 2015 3rd Experiment International Conference (exp.at'15), Ponta Delgada, Portugal, June 2-4, 2015, pp. 203-208, 2015, IEEE, 978-1-4673-7717-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Terry Borroz |
Considerations in the design of a boundary scan runtime library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Instrum. Meas. Mag. ![In: IEEE Instrum. Meas. Mag. 17(4), pp. 27-30, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya, Masaki Hashizume |
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 96-D(9), pp. 1986-1993, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Louis Y. Ungar |
Boundary scan as a system-level diagnostic tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Instrum. Meas. Mag. ![In: IEEE Instrum. Meas. Mag. 16(4), pp. 8-15, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Geng-Ming Chiu, James Chien-Mo Li |
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(1), pp. 126-134, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Bill Eklow |
Managing Complex Boundary-Scan Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 29(2), pp. 100-102, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Stephen K. Sunter, Aubin Roy |
Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 29(5), pp. 55-62, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | João Carlos Cunha, Ricardo Barbosa 0003, Gilberto Rodrigues |
On the Use of Boundary Scan for Code Coverage of Critical Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 23rd IEEE International Symposium on Software Reliability Engineering, ISSRE 2012, Dallas, TX, USA, November 27-30, 2012, pp. 341-350, 2012, IEEE Computer Society, 978-1-4673-4638-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Chun-Ming Huang, Chih-Chyau Yang, Chien-Ming Wu, Chih-Hsing Lin, Chun-Chieh Chiu, Yi-Jun Liu, Chun-Chieh Chu, Chun-Ping Lin, Wei-De Chien |
Boundary scan test solution for MorPACK platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2012, Tamsui, New Taipei City, Taiwan, November 4-7, 2012, pp. 802-805, 2012, IEEE, 978-1-4673-5083-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume |
A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, pp. 539-544, 2011, IEEE Computer Society, 978-1-4577-1984-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Stephen K. Sunter, Aubin Roy |
Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011, pp. 1-9, 2011, IEEE Computer Society, 978-1-4577-0153-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Bashar Al-Khalifa |
A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. Arab J. Inf. Technol. ![In: Int. Arab J. Inf. Technol. 7(2), pp. 124-128, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
16 | Shengjian Chen, Lei Xu |
A boundary-scan test bus controller design for mixed-signal test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCNIS ![In: Proceedings of the IEEE International Conference on Wireless Communications, Networking and Information Security, WCNIS 2010, 25-27 June 2010, Beijing, China, pp. 22-25, 2010, IEEE, 978-1-4244-5850-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Stephen K. Sunter, Matthias Tilmann |
BIST of I/O circuit parameters via standard boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 74-83, 2010, IEEE Computer Society, 978-1-4244-7206-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón |
A New Algorithm for the Selection of Control Cells in Boundary-Scan Interconnect Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 25(2-3), pp. 187-195, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Marcos Barcellos Hervé, Érika F. Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski |
NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 10th Latin American Test Workshop, LATW 2009, Rio de Janeiro, Brazil, March 2-5, 2009, pp. 1-6, 2009, IEEE, 978-1-4244-4206-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Adam W. Ley |
Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009, pp. 1-10, 2009, IEEE Computer Society, 978-1-4244-4868-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Chwee Liong Tee, Tzyy Haw Tan, Chin Chuan Ng |
Augmenting board test coverage with new intel powered opens boundary scan instruction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009, pp. 1-10, 2009, IEEE Computer Society, 978-1-4244-4868-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Steve Sunter, Kenneth P. Parker |
Testing bridges to nowhere - combining Boundary Scan and capacitive sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009, pp. 1-10, 2009, IEEE Computer Society, 978-1-4244-4868-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Philip B. Geiger, Steve Butkovich |
Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009, pp. 1-10, 2009, IEEE Computer Society, 978-1-4244-4868-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Dave F. Dubberke, James J. Grealish, Bill Van Dick |
Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, pp. 1-9, 2008, IEEE Computer Society, 978-1-4244-2403-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Dayton Norrgard, Kenneth P. Parker |
Augmenting Boundary-Scan Tests for Enhanced Defect Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, pp. 1-8, 2008, IEEE Computer Society, 978-1-4244-2403-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Kenneth P. Parker, Neil G. Jacobson |
Boundary-Scan Testing of Power/Ground Pins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, pp. 1-8, 2008, IEEE Computer Society, 978-1-4244-2403-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker |
Problems Using Boundary-Scan for Memory Cluster Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, pp. 1-10, 2008, IEEE Computer Society, 978-1-4244-2403-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren |
A practical approach to comprehensive system test & debug using boundary scan based test architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007, pp. 1-10, 2007, IEEE Computer Society, 1-4244-1128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Ing. M. F. Breeuwsma |
Forensic imaging of embedded systems using JTAG (boundary-scan). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Digit. Investig. ![In: Digit. Investig. 3(1), pp. 32-42, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Brian Foutz, Vivek Chickermane, Bing Li, Harry Linzer, Gary Kunselman |
Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 381-388, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Bambang Suparjo, Adam W. Ley, Adam Cron, Heiko Ehrenberg |
Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-9, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Heiko Ehrenberg |
IEEE P1581 - Getting More Board Test Out of Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-10, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Ilka Reis, Peter Collins, Marc van Houcke |
On-line Boundary-Scan Testing in Service of Extended Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006, pp. 1-10, 2006, IEEE Computer Society, 1-4244-0292-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Yu-Cheng Fan, Hen-Wai Tsao |
Boundary Scan Test Scheme for IP Core Identification via Watermarking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 88-D(7), pp. 1397-1400, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | David Bäckström, Gunnar Carlsson, Erik Larsson |
Remote boundary-scan system test control for the ATCA standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 10, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Peter Collins, Ilka Reis, Mikko Simonen, Marc van Houcke |
A transparent solution for providing remote wired or wireless communication to board and system level boundary-scan architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 8, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Peter J. Ashenden |
Boundary Scan Test Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(1), pp. 91-92, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
16 | Hamimi Chemali, Abdelhakim Latoui, Chouki Aktouf |
An Optical Boundary Scan Cell for On Line Testing of Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Systems and Applications ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '03, June 23 - 26, 2003, Las Vegas, Nevada, USA, pp. 155-160, 2003, CSREA Press. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
16 | Uros Kac, R. Sedevcic, Franc Novak, Anton Biasizzo |
Linux-based experimental boundary scan environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 26(5), pp. 199-206, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | William Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo |
Unsafe board states during PC-based boundary-scan testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 615-623, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Alan Albee |
A practical guide to combining ICT & boundary scan testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 487-494, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick |
Frequency detection-based boundary-scan testing of AC coupled nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 46-53, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Shih-Yu Yang, Christos A. Papachristou, Massood Tabib-Azar |
Improving Bus Test Via IDDT and Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 307-312, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001 |
A system level boundary scan controller board for VME applications [to CERN experiments]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000, pp. 153-158, 2000, IEEE Computer Society, 0-7695-0701-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace |
End-to-end testing for boards and systems using boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 585-592, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Stephen Harrison, Peter Collins, Greg Noeninckx |
The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 45-54, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Kenneth P. Parker |
System issues in boundary-scan board test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 724-728, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Michael S. Heutmaker, D. K. Le |
An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Commun. Mag. ![In: IEEE Commun. Mag. 37(6), pp. 98-102, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Jongchul Shin, Hyunjin Kim, Sungho Kang 0001 |
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 473-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Adam W. Ley |
The integration of boundary-scan test methods to a mixed-signal environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999, pp. 159-162, 1999, IEEE Computer Society, 0-7803-5753-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Yasunori Sameshima, Tomoo Fukazawa |
A DFT Methodology for High-Speed MCM Based on Boundary-Scan Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 521-, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Amitava Majumdar 0002, Michio Komoda, Tim Ayres |
Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May 1998, Princeton, NJ, USA, pp. 86-91, 1998, IEEE Computer Society, 0-8186-8436-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | T. A. García, Antonio J. Acosta 0001, José L. Huertas, J. M. Mora, J. Ramos |
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May 1998, Princeton, NJ, USA, pp. 92-97, 1998, IEEE Computer Society, 0-8186-8436-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen |
Boundary scan BIST methodology for reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 774-783, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | William J. Hughes III |
System-Level Boundary-Scan in a Highly Integrated Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997, pp. 636-639, 1997, IEEE Computer Society, 0-7803-4209-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Matthew Boutin, Peter Dziel |
Application of Boundary Scan in a Fault Tolerant Computer System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 809-817, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Keith Lofstrom |
Early Capture for Boundary Scan Timing Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 417-422, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Wuudiann Ke |
Backplane Interconnect Test in a Boundary-Scan Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 717-724, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | D. Eugene Wedge, Tom Conner |
A Roadmap for Boundary-Scan Test Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996, pp. 340-346, 1996, IEEE Computer Society, 0-7803-3541-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee |
A New Architecture for Analog Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 409-412, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Yoon-Hwa Choi, Chul Kim, Edward Jung |
Configuring Multiple Boundary Scan Chains for Board Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 2128-2131, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Douglas Reed, Jason Doege, Antonio Rubio 0001 |
Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995, pp. 577-585, 1995, IEEE Computer Society, 0-7803-2992-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Gary O'Donnell |
It's DFT, Boundary Scan and Life Cycle Benefits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995, pp. 920, 1995, IEEE Computer Society, 0-7803-2992-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Lee Whetsel |
Improved Boundary Scan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995, pp. 851-860, 1995, IEEE Computer Society, 0-7803-2992-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
16 | Theodoros Antonakopoulos 0001, Nick Kanopoulos |
Multiple boundary scan-paths for minimizing circuit-board test-application time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 40(6), pp. 377-386, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Chauchin Su |
Random Testing of Interconnects in A Boundary Scan Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 226-231, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
Displaying result #101 - #200 of 306 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ >>] |
|