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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 772 occurrences of 458 keywords
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Results
Found 2528 publication records. Showing 2528 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Davide Pandini, Cristiano Forzan, Livio Baldi |
Design Methodologies and Architecture Solutions for High-Performance Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 152-159, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin |
Delay and current estimation in a CMOS inverter with an RC load. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 80-89, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Vasily G. Moshnyaga |
Reducing cache engery through dual voltage supply. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 302-305, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Mahadevamurty Nemani, Farid N. Najm |
High-level area and power estimation for VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), pp. 697-713, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Anand Raghunathan, Niraj K. Jha |
SCALP: an iterative-improvement-based low-power data path synthesis system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1260-1277, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson |
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1), pp. 58-67, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Jan J. H. van der Biesen, Toru Toyabe |
Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 855-861, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
30 | Yu Chen, Yuchen Song, Jian Zhang |
A Novel Principal Component Analysis Flow Pattern Identification Algorithm for Electrical Capacitance Tomography System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVHI ![In: 2010 International Conference on Machine Vision and Human-machine Interface, MVHI 2010, Kaifeng, China, April 24-25, 2010, pp. 235-238, 2010, IEEE Computer Soceity, 978-0-7695-4009-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
electrical capacitance tomography, Symmetric subspace, neural network, principal component analysis |
30 | Lei Liu, Yu Chen, Yuchen Song |
A Novel Barzilai-Borwein Image Reconstruction Algorithm for Electrical Capacitance Tomography System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVHI ![In: 2010 International Conference on Machine Vision and Human-machine Interface, MVHI 2010, Kaifeng, China, April 24-25, 2010, pp. 385-388, 2010, IEEE Computer Soceity, 978-0-7695-4009-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
electrical capacitance tomography, Barzilai-Borwein, image reconstruction, Steepest Descent |
30 | Yinke Dou, Jianmin Qin, Xiaomin Chang |
The Study of a Capacitance Sensor and its System Used in Measuring Ice Thickness, Sedimentation and Water Level of a Reservoir. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFITA (3) ![In: International Forum on Information Technology and Applications, IFITA 2009, Chengdu, China, 15-17 May 2009, pp. 616-619, 2009, IEEE Computer Society, 978-0-7695-3600-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi-electrode Capacitance, Ice thickness, water level, CPLD, Sedimentation |
30 | Xuemei Hu, Linhong Tian |
Research and Analysis of Bias Voltage on Variable-Capacitance Micro-mechanical Accelerometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), Harbin, China, 15-17 August 2008, Proceedings, pp. 1490-1493, 2008, IEEE Computer Society, 978-0-7695-3278-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Variable-Capacitance Accelerometer, Reliable operation condition, Bias voltage polarity |
28 | Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak |
Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 253-258, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel |
A capacitance solver for incremental variation-aware extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 662-669, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Carlos Fernando Teodósio Soares, Antonio Petraglia |
Capacitance ratio approximation in SC filters via genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 516-519, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Tadashi Suetsugu, Marian K. Kazimierczuk |
ZVS operating frequency versus duty ratio of class E amplifier with nonlinear shunt capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3258-3261, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Sushmit Goswami, Tino Copani, Bert Vermeire, Hugh Bamaby |
BW extension in shunt feedback transimpedance amplifiers using negative miller capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 61-64, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Jintao Xue, Dian Zhou |
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1514-1519, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Shilpa Bhoj, Dinesh Bhatia |
Pre-route Interconnect Capacitance and Power Estimation in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 159-164, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li 0004, Zhihua Wang 0001, Patrick Chiang 0001 |
Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2562-2565, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Ning Lu, Judy H. McCullen |
Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 743-748, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Aditya Bansal, Bipul Chandra Paul, Kaushik Roy 0001 |
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2765-2774, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | James D. Ma, Rob A. Rutenbar |
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4), pp. 710-724, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Shu Yan, Vivek Sarin, Weiping Shi |
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2282-2286, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Elias Kougianos, Saraju P. Mohanty |
Effective tunneling capacitance: a new metric to quantify transient gate leakage current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman |
On-die decoupling capacitance: frequency domain analysis of activity radius. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Usha Narasimha, Binu Abraham, N. S. Nagaraj |
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 795-800, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Deyun Chen, Mouzun Li |
Parameters Optimization and Simulation of Transducer Based on Finite Element Method in Electrical Capacitance Tomography System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMSCCS (2) ![In: Interdisciplinary and Multidisciplinary Research in Computer Science, IEEE CS Proceeding of the First International Multi-Symposium of Computer and Computational Sciences (IMSCCS|06), June 20-24, 2006, Zhejiang University, Hangzhou, China, Vol. 2, pp. 212-216, 2006, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Dian Zhou |
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1095-1098, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Shu Yan, Vivek Sarin, Weiping Shi |
Sparse transformations and preconditioners for 3-D capacitance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1420-1426, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Nang-Ching Yeung, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-Fat Chan |
Active RC filter with reduced capacitance by current division technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3279-3282, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda |
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 153-158, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Shabbir H. Batterywala, Madhav P. Desai |
Variance Reduction in Monte Carlo Capacitance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 85-90, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Zhenhai Zhu, Jacob K. White 0001, Alper Demir 0001 |
A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 887-891, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Shoji Suzuki, Yoshinori Adachi |
Development of High-Precise and No-Contacting Capacitance Measuring System Using Dipmeter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Knowledge-Based Intelligent Information and Engineering Systems, 8th International Conference, KES 2004, Wellington, New Zealand, September 20-25, 2004. Proceedings. Part II, pp. 89-94, 2004, Springer, 3-540-23206-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Jürgen Leeb, Johannes Knorr, Horst Zimmermann |
Sensitivity-enhanced OEIC with capacitance multiplier for reduced lower-cutoff frequency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 829-832, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Ye Liu, Mei Xue, Zheng-Fan Li, Rui-Feng Xue |
Efficient Capacitance Extraction for Periodic Structures by Shanks Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 271-275, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Jozef Adut, José Silva-Martínez |
A high-Q, switched-capacitor filter with reduced capacitance spread using a randomized nonuniform sampling technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 449-452, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Li Ding 0002, Pinaki Mazumder, David T. Blaauw |
Crosstalk noise estimation using effective coupling capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 645-648, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh |
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 489-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Woojin Jin, Yungseon Eo, William R. Eisenstadt, Jongin Shim |
Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(3), pp. 450-460, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Wenjian Yu, Zeyi Wang |
An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 366-372, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Chung Kei Thomas Chan, Christofer Toumazou |
Design of a class E power amplifier with non-linear transistor output capacitance and finite DC-feed inductance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 129-132, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Asim Husain |
Models For Interconnect Capacitance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 167-172, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Yanhong Yuan, Prithviraj Banerjee |
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 133-138, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Jinsong Zhao |
Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 536-539, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Sharad Kapur, David E. Long |
Large-scale capacitance calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 744-749, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Youxin Gao, D. F. Wong 0001 |
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 217-220, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Yanhong Yuan, Prithviraj Banerjee |
ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 64-67, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Jaewon Oh, Massoud Pedram |
Gated Clock Routing Minimizing the Switched Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 692-697, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
gated clock routing, low power |
28 | Weiping Shi, Jianguo Liu 0001, Naveen Kakani, Tiejun Yu |
A Fast Hierarchical Algorithm for 3-D Capacitance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 212-217, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
28 | E. Aykut Dengi, Ronald A. Rohrer |
Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 218-223, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
28 | Chung-Ping Chen, D. F. Wong 0001 |
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 604-607, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Denis Martin, Nicholas C. Rumin |
Delay prediction from resistance-capacitance models of general MOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 997-1003, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Hong June Park, Ping Keung Ko, Chenming Hu |
A charge sheet capacitance model of short channel MOSFETs for SPICE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3), pp. 376-389, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
28 | Sanae Fukuda, Naoyuki Shigyo, Koichi Kato, Shin Nakamura |
A ULSI 2-D capacitance simulator for complex structures based on actual processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1), pp. 39-47, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
28 | Erich Barke |
Line-to-ground capacitance calculation for VLSI: a comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(2), pp. 295-298, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
26 | Data Ram Bhaskar, Meghana Shrivastava, Ajishek Raj, Pragati Kumar |
Floating parallel lossy inductance, parallel lossy capacitance, parallel C-D, and lossless capacitance multiplier circuits using current feedback operational amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 52(3), pp. 1489-1517, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Dingcheng Yang, Haoyuan Li, Wenjian Yu, Yuanbo Guo, Wenjie Liang |
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 28(4), pp. 56:1-56:22, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Siheon Seong, Sewon Lee, Sunghyun Bae, Minjae Lee |
Self Capacitance Mismatch Calibration Technique for Fully-Differential Touch Screen Panel Self Capacitance Sensing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 23(7), pp. 3779, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Hyeyeon Lee, Changuk Lee, Inhee Lee, Youngcheol Chae |
A 0.033-mm2 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(10), pp. 3048-3057, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Raoul Joly, Stephanie Girod, Noureddine Adjeroud, Patrick Grysan, Jerome Polesel-Maris |
Evidence of Negative Capacitance and Capacitance Modulation by Light and Mechanical Stimuli in Pt/ZnO/Pt Schottky Junctions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 21(6), pp. 2253, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Hyeyeon Lee, Changuk Lee, Jae-Youl Lee, Yoon-Kyung Choi, Youngcheol Chae |
A 0.033-mm2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity up to 480pF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021, pp. 1-3, 2021, IEEE, 978-1-6654-4350-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Ngoc Thanh Mai Tran, Vincenzo D'Elia, Luca Callegaro, Massimo Ortolano |
A Capacitance Build-Up Method to Determine LCR Meter Errors and Capacitance Transfer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 69(8), pp. 5727-5735, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Tianyu Yu, Weifeng Lü, Zhifeng Zhao, Peng Si, Kai Zhang |
Effect of different capacitance matching on negative capacitance FDSOI transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 98, pp. 104730, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Asif Islam Khan |
Ferroelectrics, Negative Capacitance and Depolarization Field: What exactly is negative capacitance? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2019, Ann Arbor, MI, USA, June 23-26, 2019, pp. 57-58, 2019, IEEE, 978-1-7281-2111-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Haoming Xin, Martin Andraud, Peter G. M. Baltus, Eugenio Cantatore, Pieter Harpe |
A 0.1nW -1µW All-Dynamic Capacitance-to-Digital Converter with Power/Speed/Capacitance Scalability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018, pp. 18-21, 2018, IEEE, 978-1-5386-5404-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Ali Saeidi, Farzan Jazaeri, Francesco Bellando, Igor Stolichnov, Christian C. Enz, Adrian M. Ionescu |
Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017, pp. 78-81, 2017, IEEE, 978-1-5090-5978-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
26 | Dongdi Zhu, Jiongjiong Mo, Shiyi Xu, Yong-Heng Shang, Zhiyu Wang, Zheng-Liang Huang, Fa-Xin Yu |
A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 32(3), pp. 393-397, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Shunji Nakata, Hiroshi Makino, Yoshio Matsuda |
A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014, College Station, TX, USA, August 3-6, 2014, pp. 439-442, 2014, IEEE, 978-1-4799-4134-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
26 | Susumu Kobayashi, Naoshi Doi |
An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 92-C(4), pp. 492-499, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Wuqiang Yang, A. L. Stott, J. C. Gamio |
Analysis of the effect of stray capacitance on an ac-based capacitance tomography transducer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 52(5), pp. 1674-1681, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Deyun Chen, Guibin Zheng, Xiaoyang Yu, Yukun Wang, Tong Zhou |
Analysis of capacitance sensitivity distributions and image reconstruction in electrical capacitance tomography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Color Imaging: Device-Independent Color, Color Hardcopy, and Applications ![In: Color Imaging: Device-Independent Color, Color Hardcopy, and Applications VII, San Jose, CA, USA, January 19, 2002, pp. 355-359, 2002, SPIE, 978-0-8194-4403-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Dennis Sylvester, James C. Chen, Chenming Hu |
Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 33(3), pp. 449-453, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Samed Maltabas, Martin Margala, Ugur Çilingiroglu |
Varicap threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 239-244, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
minnick tl network, variable capacitance, threshold logic, parallel counter |
24 | Chao Wang 0019, Ming Zhang, Xiangyu Wang, Dongyue Wu, Huaxiang Wang |
Primary Study on Dielectric Property Detection for Cerebral Haematoma. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMEI (2) ![In: Proceedings of the 2008 International Conference on BioMedical Engineering and Informatics, BMEI 2008, May 28-30, 2008, Sanya, Hainan, China - Volume 2, pp. 482-486, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Haematoma of brain, the permittivity of the organism, bioelectrical capacitance measuring technology |
24 | Peter Feldmann, Soroush Abbaspour |
Towards a more physical approach to gate modeling for timing, noise, and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 453-455, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
current source model, effective capacitance |
24 | Agnes Sarolta Nagy, Alicia Polanco, Manuel Alvarez |
Contributions to improve design accuracy of bipolar ics via physical effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 245-250, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
base-emitter capacitance model, emission coefficient, physical effects |
24 | Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede |
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 354-365, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual rail with precharge, wave dynamic differential logic (WDDL), differential routing, parasitic capacitance matching, side-channel attack (SCA), differential power analysis (DPA), countermeasure |
24 | Doug L. James, Dinesh K. Pai |
Multiresolution green's function methods for interactive simulation of large-scale elastostatic objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Graph. ![In: ACM Trans. Graph. 22(1), pp. 47-82, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Capacitance matrix, elastostatic, fast summation, interactive real-time applications, real-time, wavelets, deformation, force feedback, updating, lifting scheme, Green's function |
24 | Yu Chen 0005, Puneet Gupta 0001, Andrew B. Kahng |
Performance-impact limited area fill synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 22-27, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VLSI manufacturability, coupling capacitance extraction, dummy fill problem, signal delay, linear programming, greedy method |
24 | Tae-young Oh, Zhiping Yu, Robert W. Dutton |
AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 326-330, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
AC analysis, thin gate oxide, quantum mechanical correction, threshold voltage shift, transconductace, channel length reduction, density-gradient, quantum confinement, PROPHET, channel doping, transport theory, device parameter extraction, effective oxide thickness, capacitance |
24 | Nathan Kalyanasundharam, Nital Patwa |
Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 118-123, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance |
24 | Peter James Aldworth |
System-on-a-Chip Bus Architecture for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 297-298, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
architecture, interconnect, latency, infrastructure, system-on-a-chip, bus, capacitance, peripherals |
24 | Darko Kirovski, Johnson Kin, William H. Mangione-Smith |
Procedure Based Program Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 204-213, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cached procedures, compressed memory, consumer devices, design factors, directory structure, high-capacitance bus traffic, integrated data services, memory references, pagers, procedural reference resolution, procedure-based program compression, run-time performance overhead, smart telephones, transparent program compression, embedded systems, personal digital assistants, power consumption, cost, multimedia applications, source coding, RAM, performance requirements, battery life, communications applications, memory reduction |
24 | N. P. van der Meijs, T. Smedes |
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 244-251, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling |
23 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 15-20, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
23 | Kunal P. Ganeshpure, Sandip Kundu |
An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 233-238, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang |
A noniterative equivalent waveform model for timing analysis in presence of crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 25:1-25:21, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
equivalent waveform, delay, noise, timing analysis, Deep sub micron |
23 | Changhui Liu, Chunmei Xu, Le Liu, Huahui He |
Measure the Thickness of the Thin-Film Single-Slice-Capacitor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIP ![In: International Symposium on Information Processing, ISIP 2008 / International Pacific Workshop on Web Mining, and Web-Based Application, WMWA 2008, Moscow, Russia, 23-25 May 2008, pp. 770-773, 2008, IEEE Computer Society, 978-0-7695-3151-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Zheng Chen, Dawn R. Hedgepeth, Xiaobo Tan |
A nonlinear, control-oriented model for ionic polymer-metal composite actuators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: Proceedings of the 47th IEEE Conference on Decision and Control, CDC 2008, December 9-11, 2008, Cancún, Mexico, pp. 1851-1856, 2008, IEEE, 978-1-4244-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Yiling Zhang, Valencia M. Joyner, Ruida Yun, Sameer R. Sonkusale |
A 700Mbit/s CMOS capacitive feedback front-end amplifier with automatic gain control for broadband optical wireless links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 185-188, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Timothy G. Constandinou, Julius Georgiou, Chris Toumazou |
A micropower front-end interface for differential-capacitive sensor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2474-2477, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Kunal P. Ganeshpure, Sandip Kundu |
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 540-545, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang 0001 |
Coupling-aware Dummy Metal Insertion for Lithography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 13-18, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
coupling-aware dummy metal insertion, integrated circuits manufacturing technology, resolution enhancement techniques, off-axis illumination, forbidden pitches, printability improvement, invisible dummy metal segments, lithography cost minimization, optimal algorithm, chemical mechanical polish |
23 | Rupesh S. Shelar |
An efficent clustering algorithm for low power clock tree synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 181-188, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
clustering, low power, clock tree synthesis |
23 | Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap |
Fast Interconnect and Gate Timing Analysis for Performance Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(12), pp. 1383-1388, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella |
Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2006, 13th International Conference, Bangalore, India, December 18-21, 2006, Proceedings, pp. 123-134, 2006, Springer, 3-540-68039-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Di Wu 0017, Jiang Hu, Rabi N. Mahapatra |
Coupling aware timing optimization and antenna avoidance in layer assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 20-27, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, probabilistic modeling, physical design, crosstalk, design for manufacturability (DFM), antenna effect |
23 | Liang Deng, Martin D. F. Wong |
Energy optimization in memory address bus structure for application-specific systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 232-237, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Rafael Escovar, Roberto Suaya |
Optimal design of clock trees for multigigahertz applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3), pp. 329-345, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
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