Search results for "clocking"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Naveed Zaman, Antony Spilman	Triggering and clocking architecture for mixed signal test.	ITC	1998	DBLP DOI BibTeX RDF
28	Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III	Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
28	Michel R. Dagenais, Nicholas C. Rumin	On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
21	Faizal Karim, Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Konrad Walus, André Ivanov, Fabrizio Lombardi	Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	Quantum-dot cellular automata (QCA), Clocked QCA, Emerging nanotechnologies, Phase shift
21	Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy 0001	A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
21	Jungseob Lee, Nam Sung Kim	Optimizing total power of many-core processors considering voltage scaling limit and process variations.	ISLPED	2009	DBLP DOI BibTeX RDF	voltage and frequency scaling, process variations, parallel applications, many-core processor
21	Feng Qian 0001, Alexandre Gerber, Zhuoqing Morley Mao, Subhabrata Sen, Oliver Spatscheck, Walter Willinger	TCP revisited: a fresh look at TCP in the wild.	Internet Measurement Conference	2009	DBLP DOI BibTeX RDF	network measurement, tcp
21	Myungsu Choi, Minsu Choi	Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	QCA (quantum-dot cellular automata), Asynchronous architecture, Layout timing problem, Scalability, Robustness
21	Steve Babbage, Matthew Dodd	The MICKEY Stream Ciphers.	The eSTREAM Finalists	2008	DBLP DOI BibTeX RDF
21	Mayur Bubna, Sudip Roy 0002, Naresh Shenoy, Subhra Mazumdar 0002	A layout-aware physical design method for constructing feasible QCA circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	routing, partitioning, placement, quantum-dot cellular automata
21	Alan Kennedy, Xiaojun Wang 0001, Zhen Liu 0018, Bin Liu 0001	Low power architecture for high speed packet classification.	ANCS	2008	DBLP DOI BibTeX RDF	energy efficient, hardware accelerator, packet classification, frequency scaling
21	Mohammad Azim Karami, Ali Afzali-Kusha, Reza Faraji-Dana, Masoud Rostami	Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks.	ISVLSI	2007	DBLP DOI BibTeX RDF
21	Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø	A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method.	DATE	2007	DBLP DOI BibTeX RDF
21	Lei Cheng 0001, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig	Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.	ICCAD	2007	DBLP DOI BibTeX RDF
21	Eric L. Hill, Mikko H. Lipasti	Transparent mode flip-flops for collapsible pipelines.	ICCD	2007	DBLP DOI BibTeX RDF
21	Vishwanadh Tirumalashetty, Hamid Mahmoodi	Clock Gating and Negative Edge Triggering for Energy Recovery Clock.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Sanghoan Chang, Gwan Choi	Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Ruiming Chen, Hai Zhou 0001	Statistical timing verification for transparently latched circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Eric L. Hill, Mikko H. Lipasti	Stall cycle redistribution in a transparent fetch pipeline.	ISLPED	2006	DBLP DOI BibTeX RDF	pipeline gating, microarchitecture, dynamic power, instruction fetch
21	Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel	A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.	ISLPED	2006	DBLP DOI BibTeX RDF	pulse latch, low-power, latch
21	Pyung-Su Han, Woo-Young Choi	1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18µm CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park	Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design.	DFT	2006	DBLP DOI BibTeX RDF
21	Liam Noonan, Colin Flanagan	An effective network processor design framework: using multi-objective evolutionary algorithms and object oriented techniques to optimise the intel IXP1200 network processor.	ANCS	2006	DBLP DOI BibTeX RDF	object oriented, design space exploration, evolutionary approaches
21	Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001	Synthesis of skewed logic circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Skewed logic, optimization, synthesis, power
21	Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich Theodor Vierhaus, Pawel Wlaz	Synchronization Fault Cryptanalysis for Breaking A5/1.	WEA	2005	DBLP DOI BibTeX RDF
21	Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy 0001	Energy recovery clocked dynamic logic.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	logic, clock, domino, energy recovery
21	Bill Pontikakis, François R. Boyer, Yvon Savaria	Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.	IWSOC	2005	DBLP DOI BibTeX RDF
21	Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou	Experimental Evaluation of Resonant Clock Distribution.	ISVLSI	2004	DBLP DOI BibTeX RDF
21	Ruiming Chen, Hai Zhou 0001	Clock schedule verification under process variations.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	An ILP-based scheduling scheme for energy efficient high performance datapath synthesis.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
21	Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang 0008	Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.	ITC	2003	DBLP DOI BibTeX RDF
21	Saraju P. Mohanty, N. Ranganathan	Energy Efficient Scheduling for Datapath Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
21	Yongjian Brandon Guo, K. Wayne Current	Voltage Comparator Circuits for Multiple-Valued CMOS Logic.	ISMVL	2002	DBLP DOI BibTeX RDF	voltage comparator, MVL, low-power, CMOS
21	Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001	Synthesis of Selectively Clocked Skewed Logic Circuits.	ISQED	2002	DBLP DOI BibTeX RDF
21	Stefan Lund, Lars Bengtsson	Synchronizing a High-Speed SIMD Processor Array.	DSD	2001	DBLP DOI BibTeX RDF
21	Mohit Aron, Peter Druschel	Soft timers: efficient microsecond software timer support for network processing.	ACM Trans. Comput. Syst.	2000	DBLP DOI BibTeX RDF	polling, timers, transmission scheduling
21	Mauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria	A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications.	ICCD	1999	DBLP DOI BibTeX RDF
21	Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses	Some experiments about wave pipelining on FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
21	Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller	Advances of the Counterflow Pipeline Microarchitecture.	HPCA	1997	DBLP DOI BibTeX RDF	counterflow, CFPP, virtual register, architecture, pipeline, dataflow, VRP
21	Glenn Jennings, Esther Jennings	A discrete syntax for level-sensitive latched circuits having n clocks and m phases.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
21	William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Valid clock frequencies and their computation in wavepipelined circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
19	Sassan Tabatabaei, Aaron Partridge	Silicon MEMS Oscillators for High-Speed Digital Systems.	IEEE Micro	2010	DBLP DOI BibTeX RDF	silicon oscillator, microelectromechanical systems, MEMS resonator, MEMS packaging, serial interfaces, hardware, clock, oscillator, digital clocking
19	Vinayak Honkote, Baris Taskin	Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array.	VLSI Design	2010	DBLP DOI BibTeX RDF	Resonant clocking, Capacitive load balancing, Optimization, Low power, Spice
19	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
19	Martin Saint-Laurent, Baker Mohammad, Paul Bassett	A 65-nm pulsed latch with a single clocked transistor.	ISLPED	2007	DBLP DOI BibTeX RDF	low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
19	Jovan Dj. Golic, Renato Menicocci	Correlation Analysis of the Alternating Step Generator.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	stop/go clocking, stream ciphers, fast correlation attacks, time-varying channels
19	Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong	Design of a 10GHz clock distribution network using coupled standing-wave oscillators.	DAC	2003	DBLP DOI BibTeX RDF	distributed oscillators, on-chip phase measurement, resonant clocking, salphasic, standing wave, clock distribution, coupled oscillators
19	James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	ISLPED	2001	DBLP DOI BibTeX RDF	dual edge, low power, flip-flops, clocking, triggered, latches
19	Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou	Optimizing two-phase, level-clocked circuitry.	J. ACM	1997	DBLP DOI BibTeX RDF	clock tuning, level-clocked circuitry, multiphase clocking, timing analysis and optimization, VLSI, retiming
19	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
19	Gianfranco Ciardo, Christoph Lindemann	Comments on "Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	self-stabilizing clock synchronization, deterministic and stochastic Petri net, fault-tolerant clock synchronisation systems, clocking modules, software package DSPNexpress, performance evaluation, Petri nets, fault tolerant computing, synchronisation, stochastic processes, stochastic Petri nets, steady-state analysis
18	Sastry Garimella, Sasank Garikapati, Aravind Nagulu, Harish Krishnaswamy	Passive Frequency Shifting of N-Path Filters Through Rotary Clocking: Analysis and Design.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
18	Robert S. Aviles, Xi Li, Lei Lu, Zhaorui Ni, Peter A. Beerel	An Efficient and Scalable Clocking Assignment Algorithm for Multi-Threaded Multi-Phase Single Flux Quantum Circuits.	CoRR	2024	DBLP DOI BibTeX RDF
18	Rassul Bairamkulov, Giovanni De Micheli	Towards Multiphase Clocking in Single-Flux Quantum Systems.	CoRR	2024	DBLP DOI BibTeX RDF
18	Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim, Hyunsu Park, Jihwan Park, Ji-Hyo Kang, Jin-Youp Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sang-Yeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim	13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Ahmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar	A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Zhaowen Wang, Peter R. Kinget	A Very High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data Link Clocking.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Johannes Bund, Matthias Függer, Moti Medina	PALS: Distributed Gradient Clocking on Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
18	Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam	Design Automation of Series Resonance Clocking in 14-nm FinFETs.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
18	Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula	A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
18	Johannes Bund, Matthias Függer, Moti Medina	PALS: Distributed Gradient Clocking on Chip.	CoRR	2023	DBLP DOI BibTeX RDF
18	Michael A Campbell, Ben Hughes, James Blanchard, Jonathan Heaps	Frequency Scanning Interferometry and K-space Clocking with Dispersion Compensating Fibre.	I2MTC	2023	DBLP DOI BibTeX RDF
18	Pedro Arthur R. L. Silva, Jeferson F. Chaves, José Augusto Miranda Nacif, Ricardo S. Ferreira 0001, Omar Paranaiba Vilela Neto	Exploring Nanomagnetic Logic with Bennett Clocking.	SBCCI	2023	DBLP DOI BibTeX RDF
18	Rongliang Fu, Olivia Chen, Bei Yu 0001, Nobuyuki Yoshikawa, Tsung-Yi Ho	DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits.	ICCAD	2023	DBLP DOI BibTeX RDF
18	Krzysztof Kasinski, Dariusz Ziolkowski, Pawel Banachowicz, Joanna Iwanicka	Successful Selection of the SoC Clocking Architecture.	MIXDES	2023	DBLP DOI BibTeX RDF
18	Jihyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha	A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Chi-Hsiang Huang 0001, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula 0001, Nasser A. Kurd, Visvesh S. Sathe 0001	Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Xiangye Wei, Liming Xiu	A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications.	IEEE Access	2022	DBLP DOI BibTeX RDF
18		CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
18	Yongqiang Zhang 0006, Chunsong Zhu, Xin Cheng 0001, Guangjun Xie	Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Dhrubajyoti Bhowmik, Amit Kumar Pramanik, Jayanta Pal, Pinaki Sen, Ayush Ranjan Singh, Apu Kumar Saha, Bibhash Sen	Regular clocking-based Automated Cell Placement technique in QCA targeting sequential circuit.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
18	Amit Kumar Pramanik, Dhrubajyoti Bhowmik, Jayanta Pal, Pinaki Sen, Apu Kumar Saha, Bibhash Sen	Towards the realization of regular clocking-based QCA circuits using genetic algorithm.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
18	Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa	Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme.	Comput. Electr. Eng.	2022	DBLP DOI BibTeX RDF
18	Feifei Deng, Guangjun Xie, Yongqiang Zhang 0006, Song Chen	Module-based design method using clocking scheme for quantum-dot cellular automata.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
18	Feifei Deng, Guangjun Xie, Xin Cheng 0001, Yongqiang Zhang 0006	A general and efficient clocking scheme for majority logic in quantum-dot cellular automata.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
18	Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa	Adiabatic Quantum-Flux-Parametron with Delay-Line Clocking Using Square Excitation Currents.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
18	Denis Szymon Piechaczek, Olaf Schrey, Manuel Ligges, Bedrich J. Hosticka, Rainer Kokozinski	Anti-Blooming Clocking for Time-Delay Integration CCDs.	Sensors	2022	DBLP DOI BibTeX RDF
18	Xi Li, Min Pan, Tong Liu, Peter A. Beerel	Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic.	ISVLSI	2022	DBLP DOI BibTeX RDF
18	Amit Kumar Pramanik, Jayanta Pal, Bibhash Sen	Impact of Genetic Algorithm on Low Power QCA Logic Circuit with Regular Clocking.	ASCAT	2022	DBLP DOI BibTeX RDF
18	Jonah Van Assche, Georges G. E. Gielen	A 10.4-ENOB 0.92-5.38 μW Event-Driven Level-Crossing ADC with Adaptive Clocking for Time-Sparse Edge Applications.	ESSCIRC	2022	DBLP DOI BibTeX RDF
18	Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos	A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
18	Steven Hsu, Amit Agarwal 0001, Mark A. Anders 0001, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy 0001, James W. Tschanz, Vivek De	2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
18	Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An, Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin	Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application.	ISSCC	2022	DBLP DOI BibTeX RDF
18	Loai G. Salem, M. Mahmudul Hasan Sajeeb	A Multilevel N-Path Filter Topology for Low-Power Sinusoidal Clocking with Non-Overlapping Phases.	ISCAS	2022	DBLP DOI BibTeX RDF
18	Aniruddha Roy, Preetham N. Reddy, Nitin Agarwal, Nikhil Das	Achieving < 1% Precision Clocking Solution with External-R under Practical Constraints.	APCCAS	2022	DBLP DOI BibTeX RDF
18	Amit Kumar Pramanik, Jayanta Pal, Biplab K. Sikdar, Bibhash Sen	Performance Analysis of Regular Clocking Based Quantum-Dot Cellular Automata Logic Circuit: Fault Tolerant Approach.	ACRI	2022	DBLP DOI BibTeX RDF
18	Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Kulwant Brar, Nhat Nguyen, Shaishav Desai	10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
18	Dhrubajyoti Bhowmik, Jayanta Pal, Mrinal Goswami, Pinaki Sen, Apu Kumar Saha, Bibhash Sen	Systematic cell placement in quantum-dot cellular automata embedding underlying regular clocking circuit.	IET Circuits Devices Syst.	2021	DBLP DOI BibTeX RDF
18	Xin Fan 0002, Milan Babic, Shutao Zhang, Eckhard Grass, Milos Krstic	Plesiochronous Spread Spectrum Clocking With Guaranteed QoS for In-Band Switching Noise Reduction.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
18	Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos 0001, Ewout Martens, Davide Dermit, Jan Craninckx	Asynchronous Event-Driven Clocking and Control in Pipelined ADCs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
18	Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa	Adiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operation.	CoRR	2021	DBLP BibTeX RDF
18	Rasa Smidtaite, Zenonas Navickas, Minvydas Ragulskis	Clocking divergence of iterative maps of matrices.	Commun. Nonlinear Sci. Numer. Simul.	2021	DBLP DOI BibTeX RDF
18	Yan Li 0084, Jun Han 0003, Xiaoyang Zeng, Mehdi B. Tahoori	TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications.	DATE	2021	DBLP DOI BibTeX RDF
18	Irith Pomeranz	Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests.	ATS	2021	DBLP DOI BibTeX RDF
18	Ping Lu	A 25.6-27.5GHz Phase-Locked Loop for SerDes Transceiver Clocking in 5nm FinFET.	NorCAS	2021	DBLP DOI BibTeX RDF
18	Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha	A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.	ISSCC	2021	DBLP DOI BibTeX RDF
18	Chi-Hsiang Huang 0001, Xun Sun, Yidong Chen, Rajesh Pamula 0001, Arindam Mandal, Visvesh Sathe 0001	A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS.	ISSCC	2021	DBLP DOI BibTeX RDF
18	Ping-Hsuan Hsieh, Mingoo Seok, Keith A. Bowman	Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE.	ISSCC	2021	DBLP DOI BibTeX RDF
18	Dongin Kim, SeongHwan Cho	An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS.	A-SSCC	2021	DBLP DOI BibTeX RDF
18	Weiwei Shan, Wentao Dai, Liang Wan, Minyi Lu, Longxing Shi, Mingoo Seok, Jun Yang 0006	A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF