Search results for "layout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
38	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division
37	Avaneendra Gupta, John P. Hayes	CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	CMOS networks, circuit clustering, diffusion sharing, leaf cell synthesis, transistor chains, two-dimensional layout, integer programming, integer linear programming, layout optimization, module generation
37	Glenn Holt, Akhilesh Tyagi	EPNR: an energy-efficient automated layout synthesis package.	ICCD	1995	DBLP DOI BibTeX RDF	EPNR, energy-efficient automated layout synthesis package, MCNC Logic Synthesis '93 benchmarks, VPNR, VLSI energy minimization problems, VLSI, logic testing, placement, logic CAD, circuit layout CAD, global routing, logic arrays, standard cells, channel routing
37	Tamara Munzner	H3: laying out large directed graphs in 3D hyperbolic space.	INFOVIS	1997	DBLP DOI BibTeX RDF	large directed graphs, 3D hyperbolic space, H3 layout technique, euclidean 3-space, cone tree layout algorithm, hyperbolic navigation, subtree pruning, optimization, directed graphs, data visualization, spanning tree, graph drawing, hierarchical data, node-link diagrams, visual clutter, domain-specific knowledge
37	Gary S. D. Farrow, Costas S. Xydeas, John P. Oakley	Model matching in intelligent document understanding.	ICDAR	1995	DBLP DOI BibTeX RDF	intelligent document understanding, hybrid bottom-up/top-down control strategy, appropriate page layout structure, error propagation model, computationally simple search strategies, maximal column area coverage, probabilistic layout object selection, optical character recognition, document image processing, search problems, model matching
37	Scott E. Hudson, Chen-Ning Hsi	A synergistic approach to specifying simple number independent layouts by example.	INTERCHI	1993	DBLP DOI BibTeX RDF	end-user customization, grid-based layout, layout specification, generalization, programming by example
36	Kaiyou Lei	Research on Constrained Layout Optimization Problem Using Multi-adaptive Strategies Particle Swarm Optimizer.	AICI	2009	DBLP DOI BibTeX RDF	premature problem, constrained layout, particle swarm optimization
36	Kun Yuan, Jae-Seok Yang, David Z. Pan	Double patterning layout decomposition for simultaneous conflict and stitch minimization.	ISPD	2009	DBLP DOI BibTeX RDF	double patterning lithography, layout decomposition, integer linear programming
36	Marcus Furuholmen, Kyrre Harald Glette, Mats Erling Høvin, Jim Tørresen	Scalability, generalization and coevolution -- experimental comparisons applied to automated facility layout planning.	GECCO	2009	DBLP DOI BibTeX RDF	facility layout problem, development, coevolution, gene expression programming
36	Joseph Gil, William W. Pugh, Grant E. Weddell, Yoav Zibin	Two-dimensional bidirectional object layout.	ACM Trans. Program. Lang. Syst.	2008	DBLP DOI BibTeX RDF	coloring, hierarchy, inheritance, layout, bidirectional
36	Xiaozhen Mi, Xiaodong Zhao, Wenzhong Zhao, Wenhui Fan	Case Study on Optimization of Rectangular Object Layout by Genetic Algorithm.	CSCWD (Selected Papers)	2007	DBLP DOI BibTeX RDF	Rectangular Object Layout, Guillotine, Nesting optimization, Material quota, Genetic Algorithm
36	Nathaniel McIntosh, Sandya Mannarswamy, Robert Hundt	Whole-program optimization of global variable layout.	PACT	2006	DBLP DOI BibTeX RDF	compiler-directed memory management, global variable layout, data caches
36	Decai Huang, Jia Hu, Yuan Yuan	Primary-Color-Based Spatial Layout Features and New Image Matching Algorithm Based on Dual Features.	ICAT	2006	DBLP DOI BibTeX RDF	primary color, spatial layout feature, Image retrieval
36	Nathan Hurst, Kim Marriott, David W. Albrecht	Solving the simple continuous table layout problem.	ACM Symposium on Document Engineering	2006	DBLP DOI BibTeX RDF	automatic table layout, constrained optimization
36	Hiromichi Fukutake, Yoshiaki Akazawa, Yoshihiro Okada, Koichi Niijima	3D Object Layout by Voice Commands Based on Contact Constraints.	CGIV	2005	DBLP DOI BibTeX RDF	3D Scene Generation, 3D Object Layout, Voice commands, IntelligentBox
36	Charles E. Jacobs, Wilmot Li, Evan Schrier, David Bargeron, David Salesin	Adaptive grid-based document layout.	ACM Trans. Graph.	2003	DBLP DOI BibTeX RDF	XML, dynamic programming, constraints, HTML, templates, PDF, CSS, XSL, pagination, adaptive layout
36	Simon Lok, Steven Feiner	The AIL automated interface layout system.	IUI	2002	DBLP DOI BibTeX RDF	automated layout, natural language generation
36	Donald S. Gelosh, Dorothy E. Setliff	Modeling layout tools to derive forward estimates of area and delay at the RTL level.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	estimation techniques, machine learning, estimation, layout, VLSI CAD
36	Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy	Cell Swapping Based Migration Methodology for Analog and Custom Layouts.	ISQED	2008	DBLP DOI BibTeX RDF	Layout migration, compaction, constraint generation
35	Sebastian Feuerstack, Marco Blumendorf, Veit Schwartze, Sahin Albayrak	Model-based layout generation.	AVI	2008	DBLP DOI BibTeX RDF	human-computer interaction, layouting, context-of-use, model-based user interfaces, constraint generation
35	Kamran Ali, Knut Hartmann, Georg Fuchs, Heidrun Schumann	Adaptive Layout for Interactive Documents.	Smart Graphics	2008	DBLP DOI BibTeX RDF
35	Siyuan Chen, Song Mao, George R. Thoma	Simultaneous Layout Style and Logical Entity Recognition in a Heterogeneous Collection of Documents.	ICDAR	2007	DBLP DOI BibTeX RDF
35	Susanne Jucknath-John, Dennis Graf, Gabriele Taentzer	Evolutionary layout: preserving the mental map during the development of class models.	SOFTVIS	2006	DBLP DOI BibTeX RDF
35	Cao Yan, Jiang Du 0004, Lina Yang, Yanli Yang, Bai Yu, Dawei Zhang, Rujia Zhao	Development of a Sheet Metal Part Stock Layout System Based on OPENCASCADE Platform.	IMSCCS (2)	2006	DBLP DOI BibTeX RDF
35	John William Lumley, Roger Gimson, Owen Rees	Resolving layout interdependency with presentational variables.	ACM Symposium on Document Engineering	2006	DBLP DOI BibTeX RDF	functional programming, XSLT, SVG, document construction
35	Jianwen Zhu, Fang Fang, Qianying Tang	Calligrapher: a new layout-migration engine for hard intellectual property libraries.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
35	Bernhard Wess, Thomas Zeitlhofer	On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment.	SCOPES	2004	DBLP DOI BibTeX RDF
35	Roberta L. Klatzky, Susan J. Lederman	How Well Can We Encode Spatial Layout from Sparse Kinesthetic Contact?	HAPTICS	2003	DBLP DOI BibTeX RDF
35	Qi-De Qian, Sheldon X.-D. Tan	Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis.	ISQED	2003	DBLP DOI BibTeX RDF
35	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky	Area fill synthesis for uniform layout density.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
35	Shai Rubin, Rastislav Bodík, Trishul M. Chilimbi	An efficient profile-analysis framework for data-layout optimizations.	POPL	2002	DBLP DOI BibTeX RDF
35	Pedram Khademsameni, Marek Syrzycki	Manufacturability Analysis of Analog CMOS ICs through Examination of Multiple Layout Solutions.	DFT	2002	DBLP DOI BibTeX RDF
35	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Analysis of Memory Hierarchy Performance of Block Data Layout.	ICPP	2002	DBLP DOI BibTeX RDF
35	Clemens Kerer, Engin Kirda	Layout, Content and Logic Separation in Web Engineering.	Web Engineering	2001	DBLP DOI BibTeX RDF
35	Tatiana Kalganova, Julian F. Miller	Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-Objective Fitness.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
35	Jianying Hu, Ramanujan S. Kashi, Gordon T. Wilfong	Document Image Layout Comparison and Classification.	ICDAR	1999	DBLP DOI BibTeX RDF
35	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska	Post-Layout Logic Restructuring for Performance Optimization.	DAC	1997	DBLP DOI BibTeX RDF
35	Tatsuya Shindo, Hidetoshi Iwashita, Shaun Kaneshiro, Tsunehisa Doi, Junichi Hagiwara	Twisted data layout.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
35	Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu	An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
35	Mary Jane Irwin, Robert Michael Owens	A Comparison of Four Two-dimensional Gate Matrix Layout Tools.	DAC	1989	DBLP DOI BibTeX RDF
34	Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
34	Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar	Testability-oriented channel routing.	VLSI Design	1995	DBLP DOI BibTeX RDF	IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield
33	Anikó Simon, Jean-Christophe Pret, A. Peter Johnson	A Fast Algorithm for Bottom-Up Document Layout Analysis.	IEEE Trans. Pattern Anal. Mach. Intell.	1997	DBLP DOI BibTeX RDF	physical page layout, bottom-up layout analysis, Kruskal's algorithm, chemical documents, spanning tree, Document analysis
33	Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai	Interchangeable pin routing with application to package layout.	ICCAD	1996	DBLP DOI BibTeX RDF	BGA, all-angle wiring, interchangeable pin routing, min-cost max-flow heuristic, multiple layers, octilinear wiring, package layout, pin redistribution, prerouted nets, rectilinear wiring, test fixture routing, triangulated routing network, CAD, NP-complete, ASIC, circuit layout CAD, speed, PGA, input output, routing problems
33	Antonie Azokly, Rolf Ingold	A language for document generic layout description and its use for segmentation into regions.	ICDAR	1995	DBLP DOI BibTeX RDF	document generic layout description language, generic layout description, region boundary delimiters, separator determination, segmentation method, page description languages
32	Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi	Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.	ICCAD	2006	DBLP DOI BibTeX RDF	analog/RF integrated circuits, layout automation, layout symmetry, design reuse, parasitics
32	Vinod Anupam, Shaul Dar, Ted Leibfried, Eric Petajan	Research report: DataSpace: 3-D visualizations of large databases.	INFOVIS	1995	DBLP DOI BibTeX RDF	interactive 3D visualization, large database analysis, display space, information panels, 3D graph layout, continuous navigation facilities, selective rearrangements, image merging, 3D graphic operations, query step, rendering step, layout step, query processing, data analysis, transparency, data visualisation, very large databases, large databases, computer displays, DataSpace, image comparison, performance issues
32	Guangchun Luo, Jun Zhang, Xianliang Lu, Jun Lu	Active block layout: a high performance disk layout mechanism.	ACM SIGOPS Oper. Syst. Rev.	2003	DBLP DOI BibTeX RDF	performance, layout, disk
32	Leo A. Meyerovich, Rastislav Bodík	Fast and parallel webpage layout.	WWW	2010	DBLP DOI BibTeX RDF	box model, mobile, html, multicore, layout, attribute grammar, css, font, selector
32	Rani S. Ghaida, Payman Zarkesh-Ha	A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	Layout sensitivity, Narrow defects, Electromigration, Critical area, Yield prediction, Yield modeling, Spot defects
32	Jamie Shotton, John M. Winn, Carsten Rother, Antonio Criminisi	TextonBoost for Image Understanding: Multi-Class Object Recognition and Segmentation by Jointly Modeling Texture, Layout, and Context.	Int. J. Comput. Vis.	2009	DBLP DOI BibTeX RDF	Semantic image segmentation, Piecewise training, Segmentation, Context, Object recognition, Texture, Boosting, Layout, Conditional random field, Image understanding, Textons
32	Cameron Braganza, Kim Marriott, Peter Moulder, Michael Wybrow, Tim Dwyer	Scrolling behaviour with single- and multi-column layout.	WWW	2009	DBLP DOI BibTeX RDF	multi-column layout, web-browser, reading, scrolling
32	Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly	Transistor-level layout of high-density regular circuits.	ISPD	2009	DBLP DOI BibTeX RDF	transistor layout, placement and routing, regular fabric, dfm
32	Kaiyou Lei	Constrained Layout Optimization Based on Adaptive Particle Swarm Optimizer.	ISICA	2009	DBLP DOI BibTeX RDF	premature problem, constrained layout optimization, dynamic performance constraints, particle swarm optimization
32	Yun Ye, Frank Liu 0001, Min Chen 0024, Yu Cao 0001	Variability analysis under layout pattern-dependent rapid-thermal annealing process.	DAC	2009	DBLP DOI BibTeX RDF	dopant activation, layout pattern, rapid-thermal annealing, threshold voltage variation, physical design
32	Bodin Dresevic, Aleksandar Uzelac, Bogdan Radakovic, Nikola Todic	Book Layout Analysis: TOC Structure Extraction Engine.	INEX	2008	DBLP DOI BibTeX RDF	book layout analysis, TOC, TOC navigation, ocrml, bookml, information extraction
32	Wang Chen, Yanjun Shi, Hong-fei Teng	An Improved Differential Evolution with Local Search for Constrained Layout Optimization of Satellite Module.	ICIC (2)	2008	DBLP DOI BibTeX RDF	layout design, satellite module, genetic algorithm, combinatorial optimization, Differential evolution
32	Jyh-Jong Tsay, Bo-Liang Wu, Yu-Sen Jeng	Hierarchically Organized Layout for Visualization of Biochemical Pathway.	BMEI (1)	2008	DBLP DOI BibTeX RDF	Pathway Layout, Biochemical
32	Almitra Pradhan, Ranga Vemuri	A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	layout-aware, matrix-models, sizing
32	Nathan Hurst, Kim Marriott	Satisficing scrolls: a shortcut to satisfactory layout.	ACM Symposium on Document Engineering	2008	DBLP DOI BibTeX RDF	floating figure, multi-column layout, optimisation techniques
32	Cheih-Ying Chen, Ying-Jye Lee, Fong-Gong Wu, Chi-Fu Su	Screen Layout on Color Search Task for Customized Product Color Combination Selection.	HCI (2)	2007	DBLP DOI BibTeX RDF	Product color, Color name, Mass customization, Screen layout
32	Shin'ichiro Eitoku, Shunichi Yonemura, Ken-ichiro Shimokura	Impact of Sign Language Movie and Text Layout on the Readout Time.	HCI (5)	2007	DBLP DOI BibTeX RDF	Emergency message, Layout, Sign Language, Public Space
32	Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz	Automated generation of layout and control for quantum circuits.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	ion trap, CAD, control, quantum computing, layout
32	Junhyung Um, Taewhan Kim	Resource Sharing Combined with Layout Effects in High-Level Synthesis.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	resource allocation, high-level synthesis, layout
32	Walter Dees	Device Independent Layout And Style Editing Using Multi-Level Style Sheets.	CADUI	2006	DBLP DOI BibTeX RDF	Concrete user interface, Device independent authoring, Multi-level style sheets, Adaptation, Layout, Style, User interface generation, Multi-platform user interfaces
32	Alexander J. Macdonald, David F. Brailsford, John William Lumley	Evaluating invariances in document layout functions.	ACM Symposium on Document Engineering	2006	DBLP DOI BibTeX RDF	XML, optimisation, XSLT, SVG, document layout
32	Xin Yuan, Kevin W. McCullen, Fook-Luen Heng, Robert F. Walker, Jason Hibbeler, Robert J. Allen, Rani R. Narayan	Technology migration technique for designs with strong RET-driven layout restrictions.	ISPD	2005	DBLP DOI BibTeX RDF	RDR, RET-driven layout, restrictive design rules, technology migration
32	Sergio Beker, Nicolas Puech, Vasilis Friderikos	A Tabu Search Heuristic for the Offline MPLS Reduced Complexity Layout Design Problem.	NETWORKING	2004	DBLP DOI BibTeX RDF	Layout Complexity, Tabu Search, Traffic Engineering, MPLS, Multicommodity Flow, LSP, MINLP
32	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri	Fast and accurate parasitic capacitance models for layout-aware.	DAC	2004	DBLP DOI BibTeX RDF	layout aware, parasitic estimation, analog synthesis
32	Jean Flower, Peter Rodgers 0001, Paul Mutton	Layout Metrics for Euler Diagrams.	IV	2003	DBLP DOI BibTeX RDF	layout metrics, graph drawing, Euler diagrams
32	Josep Díaz, Jordi Petit, Maria J. Serna	A survey of graph layout problems.	ACM Comput. Surv.	2002	DBLP DOI BibTeX RDF	Approximation algorithms, complexity, heuristics, embedding, layout, random graphs, parameterized complexity
32	Stefan Klink, Thomas Kieninger	Rule-based document structure understanding with a fuzzy combination of layout and textual features.	Int. J. Document Anal. Recognit.	2001	DBLP DOI BibTeX RDF	Document structure analysis, Fuzzy feature combination, Document understanding, Layout analysis, Rule-based approach
32	Y. H. Liu-Gong, Bernard Dubuisson, H. N. Pham	A general analysis system for document's layout structure recognition.	ICDAR	1995	DBLP DOI BibTeX RDF	document layout structure recognition, image segmentation, rules, document image processing, document image processing, object oriented method, generic models, document recognition, document analysis system
32	Kanad Chakraborty, Pinaki Mazumder	Technology and layout-related testing of static random-access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Array layout, cell technology, Gallium Arsenide (GaAs), high electron mobility transistor (HEMT) RAMs, I DD testing, I DDQ testing
31	Zheng Liu, Lihong Zhang	Performance-constrained template-driven retargeting for analog and RF layouts.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	optimization, performance, layout, retargeting, parasitics
31	Ying Tu, Han-Wei Shen	Visualizing Changes of Hierarchical Data using Treemaps.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	visualize changes, treemap layout algorithm, Treemap, tree comparison
31	Sunyu Hwang, Geehyuk Lee	Qwerty-like 3x4 keypad layouts for mobile phone.	CHI Extended Abstracts	2005	DBLP DOI BibTeX RDF	QWERTY keyboard layout, QWERTY-like keypad layouts, mobile phone
31	Guihai Chen, Francis C. M. Lau 0001	Tighter Layouts of the Cube-Connected Cycles.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	routing, VLSI, Interconnection networks, embedding, layout, cube-connected cycles
31	Vincent W. L. Tam	Removing Node and Edge Overlapping in Graph Layouts by a Modified EGENET Solver.	ICTAI	1999	DBLP DOI BibTeX RDF	Graph Layout Problems, Local Search Methods
31	Paola Bertolazzi, Giuseppe Di Battista, Giuseppe Liotta	Parametric Graph Drawing.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	Automatic layout facility, graph drawing algorithm, diagram
31	Hua Tang, Hui Zhang 0057, Alex Doboli	Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing.	ISVLSI	2003	DBLP DOI BibTeX RDF
30	Ender Yilmaz, Günhan Dündar	Analog Layout Generator for CMOS Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
30	Ben L. Titzer, Jens Palsberg	Vertical Object Layout and Compression for Fixed Heaps.	Semantics and Algebraic Specification	2009	DBLP DOI BibTeX RDF
30	Chris Muelder, Kwan-Liu Ma	A Treemap Based Method for Rapid Layout of Large Graphs.	PacificVis	2008	DBLP DOI BibTeX RDF
30	Andrew B. Kahng, Chul-Hong Park, Xu Xu 0001, Hailong Yao	Layout decomposition for double patterning lithography.	ICCAD	2008	DBLP DOI BibTeX RDF
30	Mayur Bubna, Sudip Roy 0002, Naresh Shenoy, Subhra Mazumdar 0002	A layout-aware physical design method for constructing feasible QCA circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	routing, partitioning, placement, quantum-dot cellular automata
30	Jarkko Itkonen, Balázs P. Tuzson, Jukka Lempiäinen	A Novel Network Layout for CDMA Cellular Networks with Optimal Base Station Antenna Height and Downtilt.	VTC Spring	2006	DBLP DOI BibTeX RDF
30	Koenraad Mertens, Tom Holvoet, Yolande Berbers	A case for adaptation of the distributed environment layout in multiagent applications.	ACM SIGSOFT Softw. Eng. Notes	2005	DBLP DOI BibTeX RDF
30	Miodrag Vujkovic, David Wadkins, Carl Sechen	Efficient Post-layout Power-Delay Curve Generation.	PATMOS	2005	DBLP DOI BibTeX RDF
30	Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga	A post layout watermarking method for IP protection.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
30	Ardhendu Behera, Denis Lalanne, Rolf Ingold	Enhancement of Layout-based Identification of Low-resolution Documents using Geometrical Color Distribution.	ICDAR	2005	DBLP DOI BibTeX RDF
30	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
30	Ian Kuon, Aaron Egier, Jonathan Rose	Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
30	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.	ASP-DAC	2004	DBLP DOI BibTeX RDF
30	Enrica Zola, Francisco Barceló 0001	Planning the Base Station Layout in UMTS Urban Scenarios: A Simulation Approach to Coverage and Capacity Estimation.	ICT	2004	DBLP DOI BibTeX RDF
30	Omid Banyasad, Philip T. Cox	An Automatic Layout Algorithm for Lograph.	VL/HCC	2004	DBLP DOI BibTeX RDF
30	Sambuddhi Hettiaratchi, Peter Y. K. Cheung	Mesh Partitioning Approach to Energy Efficient Data Layout.	DATE	2003	DBLP DOI BibTeX RDF
30	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	Automatic analog layout retargeting for new processes and device sizes.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
30	Donato Malerba, Floriana Esposito, Oronzo Altamura, Michelangelo Ceci, Margherita Berardi	Correcting the Document Layout: A Machine Learning Approach.	ICDAR	2003	DBLP DOI BibTeX RDF