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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 2778 publication records. Showing 2778 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Robert Michael Owens, Mary Jane Irwin |
Being Stingy with Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(6), pp. 809-818, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
VLSI signal processor, signal processing architectures, signal processing equipment, VLSI, interconnect, adders, multipliers, digital signal processing chips |
28 | Charles C. Wang |
An Algorithm to Design Finite Field Multipliers Using a Self-Dual Normal Basis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(10), pp. 1457-1460, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
self-dual, Massey-Omura finite-field multiplier, self-dual basis, digital arithmetic, Boolean algebra, normal basis, Massey-Omura multiplier, finite field multipliers, product function |
28 | Marina C. Chen |
The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(3), pp. 329-338, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
highly parallel algorithms synthesis, long multiplication algorithm, binary numbers, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multipliers, Crystal |
28 | In-Shek Hsu, Trieu-Kien Truong, Leslie J. Deutsch, Irving S. Reed |
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(6), pp. 735-739, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
dual-basis multiplier, Massey-Omura normal basis multiplier, Scott-Tavares-Peppard standard basis multiplier, NMOS technology, VLSI, VLSI architecture, multiplying circuits, finite field multipliers, field effect integrated circuits |
28 | John Paul Shen, F. Joel Ferguson |
The Design of Easily Tastabel VLSI Array Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(6), pp. 554-560, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
design for testability, VLSI testing, Array multipliers, C-testability, exhaustive testing |
28 | Hussein T. Mouftah, Kenneth C. Smith, Zvonko G. Vranesic |
Ternary Rate-Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(10), pp. 929-931, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
rate-multipliers, Integrated circuits, three-valued logic |
28 | Kai Hwang 0001 |
Global and Modular Two's Complement Cellular Array Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(4), pp. 300-306, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
two's complement multiplication., Additive multiply modules, cellular array multipliers, two's complement multiplication, LSI arithmetic arrays, multiplication networks, pipelined arithmetic design, computer arithmetic |
28 | Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija |
Energy efficient implementation of parallel CMOS multipliers with improved compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 147-152, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding |
28 | Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume |
Bipartite modular multiplication with twice the bit-length of multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Inf. Sec. ![In: Int. J. Inf. Sec. 8(1), pp. 13-23, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Bipartite modular multiplication, Double-size technique, RSA, Smartcard, Montgomery multiplication, Modular multiplication |
28 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 830-836, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang |
Testing Transition Delay Faults in Modified Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1693-1697, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir |
C-testable bit parallel multipliers over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 5:1-5:18, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable |
28 | Jian-Feng Hu 0002, Ping-Qi Pan |
An efficient approach to updating simplex multipliers in the simplex algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 114(2), pp. 235-248, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 65K05, 90C05 |
28 | Brian J. Hickmann, Michael J. Schulte, Mark A. Erle |
Improved combined binary/decimal fixed-point multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 87-94, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Sri Raga Sudha Garimella, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal |
Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1492-1495, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Man Yan Kong, J. M. Pierre Langlois, Dhamin Al-Khalili |
Efficient FPGA implementation of complex multipliers using the logarithmic number system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3154-3157, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | José Luis Imaña, Román Hermida, Francisco Tirado |
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(12), pp. 1388-1393, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert |
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(4), pp. 370-379, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | José Luis Imaña, Juan Manuel Sánchez |
Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(3), pp. 285-296, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Galois field GF(2m), canonical basis, reconfigurable hardware, normal basis, bit-parallel multiplier |
28 | Martin Novotný, Jan Schmidt |
General Digit Width Normal Basis Multipliers with Circular and Linear Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi |
ByZFAD: a low switching activity architecture for shift-and-add multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 179-183, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity |
28 | Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen |
Post-layout energy-delay analysis of parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | César Luis Alonso, Fernando Caro, José Luis Montaña |
An Evolutionary Strategy for the Multidimensional 0-1 Knapsack Problem Based on Genetic Computation of Surrogate Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWINAC (2) ![In: Artificial Intelligence and Knowledge Engineering Applications: A Bioinspired Approach: First International Work-Conference on the Interplay Between Natural and Artificial Computation, IWINAC 2005, Las Palmas, Canary Islands, Spain, June 15-18, 2005, Proceedings, Part II, pp. 63-73, 2005, Springer, 3-540-26319-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
0–1 integer programming, genetic algorithms, Evolutionary computation, combinatorial optimization, knapsack problem |
28 | Colin D. Walter, David Samyde |
Data Dependent Power Use in Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 4-12, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
EMA, smart card, Differential power analysis, DPA, multiplication, multiplier, RSA cryptosystem |
28 | Soonhak Kwon, Taekyoung Kwon 0002, Young-Ho Park 0001 |
New Architecture for Multiplication in GF(2m) and Comparisons with Normal and Polynomial Basis Multipliers for Elliptic Curve Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2005, 8th International Conference, Seoul, Korea, December 1-2, 2005, Revised Selected Papers, pp. 335-351, 2005, Springer, 3-540-33354-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
linear multiplier, NIST recommended binary fields, elliptic curve cryptography |
28 | Kyle Kelley, David Money Harris |
Very High Radix Scalable Montgomery Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 400-404, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Richard H. Turner, Roger F. Woods |
Highly efficient, limited range multipliers for LUT-based FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(10), pp. 1113-1118, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Berk Sunar |
A Generalized Method for Constructing Subquadratic Complexity GF(2^k) Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(9), pp. 1097-1105, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Yong Ho Hwang, Sang Gyoo Sim, Pil Joong Lee |
Bit-Serial Multipliers for Exponentiation and Division in GF(2m) Using Irreducible AOP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part I, pp. 442-450, 2004, Springer, 3-540-22054-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Irreducible AOP, Finite field, Exponentiation, Bit-serial multiplier |
28 | Michele Elia, Manuel Leone |
A Basis-Independent Algorithm to Design Fast Parallel Multipliers over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (2) ![In: International Conference on Information Technology: Coding and Computing (ITCC'04), Volume 2, April 5-7, 2004, Las Vegas, Nevada, USA, pp. 553-559, 2004, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Jonathan Eckstein |
A practical general approximation criterion for methods of multipliers based on Bregman distances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 96(1), pp. 61-86, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara |
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 260-261, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Michael A. Soderstrand |
CSD multipliers for FPGA DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 469-472, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Michele Elia, Manuel Leone |
On the Inherent Space Complexity of Fast Parallel Multipliers for GF(2/supm/). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(3), pp. 346-351, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
finite fields, parallel multiplier, optimal normal basis |
28 | Lan-Da Van, Sung-Huang Lee |
A generalized methodology for lower-error area-efficient fixed-width multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 65-68, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Oscar Gustafsson, Andrew G. Dempster, Lars Wanhammar |
Extended results for minimum-adder constant integer multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 73-76, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Arash Reyhani-Masoleh, M. Anwarul Hasan |
Error Detection in Polynomial Basis Multipliers over Binary Extension Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers, pp. 515-528, 2002, Springer, 3-540-00409-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
polynomial basis multiplier, fault tolerant computing, Finite fields, error detection |
28 | Soonhak Kwon |
Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 4th International Conference, ICICS 2002, Singapore, December 9-12, 2002, Proceedings, pp. 209-216, 2002, Springer, 3-540-00164-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
systolic multiplier, finite field, basis, all one polynomial |
28 | Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee |
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(5), pp. 385-393, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
AOP, finite field, Bit-parallel systolic multiplier, ESP |
28 | Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk |
A Digit-Serial Structure for Reconfigurable Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 565-573, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar |
Minimum-adder integer multipliers using carry-save adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 709-712, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Kazimierz Wiatr, Ernest Jamro |
Implementation of Multipliers in FPGA Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 415-420, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Tim Courtney, Richard H. Turner, Roger F. Woods |
Multiplexer Based Reconfiguration for Virtex Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 749-758, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Alfonso Gerevini, Ivan Serina |
Lagrange Multipliers for Local Search on Planning Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Local Search for Planning and Scheduling ![In: Local Search for Planning and Scheduling, ECAI 2000 Workshop, Berlin, Germany, August 21, 2000, Revised Papers, pp. 37-54, 2000, Springer, 3-540-42898-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Michael Nicolaidis, Ricardo de Oliveira Duarte |
Fault-Secure Parity Prediction Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(3), pp. 90-101, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry |
Low-Power Design of Finite Field Multipliers for Wireless Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 19-25, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
architecture, low power, finite fields, multiplier |
28 | Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer |
On testable multipliers for fixed-width data path architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 541-547, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Fixed-Width Architectures, Built-in Self -Test, High-level Synthesis, Design for Testability |
25 | Ivan Zholubak, Valeriy Hlukhov |
Validation of Multipliers for Elements of Extended Galois Fields GF(pn) and Multipliers VHDL-descriptions Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSIT ![In: 18th IEEE International Conference on Computer Science and Information Technologies, CSIT 2023, Lviv, Ukraine, October 19-21, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-6046-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Martin Langhammer, Bogdan Pasca 0001, Gregg Baeckler, Sergey Gribok |
Extracting INT8 Multipliers from INT18 Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019, pp. 114-120, 2019, IEEE, 978-1-7281-4884-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie |
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(2), pp. 725-734, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo, Fabio Tessitore, Ettore Napoli |
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9), pp. 2375-2388, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Birgit Engels, Sven Oliver Krumke, Rainer Schrader, Christiane Zeck |
Integer Flow with Multipliers: The Special Case of Multipliers 1 and 2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CTW ![In: Proceedings of the 8th Cologne-Twente Workshop on Graphs and Combinatorial Optimization, CTW 2009, Paris, France, June 2-4 2009, pp. 239-243, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
25 | W. Cary Huffman, Vanessa R. Job, Vera Pless |
Multipliers and Generalized Multipliers of Cyclic Objects and Cyclic Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Theory, Ser. A ![In: J. Comb. Theory, Ser. A 62(2), pp. 183-215, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
23 | Lelia Festila, Lorant Andras Szolga, Mihaela Cirlugea, Robert Groza |
Analog Multiplying/Weighting VLSI Cells for SVM Classifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (3) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 12th International Conference, KES 2008, Zagreb, Croatia, September 3-5, 2008, Proceedings, Part III, pp. 360-367, 2008, Springer, 978-3-540-85566-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
weighting circuits, th domain, square-root domain, current controlled amplifiers, analog multipliers |
23 | Ioannis C. Demetriou |
Algorithm 863: L2WPMA, a Fortran 77 package for weighted least-squares piecewise monotonic data approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Math. Softw. ![In: ACM Trans. Math. Softw. 33(1), pp. 6, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
data smoothing, peak finding, piecewise monotonic, pound/dollar exchange rate, turning point, image processing, dynamic programming, Approximation, signal processing, histogram, spline, fitting, Lagrange multipliers, isotonic regression, divided difference |
23 | Raymond J. Madachy |
Distributed Global Development Parametric Cost Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSP ![In: Software Process Dynamics and Agility, International Conference on Software Process, ICSP 2007, Minneapolis, MN, USA, May 19-20, 2007, Proceedings, pp. 159-168, 2007, Springer, 978-3-540-72425-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
parametric cost modeling, Detailed COCOMO, phasesensitive effort multipliers, labor distribution, subcontracting, cost estimation, global software development, distributed teams, COCOMO, Distributed development, software lifecycles |
23 | Paraskevas Kalivas, Vassilis Vassilakis, Chris Meletis, Kiamal Z. Pekmestzi |
A New Low Latency Parallel FIR Filter Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 39(3), pp. 313-322, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FIR filters, array multipliers |
23 | James Alfred Walker, Julian Francis Miller |
Investigating the performance of module acquisition in cartesian genetic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Proceedings, Washington DC, USA, June 25-29, 2005, pp. 1649-1656, 2005, ACM, 1-59593-010-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
digital adders, digital comparators, digital multipliers, modularity, cartesian genetic programming, computational effort, module acquisition |
23 | Serafeim Polyzos |
Public works, investments and their regional economic effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Oper. Res. ![In: Oper. Res. 4(3), pp. 373-388, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Investments Programming, Regional Economic Changes, Regional Multipliers |
23 | Julien Lenoir, Sylvère Fonteneau |
Mixing Deformable and Rigid-Body Mechanics Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Graphics International ![In: 2004 Computer Graphics International (CGI 2004), 16-19 June 2004, Crete, Greece, pp. 327-334, 2004, IEEE Computer Society, 0-7695-2171-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Deformable continuous models, Constraints, Physically-based animation, Lagrange multipliers, Rigid bodies |
23 | Wolfgang Dahmen, Torben Klint, Karsten Urban |
On Fictitious Domain Formulations for Maxwell's Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Found. Comput. Math. ![In: Found. Comput. Math. 3(2), pp. 135-143, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Fictitious domain method, AMS Classification. 35Q60, 78A25, 65N99, 47F05, Lagrange multipliers, Saddle point problems, Maxwell's equations, 65J10 |
23 | Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer |
Testing Schemes for FIR Filter Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(7), pp. 674-688, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Complex multipliers, sign-extended adders, trees of adders, design for testability, FIR filters, pseudoexhaustive testing, state coverage, cell fault model |
23 | David W. Lin, Jiann-Jone Chen |
Efficient Optimal Rate-Distortion Coding of Video Sequences Under Multiple Rate Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 29-32, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
rate-distortion coding, multiple rate constraints, quantization scales, channel constraints, delayed-coding framework, multiple Lagrange multipliers, Lagrangian optimization theory, video coding, video coding, video sequences, efficient algorithm, optimal coding, buffer constraints |
23 | Alexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., Marcio L. Graciano Jr., José C. da Costa |
Design of a Hybrid Digital-Analog Neural Co-Processor for Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 513-519, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
hybrid digital-analog neural co-processor, digitally-controlled multiplexing, CMOS analog circuits, VLSI, signal processing, VLSI design, multilayer perceptrons, VLSI implementation, hybrid architecture, capacitors, analog multipliers |
23 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 192-198, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
23 | Enric Musoll, Jordi Cortadella |
Scheduling and resource binding for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 104-109, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding |
23 | B. Hamdi, Hakim Bederr, Michael Nicolaidis |
A tool for automatic generation of self-checking data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 460-466, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers |
23 | S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta |
A single chip, pipelined, cascadable, multichannel, signal processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 150-155, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron |
23 | Priyadarsan Patra, Donald S. Fussell |
Fully asynchronous, robust, high-throughput arithmetic structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 141-145, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers |
23 | D. V. Poornaiah, P. V. Ananda Mohan |
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 392-397, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron |
23 | Abdulah Abdulah Zadeh |
A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Third International Conference on Availability, Reliability and Security, ARES 2008, March 4-7, 2008, Technical University of Catalonia, Barcelona , Spain, pp. 1346-1351, 2008, IEEE Computer Society, 978-0-7695-3102-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hybrid multiplier, GF, Polynomial (Standard) Basis, Finite Field |
23 | José Luis Montaña, César Luis Alonso, Stefano Cagnoni, Mar Callau |
Computing Surrogate Constraints for Multidimensional Knapsack Problems Using Evolution Strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 555-564, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Kuan-Hung Chen, Yuan-Sun Chu |
A Low-Power Multiplier With the Spurious Power Suppression Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 846-850, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi |
Comb Architectures for Finite Field Multiplication in F(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(7), pp. 909-916, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, elliptic curve cryptography, normal basis, redundant representation, Finite field multiplier |
23 | Heumpil Cho, Earl E. Swartzlander Jr. |
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 7-15, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Juha Yli-Kaakinen, Tapio Saramäki |
A Simplified Structure for FIR Filters with an Adjustable Fractional Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3439-3442, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Julia L. Higle, Suvrajeet Sen |
Multistage stochastic convex programs: Duality and its implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 142(1), pp. 129-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
EVPI, Duality, Stochastic Programming |
23 | Håkan Johansson, Per Löwenborg, K. Vengattaramane |
Reconstruction of two-periodic nonuniformly sampled signals using polynomial impulse response time-varying FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Kavish Seth, K. N. Viswajith, S. Srinivasan 0001, V. Kamakoti 0001 |
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 517-520, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Stefan Mangard, Kai Schramm |
Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 76-90, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Zero-Offset DPA, Zero-Input DPA, Delay Chains, AES, DPA, Masking, Glitches |
23 | Xuewu Du |
Results on Exactness Properties of the HP-ALF for Inequality Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 638-641, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba |
Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 460-466, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Yourim Yoon, Yong-Hyuk Kim, Byung Ro Moon |
An evolutionary lagrangian method for the 0/1 multiple knapsack problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Proceedings, Washington DC, USA, June 25-29, 2005, pp. 629-635, 2005, ACM, 1-59593-010-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
zero/one multiple knapsack problem, evolution strategy, lagrange multiplier |
23 | Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi |
Sign bit reduction encoding for low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 214-217, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
signed multiplier, sing extension, low power, switching activity, bus encoding |
23 | Arash Reyhani-Masoleh, M. Anwar Hasan |
Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(8), pp. 945-959, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Michael J. Wirthlin |
Constant Coefficient Multiplication Using Look-Up Tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 36(1), pp. 7-15, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, DSP, multiplication, look-up table |
23 | Ciaran McIvor, Máire McLoone, John V. McCanny |
FPGA Montgomery Multiplier Architectures - A Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 279-282, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Rajendra S. Katti, Joseph Brennan 0001 |
Low Complexity Multiplication in a Finite Field Using Ring Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(4), pp. 418-427, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ring representation, systolic arrays, Finite field multiplication |
23 | Jia Di, Jiann-Shiun Yuan |
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 64-67, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
2-D pipeline gating, power-awareness, array multiplier |
23 | Kent E. Wires, Michael J. Schulte, Don McCarley |
FPGA Resource Reduction Through Truncated Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 574-583, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Peter-Michael Seidel, Lee D. McFearin, David W. Matula |
Binary Multiplication Radix-32 and Radix-256. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 23-32, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
23 | Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds |
High performance low power array multiplier using temporal tiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(1), pp. 121-124, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Gareth Keane, Jonathan R. Spanier, Roger F. Woods |
The impact of data characteristics and hardware topology on hardware selection for low power DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 94-96, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Pei-Chi Wu |
Multiplicative, Congruential Random-Number Generators with Multiplier ± 2k1 ± 2k2 and modulus 2p -; 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Math. Softw. ![In: ACM Trans. Math. Softw. 23(2), pp. 255-265, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
cycle length, multiplicative congruential random-number generators, efficiency, portability, spectral test |
20 | Mustafa Gök, Metin Mete Özbilen |
Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(1), pp. 51-57, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Floating-point multiplier, Sticky-bit, Rounding |
20 | Sjur Didrik Flåm, Hubertus Th. Jongen, Oliver Stein |
Slopes of shadow prices and Lagrange multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Optim. Lett. ![In: Optim. Lett. 2(2), pp. 143-155, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Optimal value function, Shadow price, Karush-Kuhn-Tucker system, Sensitivity, Matrix inversion |
20 | Jean-Luc Beuchat, Jean-Michel Muller |
Automatic Generation of Modular Multipliers for FPGA Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(12), pp. 1600-1613, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber 0001, Christian Jacobi 0002, Matthias Pflanz |
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 398-403, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Chiou-Yng Lee, Pramod Kumar Meher |
Efficient Bit-Parallel Multipliers in Composite Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSCC ![In: Proceedings of the 3rd IEEE Asia-Pacific Services Computing Conference, APSCC 2008, Yilan, Taiwan, 9-12 December 2008, pp. 686-691, 2008, IEEE Computer Society, 978-0-7695-3473-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Horácio C. Neto, Mário P. Véstias |
Decimal multiplier on FPGA using embedded binary multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 197-202, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
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