Search results for "multipliers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Robert Michael Owens, Mary Jane Irwin	Being Stingy with Multipliers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	VLSI signal processor, signal processing architectures, signal processing equipment, VLSI, interconnect, adders, multipliers, digital signal processing chips
28	Charles C. Wang	An Algorithm to Design Finite Field Multipliers Using a Self-Dual Normal Basis.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	self-dual, Massey-Omura finite-field multiplier, self-dual basis, digital arithmetic, Boolean algebra, normal basis, Massey-Omura multiplier, finite field multipliers, product function
28	Marina C. Chen	The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	highly parallel algorithms synthesis, long multiplication algorithm, binary numbers, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multipliers, Crystal
28	In-Shek Hsu, Trieu-Kien Truong, Leslie J. Deutsch, Irving S. Reed	A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	dual-basis multiplier, Massey-Omura normal basis multiplier, Scott-Tavares-Peppard standard basis multiplier, NMOS technology, VLSI, VLSI architecture, multiplying circuits, finite field multipliers, field effect integrated circuits
28	John Paul Shen, F. Joel Ferguson	The Design of Easily Tastabel VLSI Array Multipliers.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	design for testability, VLSI testing, Array multipliers, C-testability, exhaustive testing
28	Hussein T. Mouftah, Kenneth C. Smith, Zvonko G. Vranesic	Ternary Rate-Multipliers.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	rate-multipliers, Integrated circuits, three-valued logic
28	Kai Hwang 0001	Global and Modular Two's Complement Cellular Array Multipliers.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	two's complement multiplication., Additive multiply modules, cellular array multipliers, two's complement multiplication, LSI arithmetic arrays, multiplication networks, pipelined arithmetic design, computer arithmetic
28	Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija	Energy efficient implementation of parallel CMOS multipliers with improved compressors.	ISLPED	2010	DBLP DOI BibTeX RDF	arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding
28	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Bipartite modular multiplication with twice the bit-length of multipliers.	Int. J. Inf. Sec.	2009	DBLP DOI BibTeX RDF	Bipartite modular multiplication, Double-size technique, RSA, Smartcard, Montgomery multiplication, Modular multiplication
28	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
28	Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang	Testing Transition Delay Faults in Modified Booth Multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
28	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
28	Jian-Feng Hu 0002, Ping-Qi Pan	An efficient approach to updating simplex multipliers in the simplex algorithm.	Math. Program.	2008	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 65K05, 90C05
28	Brian J. Hickmann, Michael J. Schulte, Mark A. Erle	Improved combined binary/decimal fixed-point multipliers.	ICCD	2008	DBLP DOI BibTeX RDF
28	Sri Raga Sudha Garimella, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Man Yan Kong, J. M. Pierre Langlois, Dhamin Al-Khalili	Efficient FPGA implementation of complex multipliers using the logarithmic number system.	ISCAS	2008	DBLP DOI BibTeX RDF
28	José Luis Imaña, Román Hermida, Francisco Tirado	Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
28	Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert	Toward architecture-based test-vector generation for timing verification of fast parallel multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
28	José Luis Imaña, Juan Manuel Sánchez	Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	Galois field GF(2m), canonical basis, reconfigurable hardware, normal basis, bit-parallel multiplier
28	Martin Novotný, Jan Schmidt	General Digit Width Normal Basis Multipliers with Circular and Linear Structure.	FPL	2006	DBLP DOI BibTeX RDF
28	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
28	Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen	Post-layout energy-delay analysis of parallel multipliers.	ISCAS	2006	DBLP DOI BibTeX RDF
28	César Luis Alonso, Fernando Caro, José Luis Montaña	An Evolutionary Strategy for the Multidimensional 0-1 Knapsack Problem Based on Genetic Computation of Surrogate Multipliers.	IWINAC (2)	2005	DBLP DOI BibTeX RDF	0–1 integer programming, genetic algorithms, Evolutionary computation, combinatorial optimization, knapsack problem
28	Colin D. Walter, David Samyde	Data Dependent Power Use in Multipliers.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF	EMA, smart card, Differential power analysis, DPA, multiplication, multiplier, RSA cryptosystem
28	Soonhak Kwon, Taekyoung Kwon 0002, Young-Ho Park 0001	New Architecture for Multiplication in GF(2m) and Comparisons with Normal and Polynomial Basis Multipliers for Elliptic Curve Cryptography.	ICISC	2005	DBLP DOI BibTeX RDF	linear multiplier, NIST recommended binary fields, elliptic curve cryptography
28	Kyle Kelley, David Money Harris	Very High Radix Scalable Montgomery Multipliers.	IWSOC	2005	DBLP DOI BibTeX RDF
28	Richard H. Turner, Roger F. Woods	Highly efficient, limited range multipliers for LUT-based FPGA architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
28	Berk Sunar	A Generalized Method for Constructing Subquadratic Complexity GF(2^k) Multipliers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
28	Yong Ho Hwang, Sang Gyoo Sim, Pil Joong Lee	Bit-Serial Multipliers for Exponentiation and Division in GF(2m) Using Irreducible AOP.	ICCSA (1)	2004	DBLP DOI BibTeX RDF	Irreducible AOP, Finite field, Exponentiation, Bit-serial multiplier
28	Michele Elia, Manuel Leone	A Basis-Independent Algorithm to Design Fast Parallel Multipliers over GF(2m).	ITCC (2)	2004	DBLP DOI BibTeX RDF
28	Jonathan Eckstein	A practical general approximation criterion for methods of multipliers based on Bregman distances.	Math. Program.	2003	DBLP DOI BibTeX RDF
28	Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara	High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.	ISVLSI	2003	DBLP DOI BibTeX RDF
28	Michael A. Soderstrand	CSD multipliers for FPGA DSP applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
28	Michele Elia, Manuel Leone	On the Inherent Space Complexity of Fast Parallel Multipliers for GF(2/supm/).	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	finite fields, parallel multiplier, optimal normal basis
28	Lan-Da Van, Sung-Huang Lee	A generalized methodology for lower-error area-efficient fixed-width multipliers.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
28	Oscar Gustafsson, Andrew G. Dempster, Lars Wanhammar	Extended results for minimum-adder constant integer multipliers.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
28	Arash Reyhani-Masoleh, M. Anwarul Hasan	Error Detection in Polynomial Basis Multipliers over Binary Extension Fields.	CHES	2002	DBLP DOI BibTeX RDF	polynomial basis multiplier, fault tolerant computing, Finite fields, error detection
28	Soonhak Kwon	Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields.	ICICS	2002	DBLP DOI BibTeX RDF	systolic multiplier, finite field, basis, all one polynomial
28	Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee	Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	AOP, finite field, Bit-parallel systolic multiplier, ESP
28	Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk	A Digit-Serial Structure for Reconfigurable Multipliers.	FPL	2001	DBLP DOI BibTeX RDF
28	Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar	Minimum-adder integer multipliers using carry-save adders.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
28	Kazimierz Wiatr, Ernest Jamro	Implementation of Multipliers in FPGA Structures.	ISQED	2001	DBLP DOI BibTeX RDF
28	Tim Courtney, Richard H. Turner, Roger F. Woods	Multiplexer Based Reconfiguration for Virtex Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
28	Alfonso Gerevini, Ivan Serina	Lagrange Multipliers for Local Search on Planning Graphs.	Local Search for Planning and Scheduling	2000	DBLP DOI BibTeX RDF
28	Michael Nicolaidis, Ricardo de Oliveira Duarte	Fault-Secure Parity Prediction Booth Multipliers.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
28	Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry	Low-Power Design of Finite Field Multipliers for Wireless Applications.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	architecture, low power, finite fields, multiplier
28	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	On testable multipliers for fixed-width data path architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Fixed-Width Architectures, Built-in Self -Test, High-level Synthesis, Design for Testability
25	Ivan Zholubak, Valeriy Hlukhov	Validation of Multipliers for Elements of Extended Galois Fields GF(pn) and Multipliers VHDL-descriptions Generator.	CSIT	2023	DBLP DOI BibTeX RDF
25	Martin Langhammer, Bogdan Pasca 0001, Gregg Baeckler, Sergey Gribok	Extracting INT8 Multipliers from INT18 Multipliers.	FPL	2019	DBLP DOI BibTeX RDF
25	Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie	FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
25	Davide De Caro, Nicola Petra, Antonio Giuseppe Maria Strollo, Fabio Tessitore, Ettore Napoli	Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
25	Birgit Engels, Sven Oliver Krumke, Rainer Schrader, Christiane Zeck	Integer Flow with Multipliers: The Special Case of Multipliers 1 and 2.	CTW	2009	DBLP BibTeX RDF
25	W. Cary Huffman, Vanessa R. Job, Vera Pless	Multipliers and Generalized Multipliers of Cyclic Objects and Cyclic Codes.	J. Comb. Theory, Ser. A	1993	DBLP BibTeX RDF
23	Lelia Festila, Lorant Andras Szolga, Mihaela Cirlugea, Robert Groza	Analog Multiplying/Weighting VLSI Cells for SVM Classifiers.	KES (3)	2008	DBLP DOI BibTeX RDF	weighting circuits, th domain, square-root domain, current controlled amplifiers, analog multipliers
23	Ioannis C. Demetriou	Algorithm 863: L2WPMA, a Fortran 77 package for weighted least-squares piecewise monotonic data approximation.	ACM Trans. Math. Softw.	2007	DBLP DOI BibTeX RDF	data smoothing, peak finding, piecewise monotonic, pound/dollar exchange rate, turning point, image processing, dynamic programming, Approximation, signal processing, histogram, spline, fitting, Lagrange multipliers, isotonic regression, divided difference
23	Raymond J. Madachy	Distributed Global Development Parametric Cost Modeling.	ICSP	2007	DBLP DOI BibTeX RDF	parametric cost modeling, Detailed COCOMO, phasesensitive effort multipliers, labor distribution, subcontracting, cost estimation, global software development, distributed teams, COCOMO, Distributed development, software lifecycles
23	Paraskevas Kalivas, Vassilis Vassilakis, Chris Meletis, Kiamal Z. Pekmestzi	A New Low Latency Parallel FIR Filter Scheme.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	FIR filters, array multipliers
23	James Alfred Walker, Julian Francis Miller	Investigating the performance of module acquisition in cartesian genetic programming.	GECCO	2005	DBLP DOI BibTeX RDF	digital adders, digital comparators, digital multipliers, modularity, cartesian genetic programming, computational effort, module acquisition
23	Serafeim Polyzos	Public works, investments and their regional economic effects.	Oper. Res.	2004	DBLP DOI BibTeX RDF	Investments Programming, Regional Economic Changes, Regional Multipliers
23	Julien Lenoir, Sylvère Fonteneau	Mixing Deformable and Rigid-Body Mechanics Simulation.	Computer Graphics International	2004	DBLP DOI BibTeX RDF	Deformable continuous models, Constraints, Physically-based animation, Lagrange multipliers, Rigid bodies
23	Wolfgang Dahmen, Torben Klint, Karsten Urban	On Fictitious Domain Formulations for Maxwell's Equations.	Found. Comput. Math.	2003	DBLP DOI BibTeX RDF	Fictitious domain method, AMS Classification. 35Q60, 78A25, 65N99, 47F05, Lagrange multipliers, Saddle point problems, Maxwell's equations, 65J10
23	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	Testing Schemes for FIR Filter Structures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Complex multipliers, sign-extended adders, trees of adders, design for testability, FIR filters, pseudoexhaustive testing, state coverage, cell fault model
23	David W. Lin, Jiann-Jone Chen	Efficient Optimal Rate-Distortion Coding of Video Sequences Under Multiple Rate Constraints.	ICIP (2)	1997	DBLP DOI BibTeX RDF	rate-distortion coding, multiple rate constraints, quantization scales, channel constraints, delayed-coding framework, multiple Lagrange multipliers, Lagrangian optimization theory, video coding, video coding, video sequences, efficient algorithm, optimal coding, buffer constraints
23	Alexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., Marcio L. Graciano Jr., José C. da Costa	Design of a Hybrid Digital-Analog Neural Co-Processor for Signal Processing.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hybrid digital-analog neural co-processor, digitally-controlled multiplexing, CMOS analog circuits, VLSI, signal processing, VLSI design, multilayer perceptrons, VLSI implementation, hybrid architecture, capacitors, analog multipliers
23	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
23	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
23	B. Hamdi, Hakim Bederr, Michael Nicolaidis	A tool for automatic generation of self-checking data paths.	VTS	1995	DBLP DOI BibTeX RDF	self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers
23	S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta	A single chip, pipelined, cascadable, multichannel, signal processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron
23	Priyadarsan Patra, Donald S. Fussell	Fully asynchronous, robust, high-throughput arithmetic structures.	VLSI Design	1995	DBLP DOI BibTeX RDF	fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
23	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
23	Abdulah Abdulah Zadeh	A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation.	ARES	2008	DBLP DOI BibTeX RDF	Hybrid multiplier, GF, Polynomial (Standard) Basis, Finite Field
23	José Luis Montaña, César Luis Alonso, Stefano Cagnoni, Mar Callau	Computing Surrogate Constraints for Multidimensional Knapsack Problems Using Evolution Strategies.	EvoWorkshops	2008	DBLP DOI BibTeX RDF
23	Kuan-Hung Chen, Yuan-Sun Chu	A Low-Power Multiplier With the Spurious Power Suppression Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
23	Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi	Comb Architectures for Finite Field Multiplication in F(2^m).	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	FPGA, elliptic curve cryptography, normal basis, redundant representation, Finite field multiplier
23	Heumpil Cho, Earl E. Swartzlander Jr.	Serial Parallel Multiplier Design in Quantum-dot Cellular Automata.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
23	Juha Yli-Kaakinen, Tapio Saramäki	A Simplified Structure for FIR Filters with an Adjustable Fractional Delay.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Julia L. Higle, Suvrajeet Sen	Multistage stochastic convex programs: Duality and its implications.	Ann. Oper. Res.	2006	DBLP DOI BibTeX RDF	EVPI, Duality, Stochastic Programming
23	Håkan Johansson, Per Löwenborg, K. Vengattaramane	Reconstruction of two-periodic nonuniformly sampled signals using polynomial impulse response time-varying FIR filters.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Kavish Seth, K. N. Viswajith, S. Srinivasan 0001, V. Kamakoti 0001	Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.	VLSI Design	2006	DBLP DOI BibTeX RDF
23	Stefan Mangard, Kai Schramm	Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations.	CHES	2006	DBLP DOI BibTeX RDF	Zero-Offset DPA, Zero-Input DPA, Delay Chains, AES, DPA, Masking, Glitches
23	Xuewu Du	Results on Exactness Properties of the HP-ALF for Inequality Constraints.	APCCAS	2006	DBLP DOI BibTeX RDF
23	Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba	Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures.	DSD	2005	DBLP DOI BibTeX RDF
23	Yourim Yoon, Yong-Hyuk Kim, Byung Ro Moon	An evolutionary lagrangian method for the 0/1 multiple knapsack problem.	GECCO	2005	DBLP DOI BibTeX RDF	zero/one multiple knapsack problem, evolution strategy, lagrange multiplier
23	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign bit reduction encoding for low power applications.	DAC	2005	DBLP DOI BibTeX RDF	signed multiplier, sing extension, low power, switching activity, bus encoding
23	Arash Reyhani-Masoleh, M. Anwar Hasan	Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}).	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
23	Michael J. Wirthlin	Constant Coefficient Multiplication Using Look-Up Tables.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	FPGA, DSP, multiplication, look-up table
23	Ciaran McIvor, Máire McLoone, John V. McCanny	FPGA Montgomery Multiplier Architectures - A Comparison.	FCCM	2004	DBLP DOI BibTeX RDF
23	Rajendra S. Katti, Joseph Brennan 0001	Low Complexity Multiplication in a Finite Field Using Ring Representation.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	ring representation, systolic arrays, Finite field multiplication
23	Jia Di, Jiann-Shiun Yuan	Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	2-D pipeline gating, power-awareness, array multiplier
23	Kent E. Wires, Michael J. Schulte, Don McCarley	FPGA Resource Reduction Through Truncated Multiplication.	FPL	2001	DBLP DOI BibTeX RDF
23	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Binary Multiplication Radix-32 and Radix-256.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
23	Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds	High performance low power array multiplier using temporal tiling.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
23	Gareth Keane, Jonathan R. Spanier, Roger F. Woods	The impact of data characteristics and hardware topology on hardware selection for low power DSP.	ISLPED	1998	DBLP DOI BibTeX RDF
23	Pei-Chi Wu	Multiplicative, Congruential Random-Number Generators with Multiplier ± 2k1 ± 2k2 and modulus 2p -; 1.	ACM Trans. Math. Softw.	1997	DBLP DOI BibTeX RDF	cycle length, multiplicative congruential random-number generators, efficiency, portability, spectral test
20	Mustafa Gök, Metin Mete Özbilen	Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Floating-point multiplier, Sticky-bit, Rounding
20	Sjur Didrik Flåm, Hubertus Th. Jongen, Oliver Stein	Slopes of shadow prices and Lagrange multipliers.	Optim. Lett.	2008	DBLP DOI BibTeX RDF	Optimal value function, Shadow price, Karush-Kuhn-Tucker system, Sensitivity, Matrix inversion
20	Jean-Luc Beuchat, Jean-Michel Muller	Automatic Generation of Modular Multipliers for FPGA Applications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
20	Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber 0001, Christian Jacobi 0002, Matthias Pflanz	Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.	ASP-DAC	2008	DBLP DOI BibTeX RDF
20	Chiou-Yng Lee, Pramod Kumar Meher	Efficient Bit-Parallel Multipliers in Composite Fields.	APSCC	2008	DBLP DOI BibTeX RDF
20	Horácio C. Neto, Mário P. Véstias	Decimal multiplier on FPGA using embedded binary multipliers.	FPL	2008	DBLP DOI BibTeX RDF