Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Chung-Yen Chang, Prasant Mohapatra	An Integrated Processor Management Scheme for the Mesh-Connected Multicomputer Systems.	ICPP	1997	DBLP DOI BibTeX RDF	Bypass-Queue, Fixed-Orientation Allocation, Integrated Processor Management Scheme, Job Scheduling, Mesh-Connected Multicomputer
28	Kumar N. Ganapathy, Benjamin W. Wah	Optimal Synthesis of Algorithm-Specific Lower-Dimensional Processor Arrays.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	polynomial-time search, transitive closure, processor arrays, optimal design, objective function, Design constraints, uniform recurrence equations
28	An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu	Parallel programmable video co-processor design.	ICIP	1995	DBLP DOI BibTeX RDF	quadrature mirror filters, parallel programmable video co-processor design, computationally intensive data processing, very high data rate, subband filtering, discrete orthogonal transforms, computational speed, multirate FIR/IIR/DT operations, low-power implementation, QMF, parallel architectures, transforms, high-performance, adaptive filters, adaptive filtering, FIR filters, FIR filtering, video signal processing, digital signal processing chips, low-cost, IIR filters, IIR filtering, hardware overhead, video applications, processing speed
28	Mark S. Squillante, Edward D. Lazowska	Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	processor-cache affinity information, shared-memorymultiprocessor scheduling, quantum expiration, meanvalue analysis, analytic cache model, queueingtheory, scheduling, performance evaluation, synchronization, shared memory systems, buffer storage, I/O, preemption, queueing network models
28	Henk Corporaal, J. G. E. Olk	A Scalable Communication Processor Design supporting Systolic Communication.	EDMCC	1991	DBLP DOI BibTeX RDF	high performance communication processor, fine-grain communication, scalability of design, message compression, routing, virtual connections
28	Scott Davidson 0001	How to make your own processor architecture.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	system-on-chip computing, FPGAs, ASICs, processor architecture, processor design
28	Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai	An Integrated Memory Array Processor for Embedded Image Recognition Systems.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Parallel SIMD processor, memory array processor, image processing, image recognition, parallel language
28	Tilman Wolf, Mark A. Franklin	Performance Models for Network Processor Design.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	Network processor design, network processor benchmark, performance model, power optimization, design optimization
28	Matthew Clegg, Keith Marzullo	A low-cost processor group membership protocol for a hard real-time distributed system.	RTSS	1997	DBLP DOI BibTeX RDF	processor group membership protocol, hard real-time distributed system, failure detection latency, processor time, bounded tax, broadcast message traffic, protocols, schedulability analysis, message complexity, shared resources, network bandwidth
28	István Vassányi, István Erényi	Implementation of Processor Cells for Array Algorithms on FPGAs.	EUROMICRO	1996	DBLP DOI BibTeX RDF	array algorithms, processor cells, fine-grain array architectures, cellular image processing algorithms, placement-routing tool, field programmable gate arrays, FPGA, processor arrays
28	Wenjian Qiao, Lionel M. Ni	Efficient processor allocation for 3D tori.	IPPS	1995	DBLP DOI BibTeX RDF	3D tori, 3D submesh, maximal free submeshes, scheduling overhead, performance, resource allocation, reconfigurable architectures, processor scheduling, processor allocation, space sharing, large scale parallel computers, Cray T3D
28	Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa	A superscalar RISC processor with pseudo vector processing feature.	ICCD	1995	DBLP DOI BibTeX RDF	superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems
28	Ram K. Krishnamurthy, Ramalingam Sridhar	A CMOS wave-pipelined image processor for real-time morphology .	ICCD	1995	DBLP DOI BibTeX RDF	CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity
28	William F. Richardson, Erik Brunvand	Precise exception handling for a self-timed processor.	ICCD	1995	DBLP DOI BibTeX RDF	precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems
28	Stephen C. Glinski, David B. Roe	Spoken Language Recognition on a DSP Array Processor.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	speechrecognition, spoken language recognition, DSP array processor, real-time large-vocabulary speaker-independent continuous speech recognizers, multiplehigh-performance central processing units, high interprocessor communication bandwidth, feature extractor, mixture probability computer, state probability computer, word probability computer, phrase probability computer, traceback computer, multistage stack decoder, parallel architectures, partitioning, message passing, array processor, array signal processing, linear predictive coding, linear predictive coding
28	Peter R. Cappello	A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	hexagon shaped, cylinder connected, processor-time-minimal systolic array, cubical meshalgorithms, time-minimal multiprocessor schedules, processor-time-minimal scheduling, triangular shaped 2-D directed mesh, 2-D directed mesh, directedgraphs, parallel algorithms, computational complexity, topology, systolic arrays, directed acyclic graph, processing elements, matrix product
27	L. S. K. Udugama, Janath C. Geeganage	Students' experimental processor: a processor integrated with different types of architectures for educational purposes.	WCAE	2006	DBLP DOI BibTeX RDF
26	Joonhyuk Yoo, Manoj Franklin	The Filter Checker: An Active Verification Management Approach.	DFT	2006	DBLP DOI BibTeX RDF
26	Ivan Stojmenovic	Detecting intersection of two convex polygons in parallel.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF
26	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
26	Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler	Reconciling performance and programmability in networking systems.	SIGCOMM	2007	DBLP DOI BibTeX RDF	memoty bottleneck, multithreading, reconfigurable architectures, routers, data cache, processor architectures, packet processing
26	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Fine-grain performance scaling of soft vector processors.	CASES	2009	DBLP DOI BibTeX RDF	VESPA, soft vector processor, viram, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
26	Jason Yu, Guy G. Lemieux, Christopher Eagleston	Vector processing as a soft-core CPU accelerator.	FPGA	2008	DBLP DOI BibTeX RDF	C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism
26	Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane Irwin	Adaptive set pinning: managing shared caches in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	inter-processor, intra-processor, set pinning, CMP, shared cache
26	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
26	Azzedine Boukerche, Carl Tropper	Hierarchical schedulings of time-next-event heuristic on distributed memory machines.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	semi-global time-next-event heuristic, logical process unblocking, interprocessor deadlocks, processor cluster, queuing network simulation, one-level scheduling, parallel algorithms, concurrency control, distributed memory systems, processor scheduling, torus, heuristic programming, run time, distributed memory machines, hierarchical scheduling, shortest path algorithm, lookahead, two-level scheduling, simulation parallelism
26	Swapan Kumar Ray	Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Content Addressable Memory (CAM), associative store, Associative Memory (AM), pipelined CAM, Content-To-Address Memory (CTAM), pipelined CTAM, Binary Search Processor (BSP), Pipelined Binary Search Processor (PBSP), pipelined binary search, Binary Search Pipeline (BSPL), pipelined search processor, pipelined search engine
26	Xavier Martorell, Jesús Labarta, Nacho Navarro, Eduard Ayguadé	Analysis of Several Scheduling Algorithms under the Nano-Thread Programming Model.	IPPS	1997	DBLP DOI BibTeX RDF	scheduling algorithm analysis, nano-threads programming model, dynamic processor allocation environment, uniform-sized chunking, guided self-scheduling, trapezoid self-scheduling, adaptable size chunking, automatic application decomposition, hierarchical task graph, source application, executable graph representation, user-level library, nano-threads library, user-level process, CPU manager, dynamic processor changes, processor scheduling, parallelizing compiler, parallel code
25	Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero	A distributed processor state management architecture for large-window processors.	MICRO	2008	DBLP DOI BibTeX RDF
25	Qiang Zhu 0008, Aviral Shrivastava, Nikil D. Dutt	Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.	DATE	2007	DBLP DOI BibTeX RDF
25	Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu	Processor Directed Dynamic Page Policy.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Godson-2, Memory Control Policy, Dynamic Page Policy, Open Page, Close Page
25	Roman L. Lysecky, Frank Vahid	A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.	DATE	2005	DBLP DOI BibTeX RDF
25	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
25	H. Peter Hofstee, Michael N. Day	Hardware and software architectures for the CELL processor.	CODES+ISSS	2005	DBLP DOI BibTeX RDF
25	Andreas Hoffmann 0002, Frank Fiedler, Achim Nohl, Surender Parupalli	A Methodology and Tooling Enabling Application Specific Processor Design.	VLSI Design	2005	DBLP DOI BibTeX RDF	SIMD, VLIW, ASIP
25	Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui	Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture.	ICCD	2002	DBLP DOI BibTeX RDF
25	Mostafa I. Soliman, Stanislav Sedukhin	Performance Analysis of SVD Algorithm on the Trident Processor.	CW	2002	DBLP DOI BibTeX RDF
25	Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad	Characterizing processor architectures for programmable network interfaces.	ICS	2000	DBLP DOI BibTeX RDF
25	Rajat Moona	Processor Models for Retargetable Tools.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF
25	Cathy McCann, John Zahorjan	Processor Allocation Policies for Message-Passing Parallel Computers.	SIGMETRICS	1994	DBLP DOI BibTeX RDF
25	Songnian Zhou, Tim Brecht	Processor-Pool-Based Scheduling for Large-Scale NUMA Multiprocessors.	SIGMETRICS	1991	DBLP DOI BibTeX RDF
25	Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang 0006, Cristiano Pereira	Offline symbolic analysis for multi-processor execution replay.	MICRO	2009	DBLP DOI BibTeX RDF	multi-processor replay, shared-memory dependencies, SMT solver
25	George C. Caragea, A. Beliz Saybasili, Xingzhi Wen, Uzi Vishkin	Brief announcement: performance potential of an easy-to-program PRAM-on-chip prototype versus state-of-the-art processor.	SPAA	2009	DBLP DOI BibTeX RDF	ease of programming, explicit multi-treading, on-chip parallel processor, paraleap, parallel algorithms, PRAM, xmt
25	Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design
25	Wolfgang Puffitsch	Decoupled root scanning in multi-processor systems.	CASES	2008	DBLP DOI BibTeX RDF	real-time, garbage collection, multi-processor
25	Xingzhi Wen, Uzi Vishkin	Fpga-based prototype of a pram-on-chip processor.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	ease-of-programming, explicit multi-threading, on-chip parallel processor, pram, parallel algorithms, xmt
25	Jeffrey M. Arnold	The Architecture and Development Flow of the S5 Software Configurable Processor.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	software configurable processor, reconfigurable architectures, embedded computing, instruction set extension
25	Shinya Toji, Minoru Uehara, Hideki Mori	Design of the Tile-Based Embedded Multimedia Processor -TEMP-.	NBiS	2007	DBLP DOI BibTeX RDF	Tile-Based Processor, Embedded System
25	Jorgen Peddersen, Sri Parameswaran	CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time.	ASP-DAC	2007	DBLP DOI BibTeX RDF	dynamic power optimization, CLIPPER, counter-based low impact processor, run-time power optimization, power consumption, energy consumption
25	Satoshi Amamiya, Masaaki Izumi, Takanori Matsuzaki, Ryuzo Hasegawa, Makoto Amamiya	Fuce: the continuation-based multithreading processor.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	continuation-based multithread programming, multithreading, thread-level parallelism, chip multi-processor
25	Ricardo E. Gonzalez	A Software-Configurable Processor Architecture.	IEEE Micro	2006	DBLP DOI BibTeX RDF	software-configurable processor
25	Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa	High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	queue processor, design, prototyping, high performance, high-level modeling
25	Jih-Woei Huang, Chih-Ping Chu	An Efficient Communication Scheduling Method for the Processor Mapping Technique Applied Data Redistribution.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	MPI, parallel compiler, communication scheduling, data redistribution, data-parallel programming, processor mapping
25	Fayez Gebali, A. N. M. Ehtesham Rafiq	Processor Array Architectures for Deep Packet Classification.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	deep packet classification, parallel hardware, Processor array, string search
25	Panagiotis D. Michailidis, Konstantinos G. Margaritis	New Processor Array Architectures for the Longest Common Subsequence Problem.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	longest common subsequence problem, parallel algorithms, VLSI, parallel architectures, linear processor arrays
25	Radu Muresan, Catherine H. Gebotys	Instantaneous current modeling in a complex VLIW processor core.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Instruction-level current model, current and power measurement in a processor, instantaneous current model, power and energy model
25	Jarek Nieplocha, Manojkumar Krishnan, Bruce J. Palmer, Vinod Tipparaju, Yeliang Zhang	Exploiting processor groups to extend scalability of the GA shared memory programming model.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	extreme scalability, multi-level parallelism, processor groups, global arrays
25	Prabhat Mishra 0001, Mahesh Mamidipaka, Nikil D. Dutt	Processor-memory coexploration using an architecture description language.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Processor-memory codesign, memory exploration, design space exploration, architecture description language
25	Ching-Hsien Hsu, Kun-Ming Yu	Processor Mapping Technique For Communication Free Data Redistribution on Symmetrical Matrix.	ISPAN	2004	DBLP DOI BibTeX RDF	communication free, runtime support, data redistribution, symmetrical matrix, processor mapping
25	Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen	Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform.	ASPLOS	2004	DBLP DOI BibTeX RDF	DB2 database, cache miss prefetching, itanium processor, switch-on-event, multithreading, helper thread, PAL
25	Heejo Lee, Jong Kim 0001, Sung Je Hong, Sunggu Lee	Processor Allocation and Task Scheduling of Matrix Chain Products on Parallel Systems.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	Matrix chain product, matrix chain scheduling problem, task scheduling, processor allocation, parallel matrix multiplication
25	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	processor cores, built-in self-test, instruction set, at-speed testing, software-based self test
25	Martin Delvai, Wolfgang Huber, Peter P. Puschner, Andreas Steininger	Processor Support for Temporal Predictability - The SPEAR Design Example.	ECRTS	2003	DBLP DOI BibTeX RDF	real-time processor, response jitter, one path programming, response time, worst case execution time
25	Jinhwan Kim, Sungjoon Jung, Yunheung Paek, Gang-Ryung Uh	Experience with a retargetable compiler for a commercial network processor.	CASES	2002	DBLP DOI BibTeX RDF	non-orthogonal architecture, compiler, network processor
25	Thomas Rauber, Gudula Rünger	Library support for hierarchical multi-processor tasks.	SC	2002	DBLP DOI BibTeX RDF	hierarchical decomposition of processor sets, library support, mixed task and data parallelism, multilevel group SPMD, distributed memory, multiprocessor tasks
25	M. Anwarul Hasan, Amr G. Wassal	VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2m) Processor.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Galois (or finite) field processor, canonical (or polynomial) basis, triangular basis, cryptography, VLSI implementation, datapath
25	Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen	Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration.	HPCA	2000	DBLP DOI BibTeX RDF	directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA
25	Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra	Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications.	VLSI Design	2000	DBLP DOI BibTeX RDF	ATSC standard, picture processing, VLSI design, video processing, Digital television, HDTV, media processor
25	Andrew A. Chien, Jay H. Byun	Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor.	FCCM	1999	DBLP DOI BibTeX RDF	Multiprocess Protection, Process isolation, Machine Virtualization, Adaptive Computing, Reconfigurable Processor
25	Abhijit Jas, Nur A. Touba	Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip.	ICCD	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
25	You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung	Customization of a CISC Processor Core for Low-Power Applications.	ICCD	1999	DBLP DOI BibTeX RDF	CISC-processor, Complex-instruction, ROM-compile, Low-power-design, Microcode
25	Edgar T. Kalns, Lionel M. Ni	Processor Mapping Techniques Toward Efficient Data Redistribution.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	High Performance Fortran, data redistribution, Distributed-memory architectures, data-parallel programming, data decomposition, processor mapping
25	Goutam Debnath, Kathy Debnath, Roshan Fernando	The Pentium processor-90/100, microarchitecture and low power circuit design.	VLSI Design	1995	DBLP DOI BibTeX RDF	BIMOS integrated circuits, Pentium processor-90/100, low power circuit design, BiNMOS process, power consumption reduction, symmetric dual processing feature, multithreaded operating systems, 0.6 micron, 3.3 V, computer architecture, microarchitecture, integrated circuit design, microprocessor chips, 100 MHz
25	J. L. van den Berg, Onno J. Boxma	TheM/G/1 queue with processor sharing and its relation to a feedback queue.	Queueing Syst. Theory Appl.	1991	DBLP DOI BibTeX RDF	M/M/1 feedback queue, M/G/1 processor sharing queue, sojourn times
25	Maurizio Paganini	Nomadik®: A Mobile Multimedia Application Processor Platform.	ASP-DAC	2007	DBLP DOI BibTeX RDF	mobile multimedia application processor platform, Nomadik platform, industry standard host processor, low-power DSP, hardware accelerators
25	Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel	Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	64-bit Power Architecture, design dependency solution, digital thermal sensor, flexible IO, hardware content protection, high-performance latch, linear sensor, local clock buffer, multi-operating system, synergistic processor, real-time system, modularity, power management, Linux, multi-core, multi-threading, SOC, thermal management, design environment, CELL Processor, clock distribution, virtualization technology, SOI, correct-by-construction, re-use, design hierarchy
25	Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher	A low-power memory hierarchy for a fully programmable baseband processor.	WMPI	2004	DBLP DOI BibTeX RDF	baseband processor, multi-tasked processor, task interleaving, memory hierarchy, low-power memory
25	Sebastien Vagnier, Hassane Essafi, Alain Mérigot	A Configurable Processor Network for Document Management.	CAMP	2000	DBLP DOI BibTeX RDF	configurable processor network, European STRETCH project, imaged document, component extraction, configurable network, information retrieval, document management, configurable processor, content-based information retrieval
25	Andreas Svolos, Charalampos Konstantopoulos, Christos Kaklamanis	fficient Binary Morphological Algorithms on a Massively Parallel Processor.	IPDPS	2000	DBLP DOI BibTeX RDF	hypercube, mathematical morphology, dilation, massively parallel processor, erosion, associative processor
25	Ireneusz Karkowski, Henk Corporaal	Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining.	IEEE PACT	1997	DBLP DOI BibTeX RDF	heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops
25	Hidehiko Tanaka	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain
25	D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello	Micronets: a model for decentralising control in asynchronous processor architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency
25	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
25	Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito	SSM-MP: more scalability in shared-memory multi-processor.	ICCD	1995	DBLP DOI BibTeX RDF	SSM-MP, shared-memory multi-processor, cache refill latency, bus bottle neck problem, MTag, scalability, shared memory systems, cache coherency, memory architecture, multi-processor system
25	Rong Lin, Stephan Olariu	A simple array processor for binary prefix sums.	ASAP	1995	DBLP DOI BibTeX RDF	binary prefix sums, storage compaction, routing, computational complexity, parallel processing, VLSI, network routing, circuit CAD, array processor, binary sequence, special-purpose architecture, processor assignment, operating system design
25	Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura 0003, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi	Configurable multi-processor architecture and its processor element design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
25	Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl	A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.	DATE	2004	DBLP DOI BibTeX RDF
25	Oleg Maslennikov	Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units.	PPAM	2001	DBLP DOI BibTeX RDF
25	Dirk Fimmel, Renate Merker	Determination of the Processor Functionality in the Design of Processor Arrays.	ASAP	1997	DBLP DOI BibTeX RDF
24	Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic	MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm.	ICCAD	2008	DBLP DOI BibTeX RDF
24	Huiyang Zhou	Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window.	IEEE PACT	2005	DBLP DOI BibTeX RDF
24	Kenneth M. Wilson, Kunle Olukotun	High Bandwidth On-Chip Cache Design.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth
23	Arvind Easwaran, Insik Shin, Insup Lee 0001	Optimal virtual cluster-based multiprocessor scheduling.	Real Time Syst.	2009	DBLP DOI BibTeX RDF	Virtual processor clustering, Compositional schedulability analysis, Multiprocessor scheduling, Hierarchical scheduling
23	John Wei, Chris Rowen	Implementing low-power configurable processors: practical options and tradeoffs.	DAC	2005	DBLP DOI BibTeX RDF	PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power
23	Jason E. Fritts, Roger D. Chamberlain	Breaking the Memory Bottleneck with an Optical Data Path.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF	bandwidth bottleneck, processor-memory gap, performance evaluation, media processing, optical bus
23	Rudesindo Núñez-Queija	Queues with Equally Heavy Sojourn Time and Service Requirement Distributions.	Ann. Oper. Res.	2002	DBLP DOI BibTeX RDF	foreground-background processor sharing, queues with heavy tails, (intermediate) regular variation, telecommunications, processor sharing, shortest remaining processing time
23	Ken'ichirou Kimura, Hirofumi Amano, Akifumi Makinouchi	Dynamic Performance Optimization Mechanism for Parallel Object-Oriented Database Programming Languages.	IDEAS	2000	DBLP DOI BibTeX RDF	dynamic performance optimization, parallel object-oriented database programming languages, distributed-memory parallel processor, remote object referencing, biased distribution, object relocation, simulation tests, topology, parallel languages, performance degradation, inter-processor communication, load imbalance, object allocation
23	Jochen Kreuzinger, A. Schulz, Matthias Pfeffer, Theo Ungerer, Uwe Brinkschulte, C. Krakowski	Real-time scheduling on multithreaded processors.	RTCSA	2000	DBLP DOI BibTeX RDF	core processor, real-time events, interrupt service threads, interrupt service routines, zero-cycle context switching, fixed priority preemptive, least laxity first, embedded systems, real-time scheduling, processor scheduling, system-on-a-chip, multi-threading, earliest deadline first, multithreaded processors
23	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen	Tuning Compiler Optimizations for Simultaneous Multithreading.	MICRO	1997	DBLP DOI BibTeX RDF	cyclic algorithm, fine-grained sharing, inter-thread instruction-level parallelism, loop-iteration scheduling, memory system resources, software speculative execution, performance, parallel programs, parallel architecture, compiler optimizations, shared-memory multiprocessors, processor architecture, instructions, simultaneous multithreading, latency hiding, loop tiling, optimising compilers, inter-processor communication, cache size
23	Sungcheol Hong	Optimal server allocation for real time computing systems with bursty priority.	RTCSA	1995	DBLP DOI BibTeX RDF	bursty priority jobs, server allocation, bursty job arrival, high priority queue, processor pool, low priority queue, scheduling, real-time systems, response time, processor scheduling, file servers, real time computing systems, average waiting time