Search results for "PLL"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi	10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Haoran Li, Tailong Xu, Xi Meng, Jun Yin 0001, Rui Paulo Martins, Pui-In Mak	10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. AbdelRahman, Tianyu Wang 0006, Kyu-Sang Park, Pavan Kumar Hanumolu	7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino	10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada	10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino	10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin	10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Yunbo Huang, Yong Chen 0005, Zunsong Yang, Rui Paulo Martins, Pui-In Mak	7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang 0001	14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Byeong-Taek Moon, Hyun-Chul Park, Sang-Gug Lee 0001	10.8 A 281GHz, -1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference.	ISSCC	2024	DBLP DOI BibTeX RDF
13	Bin Hu, Heng Nian, Meng Li, Yuming Liao, Jun Yang, Hao Tong	Impedance Characteristic Analysis and Stability Improvement Method for DFIG System Within PLL Bandwidth Based on Different Reference Frames.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
13	Yuhang Chen, Xinbo Ruan, Zhiheng Lin, Yiran Yan, Yuying He	A Reconstructed Singular Return Ratio Matrix for Optimizing Design of the PLL in Grid-Connected Inverters.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
13	Ting Wu 0006, Xuan Wu, Shoudao Huang, Kaiyuan Lu, Hesong Cui	An Optimized PLL With Time Delay and Harmonic Suppression for Improved Position Estimation Accuracy of PMSM Based on Levenberg-Marquardt.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
13	Pengfei Hu 0002, Zheng Chen, Yanxue Yu, Daozhuo Jiang	On Transient Instability Mechanism of PLL-Based VSC Connected to a Weak Grid.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
13	Xianfu Lin, Ruoxue Yu, Jingrong Yu, He Wen	Constant-Coupling-Effect-Based PLL for Synchronization Stability Enhancement of Grid-Connected Converter Under Weak Grids.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
13	Leilei Guo, Han Xiao, Hailiang Zhao, Zhiyan Zhang, Changzhou Yu, Xiaoliang Yang, Hong Zhu	A Virtual-Flux State Observer-Based Inductance Identification Method for Model Predictive Control of Grid-Tied Inverters With a Finite Phase Angle Set-Based PLL.	IEEE Trans. Ind. Electron.	2023	DBLP DOI BibTeX RDF
13	Zhong Gao, Martin Fritz, Gerd Spalink, Robert Bogdan Staszewski, Masoud Babaie	A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Kyumin Kwon, Omar A. B. Abdelatty, David D. Wentzloff	PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	David Murphy, Dihang Yang, Hooman Darabi, Arya Behzad	A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie	A Cryo-CMOS PLL for Quantum Computing Applications.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie	A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi	A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher Dennis Hull, Steven Callender, Stefano Pellerano	A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Yu Zhao, Mahdi Forghani, Behzad Razavi	A 20-GHz PLL With 20.9-fs Random Jitter.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Yizhuo Wang, Jiahe Shi, Hao Xu 0005, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao 0001, Hao Min, Na Yan	Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi	A 56-GHz Fractional-N PLL With 110-fs Jitter.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
13	Mohammad Kazem Bakhshizadeh, Sujay Ghosh, Lukasz Kocewiak, Guangya Yang	Improved Reduced-Order Model for PLL Instability Investigations.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Pooya Taheri, Jalal Amini, Mehrdad Moallem	Improving Performance of Three-Phase MAF-PLL Under Asymmetrical DC-Offset Condition.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Dengke Xu, Meng Zhan	Transient Stability Analysis and Enhancement of PLL-VSC Considering State-Dependent Damping.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Benjamin Hoepfner, Ralf Vick	A Three-Phase Frequency-Fixed DSOGI-PLL With Low Computational Effort.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Saurabh Kumar, Yatendra Kumar Singh	A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Mariam Maurice, Mohamed Dessouky, Ashraf Salem	Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator.	IEEE Access	2023	DBLP DOI BibTeX RDF
13	Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins	A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
13	Fehmi Sevilmis, Hulusi Karaca, Hafiz Ahmed	High-Order Delayed Signal Cancellation-Based PLL Under Harmonically Distorted Grid Voltages.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
13	Mohsen Eskandari, Andrey V. Savkin	Robust PLL Synchronization Unit for Grid-Feeding Converters in Micro/Weak Grids.	IEEE Trans. Ind. Informatics	2023	DBLP DOI BibTeX RDF
13	Riyaz Ahmad, Gaurav Kumar Sharma, Dharmendar Boolchandani, Ashutosh Yadav	A Novel Wide Tuning Range Differential Ring Oscillator Application in Dynamically Stable and 1.17 $\upmu $s Lock Time CP-PLL Frequency Synthesizer.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
13	Hong-Yi Huang, Jen-Chieh Liu, Fu-Chien Tsai, Kun-Hua Lee, Kun-Yuan Chen	A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
13	Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu	A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins	A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim	A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
13	Mateus Bernardino Moreira, Francois Rivet, Magali De Matos, Hervé Lapuyade, Yann Deval	A (0.75-1.13) mW and (2.4-5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Junlin Zhong, Xiaofeng Yang 0004, Rui Paulo Martins, Yan Zhu 0001, Chi-Hang Chan	A 0.016mm2 Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Kyungmin Lee, Jaehong Jung, Seungjin Kim, Seunghyun Oh, Jongwoo Lee, Sung Min Park 0001	A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
13	Federico Cecati, Johanna Kristin Maria Becker, Sante Pugliese, Yihui Zuo, Marco Liserre, Mario Paolone	LTP Modeling and Analysis of Frequency Coupling in PLL-Synchronized Converters for Harmonic Power Flow Studies.	IEEE Trans. Smart Grid	2023	DBLP DOI BibTeX RDF
13	Priti Gupta, Sanjay Kumar Jana	Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
13	Jinwei Li, Bing Sun, Jiawei Huang, Hudong Chang, Rui Jia, Honggang Liu	A 7.6-12.3 GHz wide-band PLL with an ultra low reference spur -81.1 dBc in 0.13 μm CMOS technology.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
13	Yuyang Liu, Zhaohui Wu 0004, Bin Li 0007, Yanqi Zheng, Zhijian Chen	An optimization method for PLL-based charge control SIMO Buck DC-DC.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
13	Mohammad Oveisi, Seyedali Hosseinisangchi, Payam Heydari	A Study of Out-of-Band Emission in Digital Transmitters Due to PLL Phase Noise, Circuit Non-Linearity, and Bandwidth Limitation.	IEEE Open J. Circuits Syst.	2023	DBLP DOI BibTeX RDF
13	Jin Wu, Minwei Hu, Xudong Wu, Yang Zuo, Chenggong Wan, Lixia Zheng, Weifeng Sun	A low jitter fractional PLL with offset current charge pump.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Ding Qiu, Xiangjian Kong, Mingchao Jian, Jiwei Zheng, Chunbing Guo	A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Chao Yang, Sheng Wang, Xiaoming Liu 0008, Jing Jin 0005, Jianjun Zhou	A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Zirui Jin, Ang Hu, Xiaoyu Shan, Chengcheng Zhang, Jinsong Cui, Jianming Lei, Dongsheng Liu	A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Huang-Hong Yang, Hua Wu, An-An Zhang, Xian-Guo Cao	A high efficiency buck converter based on PLL for frequency stabilization.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
13	Xiaoling Xiong, Bochen Luo, Longcan Li, Ziming Sun, Frede Blaabjerg	Impedance Reshaping Method of DFIG System Based on Compensating Rotor Current Dynamic to Eliminate PLL Influence.	CoRR	2023	DBLP DOI BibTeX RDF
13	Viktor Fischer, Florent Bernard, Nathalie Bochard, Quentin Dallison, Maciej Skórski	Enhancing Quality and Security of the PLL-TRNG.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2023	DBLP DOI BibTeX RDF
13	Sangyeop Lee, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima	A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC.	IEICE Trans. Electron.	2023	DBLP DOI BibTeX RDF
13	Yantian Xu, Zhiyu Wang, Jiarui Liu 0001, Hua Chen, Faxin Yu	Multi-chip phase synchronization circuit of fractional-N PLL.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
13	Zhichao Zhang, Wenjie Zheng, Xinlin Xia, Yanjie Wang	A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
13	Mehmet Emin Kisa, Burak Kelleci, Mustafa Berke Yelten	A 560 MHz Frequency Multiplier Employing a Novel Pseudo-Differential Charge-Pump PLL.	PRIME	2023	DBLP DOI BibTeX RDF
13	Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang	Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL.	MWSCAS	2023	DBLP DOI BibTeX RDF
13	Vladimir Veselý, Calvin Yoji Lee, Tejasvi Anand, Un-Ku Moon	PLL-SAR: A New High-Speed Analog to Digital Converter Architecture.	MWSCAS	2023	DBLP DOI BibTeX RDF
13	Wenqiang Huang, Yanshu Guo, Yaoyu Li, Zhihua Wang 0001, Yuanjin Zheng, Tiefu Li, Hanjun Jiang, Wen Jia	A 1-1.7 GHz Cryogenic Fractional-N CP-PLL for Quantum Computing Applications.	MWSCAS	2023	DBLP DOI BibTeX RDF
13	Marco Gonzalez, David Bol	Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW.	DATE	2023	DBLP DOI BibTeX RDF
13	Zetao Feng, Yan Xia, Renzhao Chen, Yili Yang, Jie Wu, Huizhu Li	Research on the Performance of DDSRF-PLL under Unbalanced Grid Voltage.	SAFEPROCESS	2023	DBLP DOI BibTeX RDF
13	Nikolay V. Kuznetsov, Mikhail Y. Lobachev, Marat V. Yuldashev, Renat V. Yuldashev	Bifurcation Analysis of the Boundary of Global Stability of Type 1 PLL.	ECC	2023	DBLP BibTeX RDF
13	Jae Hyung Jung, Kang Yoon Lee	Fast Locking Dual Band PLL for NB-IoT with QPSK Modulation.	ICUFN	2023	DBLP DOI BibTeX RDF
13	Sumit Kumar	Stability Limited PLL bandwidth Derivation using Impulse Invariance Method.	ICECS	2023	DBLP DOI BibTeX RDF
13	Wenqiang Huang, Yanshu Guo, Yaoyu Li, Zhihua Wang 0001, Yuanjin Zheng, Tiefu Li, Wen Jia, Hanjun Jiang	A 400uW 3.6GHz-4.6GHz Low Power Cryogenic CP-PLL with Transformer-Based VCO in 28nm Bulk CMOS.	ICTA	2023	DBLP DOI BibTeX RDF
13	Haoyuan Gao, Hao Xu, Xinyi Lin, Yan Liu, Zhidong Tang, Xufeng Kou, Xingyu Zhang, Tetsuya Iizuka, Na Yan	INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications.	ICTA	2023	DBLP DOI BibTeX RDF
13	Hongzhuo Liu, Wei Deng 0001, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi	A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter.	ESSCIRC	2023	DBLP DOI BibTeX RDF
13	Xinyu Shen, Zhao Zhang 0004, Guike Li, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.	ESSCIRC	2023	DBLP DOI BibTeX RDF
13	Jie Dong, Binxing Li, Hua Yang, Guoqiang Zhang, Gaolin Wang, Dianguo Xu 0001	Estimated Position Error Suppression Using PLL with Speed Compensation for Sensorless IPMSM Drives.	IECON	2023	DBLP DOI BibTeX RDF
13	Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka	A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
13	Angxiao Yan, Wei Deng 0001, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi	An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
13	Jaehong Jung, Kyungmin Lee, Gunwoo Kong, Baekmin Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee	A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
13	Naiara Goñi, Javier Marcos, Miguel García, Alberto García, Andoni Urtasun, Luis Marroyo	High-Fidelity Averaged Model of Grid-Following Inverter for Stability Analysis Considering the PLL Influence.	ISIE	2023	DBLP DOI BibTeX RDF
13	Raghav Bansal, Shouri Chatterjee	A 40 nA, 84% Efficient, PLL-based Rectifier-Less Power Switching Converter for Low-Voltage Piezoelectric Energy Harvesting.	NEWCAS	2023	DBLP DOI BibTeX RDF
13	Frank Herzel, Corrado Carta, Gunter Fischer	Random and Static Phase Errors in a PLL Array for Millimeter-Wave Frequency Generation.	NEWCAS	2023	DBLP DOI BibTeX RDF
13	Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada	A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference.	CICC	2023	DBLP DOI BibTeX RDF
13	Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin	A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL.	CICC	2023	DBLP DOI BibTeX RDF
13	Liqun Feng, Woogeun Rhee, Zhihua Wang 0001	A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter.	CICC	2023	DBLP DOI BibTeX RDF
13	Shiwei Zhang, Wei Deng 0001, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi	A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.	CICC	2023	DBLP DOI BibTeX RDF
13	Wen Chen, Yiyang Shu, Xun Luo	A 21.8-41.6GHz Fractional-N Sub-Sampling PLL with Dividerless Unequal-REF-Delay Frequency-Locked Loop Achieving -246.9dB FoMj and -270.3dB FoMj,N.	CICC	2023	DBLP DOI BibTeX RDF
13	Xinlin Geng, Zonglin Ye, Yao Xiao, Oian Xie, Zheng Wang 0050	A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels.	CICC	2023	DBLP DOI BibTeX RDF
13	Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi	A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Zhao Zhang 0004, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu 0021, Yong Chen, Nanjian Wu, Liyuan Liu	A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Byeong-Taek Moon, Sang-Gug Lee 0001, Jaehyouk Choi	A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Chanwoong Hwang, Hangi Park, Jaehyouk Choi	A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Yumeng Yang, Wei Deng 0001, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang 0001, Baoyong Chi	A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx	A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi	A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada	A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher D. Hull, Steven Callender, Stefano Pellerano	A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Xuhong Lil, Jianghu Hong, Chunqi Shi, Leilei Huang, Boxiao Liu, Hao Deng 0003, Jinghong Chen, Runxi Zhang	A 3.84 GHz 32 fs RMS Jitter Over-Sampling PLL with High-Gain Cross-Switching Phase Detector.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Shengyuan Zhou, Ziyao Xia, Chao Yang, Xiaoming Liu 0008, Sheng Wang, Jing Jin 0005	Fast locking Sampling PLL Using Phase Error Eliminator.	ASICON	2023	DBLP DOI BibTeX RDF
13	Edwin C. Cuizon, Marven A. Yuson, Aileen B. Caberos, Nieva M. Mapula, Harreez M. Villaruz	Design of Charge Pump for Low Power, Wide Range PLL in 65nm CMOS Technology.	ISCIT	2023	DBLP DOI BibTeX RDF