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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2846 occurrences of 1432 keywords
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Results
Found 14080 publication records. Showing 14080 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
29 | Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham |
A unified approach for fault simulation of linear mixed-signal circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(1-2), pp. 29-41, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
arithmetic distance, testing, fault simulation, mixed-signal |
29 | O. Vermesan |
A Modular VLSI Architecture for Neural Networks Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: From Natural to Artificial Neural Computation, International Workshop on Artificial Neural Networks, IWANN '95, Malaga-Torremolinos, Spain, June 7-9, 1995, Proceedings, pp. 794-799, 1995, Springer, 3-540-59497-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Mar Hershenson |
Design platform for electrical and physical co-design of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 45, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
design, analog, co-design |
28 | Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi |
Performance assessment of analog circuits with carbon nanotube FET (CNFET). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 163-166, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog, circuits |
28 | Bradley N. Bond, Luca Daniel |
Automated compact dynamical modeling: an enabling tool for analog designers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 415-420, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parameterized modeling, semidefinite programming, model reduction, analog design, compact modeling |
28 | Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu |
Behavior-level yield enhancement approach for large-scaled analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 903-908, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
process variation, analog circuits, yield enhancement |
28 | Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela Araújo Cunha |
Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS multipliers, distortion, analog multipliers |
28 | Wimol San-Um, Masayoshi Tachibana |
Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test |
28 | Yigang He, Wenji Zhu |
Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks and Multi-Space Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (3) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part III, pp. 714-723, 2009, Springer, 978-3-642-01512-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Bilinear Transformation, Space Transformation, Neural Network, Fault Diagnosis, Analog Circuits |
28 | Pedro Sousa, Carla Duarte, Nuno Horta |
FUGA: a fuzzy-genetic analog circuit optimization kernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2009, Proceedings, Montreal, Québec, Canada, July 8-12, 2009, pp. 1779-1780, 2009, ACM, 978-1-60558-325-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
genetic algorithms, optimization, CAD, analog circuit, fuzzy model |
28 | Masashi Kawaguchi, Shoji Suzuki, Takashi Jimbo, Naohiro Ishii |
Speed Flexibility Biomedical Vision Model Using Analog Electronic Circuits and VLSI Layout Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based and Intelligent Information and Engineering Systems, 13th International Conference, KES 2009, Santiago, Chile, September 28-30, 2009, Proceedings, Part II, pp. 697-704, 2009, Springer, 978-3-642-04591-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Biomedical Vision System, Neural Network, Motion Detection, Analog Circuits |
28 | Gabriel Oltean, Sorin Hintea, Emilia Sipos |
A Genetic Algorithm-Based Multiobjective Optimization for Analog Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based and Intelligent Information and Engineering Systems, 13th International Conference, KES 2009, Santiago, Chile, September 28-30, 2009, Proceedings, Part II, pp. 506-514, 2009, Springer, 978-3-642-04591-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Pareto ranking, genetic algorithm, multiobjective optimization, Pareto front, analog circuit design |
28 | Tomonori Shirotori, Yuko Osana |
Improved Kohonen Feature Map Associative Memory with Area Representation for Sequential Analog Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (1) ![In: Artificial Neural Networks - ICANN 2009, 19th International Conference, Limassol, Cyprus, September 14-17, 2009, Proceedings, Part I, pp. 505-514, 2009, Springer, 978-3-642-04273-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Kohonen Feature Map (Self-Organizing Map), Successive Learning, Sequential Analog Pattern, Associative Memory |
28 | Yalin Evren Sagduyu, Dongning Guo, Randall Berry |
Throughput and stability of digital and analog network coding for wireless networks with single and multiple relays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WICON ![In: Proceedings of the 4th Annual International Conference on Wireless Internet, WICON 2008, Maui, Hawaii, USA, November 17-19, 2008, pp. 68, 2008, ICST, 978-963-9799-36-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
analog network coding, digital network coding, queue stability, stable throughput region, throughput optimal control |
28 | Masashi Kawaguchi, Takashi Jimbo, Naohiro Ishii |
Analog VLSI Layout Design and the Circuit Board Manufacturing of Advanced Image Processing for Artificial Vision Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 12th International Conference, KES 2008, Zagreb, Croatia, September 3-5, 2008, Proceedings, Part II, pp. 895-902, 2008, Springer, 978-3-540-85564-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Biomedical Vision System, Neural Network, Motion Detection, Analog Circuits |
28 | K. R. Anne, S. K. Bhagavatula, Jean Chamberlain Chedjou, Kyandoghere Kyamakya |
Self-organized supply chain networks: theory in practice and an analog simulation based approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autonomics ![In: Proceedings of the 2nd International Conference on Autonomic Computing and Communication Systems, Autonomics 2008, September 23-25, 2008, Turin, Italy, pp. 30, 2008, ICST, 978-963-9799-34-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
adaptive supply chains, analog simulation, self-organized supply chains, supply chain optimization |
28 | Tony Poitschke, Markus Ablaßmeier, Gerhard Rigoll, Stanislavs Bardins, Stefan Kohlbecher, Erich Schneider |
Contact-analog information representation in an automotive head-up display. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETRA ![In: Proceedings of the Eye Tracking Research & Application Symposium, ETRA 2008, Savannah, Georgia, USA, March 26-28, 2008, pp. 119-122, 2008, ACM, 978-1-59593-982-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
HUD, contact-analog, eye tracking, calibration, automotive, head-up display |
28 | David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
Symbolic Model Checking of Analog/Mixed-Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 316-323, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
analog/mixed-signal circuits, Boolean based symbolic model checking algorithm, VHDL-AMS description, labeled hybrid Petri nets, Boolean signals, temporal logic formulas, timed CTL, Boolean variables, Boolean function, binary decision diagram, hardware description language |
28 | Fernando da Rocha Paixão Cortes, Sergio Bampi |
A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 271-275, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RF front-end, VGA, analog/RF design, frequency translation, mixer |
28 | Yukiya Miura |
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 411-423, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MOS transistors, operation-region model, X-Y zoning method, fault diagnosis, analog circuits |
28 | Fernando De Bernardinis, Pierluigi Nuzzo 0001, Alberto L. Sangiovanni-Vincentelli |
Robust system level design with analog platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 334-341, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog platforms, robust hierarchical design, system-level design |
28 | Christopher Labrecque |
Near-term industrial perspective of analog CAD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 456-457, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
computer-aided design, analog, integrated circuits, mixed-signal |
28 | Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu |
Analog placement with symmetry and other placement constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 349-354, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
symmetry constraints, placement, analog circuits, sequence-pair |
28 | Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi |
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 342-348, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog/RF integrated circuits, layout automation, layout symmetry, design reuse, parasitics |
28 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra |
A formal approach for high level synthesis of linear analog systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 345-348, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
L2 sensitivity, analog high level synthesis, linear systems, architecture exploration, state space model |
28 | Maria José Pereira Dantas, Leonardo da C. Brito, Paulo Henrique Portela de Carvalho |
Multi-objective Memetic Algorithm Applied to the Automated Synthesis of Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBERAMIA-SBIA ![In: Advances in Artificial Intelligence - IBERAMIA-SBIA 2006, 2nd International Joint Conference, 10th Ibero-American Conference on AI, 18th Brazilian AI Symposium, Ribeirão Preto, Brazil, October 23-27, 2006, Proceedings, pp. 258-267, 2006, Springer, 3-540-45462-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-objective memetic algorithm, 2D representation, analog circuit, building-blocks, automated synthesis |
28 | Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein |
Chameleon ART: a non-optimization based analog design migration framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 885-888, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog reuse, design extraction, layout compaction, layout retargeting, circuit sizing |
28 | Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell |
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 135-146, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPAA test, Oscillation Test Strategy (OTS), Built-In Self Test (BIST), analog testing |
28 | Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio |
An On-Chip Spectrum Analyzer for Analog Built-In Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(3), pp. 205-219, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analog IC test, built-in testing, frequency response, switched-capacitor circuits |
28 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi |
Template-driven parasitic-aware optimization of analog integrated circuit layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 644-647, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analog layout automation, optimization, sensitivity, parasitics |
28 | Chun-Lung Hsu |
Control and Observation Structure for Analog Circuits with Current Test Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 39-44, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
current store cell (CSC), controllability, observability, analog circuit, current-mode |
28 | Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski |
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 11-23, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
analog test generation, fault modeling, fault simulation, catastrophic faults, supply current monitoring |
28 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 704-705, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Analog Filer, Trim Bit, Dynamic Supply Current (IDD), Wavelet Transform |
28 | Xin Li 0001, Yang Xu 0017, Peng Li 0001, Padmini Gopalakrishnan, Lawrence T. Pileggi |
A frequency relaxation approach for analog/RF system-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 842-847, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
analog/RF circuits, system-level simulation |
28 | Haibo Wang 0005, Sarma B. K. Vrudhula |
Behavioral synthesis of field programmable analog array circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 563-604, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Programmable circuits, analog synthesis |
28 | Mike W. T. Wong, K. Y. Ko, Yim-Shu Lee |
Analog and Mixed-Signal IP Cores Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 3-7, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
mixed-signal design, analog circuit testing, SOCs |
28 | Jens Lienig, Goeran Jerke, Thorsten Adler |
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 372-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
wire width, wire planning, current-driven routing, Design methodology, electromigration, detailed routing, current density, analog circuit design |
28 | Suresh Seshadri, Jacob A. Abraham |
Frequency Response Verification of Analog Circuits Using Global Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(5), pp. 395-408, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modeling, verification, global optimization, analog circuits, formal techniques, parameter variation, frequency response |
28 | Farzan Aminian, Mehran Aminian |
Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(6), pp. 471-481, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
electronic circuits, neural networks, fault diagnosis, wavelet transform, Fourier transform, analog circuits, nonlinear circuits |
28 | Eduardo J. Peralías, Adoración Rueda, José Luis Huertas |
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(5), pp. 373-383, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
mixed-signal IC test, testable ADC, BIST, design for test, pipelined analog to digital converters |
28 | Abdelhakim Khouas, Anne Derieux |
Fault Simulation for Analog Circuits Under Parameter Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(3), pp. 269-278, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
test optimisation, fault simulation, analog testing |
28 | Jun-Weir Lin, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
Fault diagnosis for linear analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 25-30, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
discrete signal flow graph, equivalent faults, fault diagnosis, fault diagnosis, signal flow graphs, analogue circuits, linear analog circuits |
28 | Paolo Migliavacca |
Faster Time-to-Market, Lower Cost of Development and Test for Standard Analog IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 155-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Bipolar array, standard analog IC, time-to-market, Voltage Reference |
28 | Mohamed Dessouky, Marie-Minerve Louërat |
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 291-298, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Analog layout, layout generation |
28 | Abdelhakim Khouas, Mohamed Dessouky, Anne Derieux |
Optimized Statistical Analog Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 227-232, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Fault Simulation, Analog Testing, Statistical Simulation |
28 | Bertram Emil Shi |
Real-Time Gabor-Type Filtering Using Analog Focal Plane Image Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: 1999 Conference on Computer Vision and Pattern Recognition (CVPR '99), 23-25 June 1999, Ft. Collins, CO, USA, pp. 1507-1513, 1999, IEEE Computer Society, 0-7695-0149-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
oriented filters, image fixation, analog processing circuits, mobile robots, scale-space, image sensors, steerable filters |
28 | Bruno Crespi, Alex Cozzi, Luigi Raffo, Silvio P. Sabatini |
Analog computation for phase-based disparity estimation: continuous and discrete models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Vis. Appl. ![In: Mach. Vis. Appl. 11(2), pp. 83-95, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Phase-based technique, VLSI, Differential equations, Disparity, Analog computation |
28 | Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb |
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 822-827, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
analog and mixed-signal test design, IDD spectral measurements, test decision criteria, yield coverage, fault modeling, fault coverage, discrimination analysis, measurement noise |
28 | Prakash Gopalakrishnan, Vinita Vasudevan |
A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 249-252, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
routing, layout, analog circuits |
28 | Pramodchandran N. Variyam, Abhijit Chatterjee |
Test generation for comprehensive testing of linear analog circuits using transient response sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 382-385, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Implicit functional testing, Transient testing, Linear Analog Circuits |
28 | Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen |
Automated test pattern generation for analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 296-301, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
automated test pattern generation, generated fault list, optimal test signals, statistical fluctuations, statistical test criterion, ATPG algorithm, analogue integrated circuits, analog integrated circuits |
28 | Eduardo J. Peralías, Adoración Rueda, José L. Huertas |
A DFT Technique for Analog-to-Digital Converters with digital correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 302-307, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Design for Testability of Data Converters, Analog and Mixed Signal Test |
28 | Karim Arabi, Bozena Kaminska |
Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 166-171, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits |
28 | Walter M. Lindermeir |
Design of robust test criteria in analog testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 604-611, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
measurement selection, sample generation, analog testing, measurement noise |
28 | Karim Arabi, Bozena Kaminska |
Oscillation-test strategy for analog and mixed-signal integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 476-482, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs |
28 | Eric Felt, Alberto L. Sangiovanni-Vincentelli |
Optimization of analog IC test structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 48-53, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
integrated circuit measurement, analog IC test structures, circuit parameters, statistical analysis, integrated circuit testing, accuracy, circuit optimisation, design of experiments, design of experiments, analogue integrated circuits, statistical techniques, network parameters, integrated circuit noise, measurement noise |
28 | A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri |
A micropower analog hearing aid on low voltage CMOS digital process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 85-89, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids |
28 | Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi |
Low-cost DC built-in self-test of linear analog circuits using checksums. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 230-233, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes |
28 | Eugenia Penn, Leo N. Schelovanov |
A new approach for modeling and optimization of analog systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 28-32, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
recurrent procedure, complex analog systems, diverse systems, computer-aided optimization design, system optimisation, modelling, modeling, CAD, optimisation, digital simulation, digital simulation |
28 | Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana |
CODAC-a characterization system for digital and analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 193-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CODAC, characterization system, electrical simulator, procedural interface, customized analysis functions, parallel processing, circuit analysis computing, Monte Carlo methods, circuit CAD, SPICE, SPICE, analog circuits, digital circuits, CAD tool, digital integrated circuits, analogue integrated circuits, circuit analysis, Monte Carlo analysis |
27 | Ender Yilmaz, Günhan Dündar |
Analog Layout Generator for CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1), pp. 32-45, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Sha Yao, Mikael Skoglund |
Hybrid Digital-Analog Relaying for Cooperative Transmission Over Slow Fading Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 55(3), pp. 944-951, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín |
Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 26-27, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann |
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), pp. 2209-2222, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Angelo Ciccazzo, Piero Conca, Giuseppe Nicosia, Giovanni Stracquadanio |
An Advanced Clonal Selection Algorithm with Ad-Hoc Network-Based Hypermutation Operators for Synthesis of Topology and Sizing of Analog Electrical Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARIS ![In: Artificial Immune Systems, 7th International Conference, ICARIS 2008, Phuket, Thailand, August 10-13, 2008. Proceedings, pp. 60-70, 2008, Springer, 978-3-540-85071-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Sheng-Yu Peng, Yu Tsao 0001, Paul E. Hasler, David V. Anderson |
A programmable analog radial-basis-function based classifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 1425-1428, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Joachim Becker, Fabian Henrici, Stanis Trendelenburg, Yiannos Manoli |
A rapid prototyping environment for high-speed reconfigurable analog signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-4, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Luiz Carlos Gouveia, Thomas Jacob Koickal, Alister Hamilton |
An asynchronous spike event coding scheme for programmable analog arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1364-1367, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Sri Chandra |
Driving Analog Mixed Signal Verification through Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 731, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Joaquin Sitte, Liang Zhang, Ulrich Rückert 0001 |
Characterization of Analog Local Cluster Neural Network Hardware for Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 18(4), pp. 1242-1253, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Lauri Koskinen, Joona Marku, Ari Paasio, Kari Halonen |
Architecture for Analog Variable Block-Size Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (2) ![In: Proceedings of the International Conference on Image Processing, ICIP 2007, September 16-19, 2007, San Antonio, Texas, USA, pp. 493-496, 2007, IEEE, 978-1-4244-1436-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Sheng-Yu Peng, Paul E. Hasler, David V. Anderson |
An analog programmable multi-dimensional radial basis function based classifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 13-18, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson |
Placement for large-scale floating-gate field-programable analog arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 906-910, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Mikael Skoglund, Nam Phamdo, Fady Alajaji |
Hybrid Digital-Analog Source-Channel Coding for Bandwidth Compression/Expansion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 52(8), pp. 3757-3763, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa |
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(6), pp. 1143, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa |
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(11), pp. 1973-1982, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani |
Adaptive Porting of Analog IPs with Reusable Conservative Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 18-23, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Fujita Tomohiro, Iiduka Osamu |
Analog circuit sizing with dynamic search window. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Shantanu Chakrabartty |
CMOS analog iterative decoders using margin propagation circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Josep Soler Garrido, Robert J. Piechocki, Koushik Maharatna, Darren P. McNamara |
MIMO detection in analog VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Varun Aggarwal, Meng Mao, Una-May O'Reilly |
A Self-Tuning Analog Proportional-Integral-Derivative (PID) Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 12-19, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Kaiping Zeng, Sorin A. Huss |
Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 225-230, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Rodrigo Cardim, Marcelo C. M. Teixeira, Edvaldo Assunção, Nobuo Oki, Aparecido Augusto de Carvalho, Márcio R. Covacic |
Hardware Implementation of an Analog Neural Nonderivative Optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (3) ![In: Neural Information Processing, 13th International Conference, ICONIP 2006, Hong Kong, China, October 3-6, 2006, Proceedings, Part III, pp. 1131-1140, 2006, Springer, 3-540-46484-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Michael Unser |
Cardinal exponential splines: part II - think analog, act digital. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 53(4), pp. 1439-1449, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Jianyun Hu, Hao Min |
A Low Power and High Performance Analog Front End for Passive RFID Transponder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AutoID ![In: Proceedings of the Fourth IEEE Workshop on Automatic Identification Advanced Technologies (AutoID 2005), 16-18 October 2005, Buffalo, NY, USA, pp. 199-204, 2005, IEEE Computer Society, 0-7695-2475-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Hongrak Son, Hyunjung Kim, Hyongsuk Kim, Kil To Chong |
Feasibility of the Circularly Connected Analog CNN Cell Array-Based Viterbi Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 8th International Conference, PaCT 2005, Krasnoyarsk, Russia, September 5-9, 2005, Proceedings, pp. 151-158, 2005, Springer, 3-540-28126-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Chris Winstead |
Analog Soft Decoding for Multi-Level Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada, pp. 132-137, 2005, IEEE Computer Society, 0-7695-2336-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Dayu Yang, Foster F. Dai, Charles E. Stroud |
Built-in self-test for automatic analog frequency response measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2208-2211, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Ravi Chawla, Christopher M. Twigg, Paul E. Hasler |
An analog modulator/demodulator using a programmable arbitrary waveform generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 6106-6109, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli |
A Methodology for System-Level Analog Design Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 676-677, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski |
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 105-110, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
system-on-chip, BIST, power aware, mixed-signal test |
27 | Chin-Long Wey, Mohammad Athar Khalil, Jim Liu, Gregory Wierzba |
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 322-327, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
IC reliability |
27 | José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Ricardo Tanscheit, Marley M. B. R. Vellasco, Marco Aurélio Cavalcanti Pacheco |
Towards Evolvable Analog Artificial Neural Networks Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 24-26 June 2004, Seattle, WA, USA, pp. 46-, 2004, IEEE Computer Society, 0-7695-2145-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, Martin Trefzer |
Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 24-26 June 2004, Seattle, WA, USA, pp. 18-25, 2004, IEEE Computer Society, 0-7695-2145-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Junwei Hou, Abhijit Chatterjee |
Concurrent transient fault simulation for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10), pp. 1385-1398, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Wallace B. Leigh |
Simplifying Analog CMOS Design for Undergraduates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 156-, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Alain Vachoux, Christoph Grimm 0001, Karsten Einwich |
Analog and mixed signal modelling with SystemC-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 914-917, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Yuan-Pei Lin, See-May Phoong |
Analog representation and digital implementation of OFDM systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 9-12, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu |
A digital background calibration technique for pipelined analog-to-digital converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 881-884, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Marco S. Dragic, Martin Margala |
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 124-131, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
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