Search results for "analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham	A unified approach for fault simulation of linear mixed-signal circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	arithmetic distance, testing, fault simulation, mixed-signal
29	O. Vermesan	A Modular VLSI Architecture for Neural Networks Implementation.	IWANN	1995	DBLP DOI BibTeX RDF
28	Mar Hershenson	Design platform for electrical and physical co-design of analog circuits.	ISPD	2010	DBLP DOI BibTeX RDF	design, analog, co-design
28	Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi	Performance assessment of analog circuits with carbon nanotube FET (CNFET).	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	analog, circuits
28	Bradley N. Bond, Luca Daniel	Automated compact dynamical modeling: an enabling tool for analog designers.	DAC	2010	DBLP DOI BibTeX RDF	parameterized modeling, semidefinite programming, model reduction, analog design, compact modeling
28	Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu	Behavior-level yield enhancement approach for large-scaled analog circuits.	DAC	2010	DBLP DOI BibTeX RDF	process variation, analog circuits, yield enhancement
28	Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela Araújo Cunha	Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS multipliers, distortion, analog multipliers
28	Wimol San-Um, Masayoshi Tachibana	Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test
28	Yigang He, Wenji Zhu	Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks and Multi-Space Transformations.	ISNN (3)	2009	DBLP DOI BibTeX RDF	Bilinear Transformation, Space Transformation, Neural Network, Fault Diagnosis, Analog Circuits
28	Pedro Sousa, Carla Duarte, Nuno Horta	FUGA: a fuzzy-genetic analog circuit optimization kernel.	GECCO	2009	DBLP DOI BibTeX RDF	genetic algorithms, optimization, CAD, analog circuit, fuzzy model
28	Masashi Kawaguchi, Shoji Suzuki, Takashi Jimbo, Naohiro Ishii	Speed Flexibility Biomedical Vision Model Using Analog Electronic Circuits and VLSI Layout Design.	KES (2)	2009	DBLP DOI BibTeX RDF	Biomedical Vision System, Neural Network, Motion Detection, Analog Circuits
28	Gabriel Oltean, Sorin Hintea, Emilia Sipos	A Genetic Algorithm-Based Multiobjective Optimization for Analog Circuit Design.	KES (2)	2009	DBLP DOI BibTeX RDF	Pareto ranking, genetic algorithm, multiobjective optimization, Pareto front, analog circuit design
28	Tomonori Shirotori, Yuko Osana	Improved Kohonen Feature Map Associative Memory with Area Representation for Sequential Analog Patterns.	ICANN (1)	2009	DBLP DOI BibTeX RDF	Kohonen Feature Map (Self-Organizing Map), Successive Learning, Sequential Analog Pattern, Associative Memory
28	Yalin Evren Sagduyu, Dongning Guo, Randall Berry	Throughput and stability of digital and analog network coding for wireless networks with single and multiple relays.	WICON	2008	DBLP DOI BibTeX RDF	analog network coding, digital network coding, queue stability, stable throughput region, throughput optimal control
28	Masashi Kawaguchi, Takashi Jimbo, Naohiro Ishii	Analog VLSI Layout Design and the Circuit Board Manufacturing of Advanced Image Processing for Artificial Vision Model.	KES (2)	2008	DBLP DOI BibTeX RDF	Biomedical Vision System, Neural Network, Motion Detection, Analog Circuits
28	K. R. Anne, S. K. Bhagavatula, Jean Chamberlain Chedjou, Kyandoghere Kyamakya	Self-organized supply chain networks: theory in practice and an analog simulation based approach.	Autonomics	2008	DBLP DOI BibTeX RDF	adaptive supply chains, analog simulation, self-organized supply chains, supply chain optimization
28	Tony Poitschke, Markus Ablaßmeier, Gerhard Rigoll, Stanislavs Bardins, Stefan Kohlbecher, Erich Schneider	Contact-analog information representation in an automotive head-up display.	ETRA	2008	DBLP DOI BibTeX RDF	HUD, contact-analog, eye tracking, calibration, automotive, head-up display
28	David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda	Symbolic Model Checking of Analog/Mixed-Signal Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	analog/mixed-signal circuits, Boolean based symbolic model checking algorithm, VHDL-AMS description, labeled hybrid Petri nets, Boolean signals, temporal logic formulas, timed CTL, Boolean variables, Boolean function, binary decision diagram, hardware description language
28	Fernando da Rocha Paixão Cortes, Sergio Bampi	A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface.	SBCCI	2007	DBLP DOI BibTeX RDF	RF front-end, VGA, analog/RF design, frequency translation, mixer
28	Yukiya Miura	Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MOS transistors, operation-region model, X-Y zoning method, fault diagnosis, analog circuits
28	Fernando De Bernardinis, Pierluigi Nuzzo 0001, Alberto L. Sangiovanni-Vincentelli	Robust system level design with analog platforms.	ICCAD	2006	DBLP DOI BibTeX RDF	analog platforms, robust hierarchical design, system-level design
28	Christopher Labrecque	Near-term industrial perspective of analog CAD.	ICCAD	2006	DBLP DOI BibTeX RDF	computer-aided design, analog, integrated circuits, mixed-signal
28	Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu	Analog placement with symmetry and other placement constraints.	ICCAD	2006	DBLP DOI BibTeX RDF	symmetry constraints, placement, analog circuits, sequence-pair
28	Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi	Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.	ICCAD	2006	DBLP DOI BibTeX RDF	analog/RF integrated circuits, layout automation, layout symmetry, design reuse, parasitics
28	Soumya Pandit, Chittaranjan A. Mandal, Amit Patra	A formal approach for high level synthesis of linear analog systems.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	L2 sensitivity, analog high level synthesis, linear systems, architecture exploration, state space model
28	Maria José Pereira Dantas, Leonardo da C. Brito, Paulo Henrique Portela de Carvalho	Multi-objective Memetic Algorithm Applied to the Automated Synthesis of Analog Circuits.	IBERAMIA-SBIA	2006	DBLP DOI BibTeX RDF	multi-objective memetic algorithm, 2D representation, analog circuit, building-blocks, automated synthesis
28	Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein	Chameleon ART: a non-optimization based analog design migration framework.	DAC	2006	DBLP DOI BibTeX RDF	analog reuse, design extraction, layout compaction, layout retargeting, circuit sizing
28	Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell	Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	FPAA test, Oscillation Test Strategy (OTS), Built-In Self Test (BIST), analog testing
28	Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio	An On-Chip Spectrum Analyzer for Analog Built-In Testing.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	analog IC test, built-in testing, frequency response, switched-capacitor circuits
28	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Template-driven parasitic-aware optimization of analog integrated circuit layouts.	DAC	2005	DBLP DOI BibTeX RDF	analog layout automation, optimization, sensitivity, parasitics
28	Chun-Lung Hsu	Control and Observation Structure for Analog Circuits with Current Test Data.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	current store cell (CSC), controllability, observability, analog circuit, current-mode
28	Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski	Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	analog test generation, fault modeling, fault simulation, catastrophic faults, supply current monitoring
28	Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001	Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.	DATE	2004	DBLP DOI BibTeX RDF	Analog Filer, Trim Bit, Dynamic Supply Current (IDD), Wavelet Transform
28	Xin Li 0001, Yang Xu 0017, Peng Li 0001, Padmini Gopalakrishnan, Lawrence T. Pileggi	A frequency relaxation approach for analog/RF system-level simulation.	DAC	2004	DBLP DOI BibTeX RDF	analog/RF circuits, system-level simulation
28	Haibo Wang 0005, Sarma B. K. Vrudhula	Behavioral synthesis of field programmable analog array circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Programmable circuits, analog synthesis
28	Mike W. T. Wong, K. Y. Ko, Yim-Shu Lee	Analog and Mixed-Signal IP Cores Testing.	DELTA	2002	DBLP DOI BibTeX RDF	mixed-signal design, analog circuit testing, SOCs
28	Jens Lienig, Goeran Jerke, Thorsten Adler	Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	wire width, wire planning, current-driven routing, Design methodology, electromigration, detailed routing, current density, analog circuit design
28	Suresh Seshadri, Jacob A. Abraham	Frequency Response Verification of Analog Circuits Using Global Optimization Techniques.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	modeling, verification, global optimization, analog circuits, formal techniques, parameter variation, frequency response
28	Farzan Aminian, Mehran Aminian	Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	electronic circuits, neural networks, fault diagnosis, wavelet transform, Fourier transform, analog circuits, nonlinear circuits
28	Eduardo J. Peralías, Adoración Rueda, José Luis Huertas	New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	mixed-signal IC test, testable ADC, BIST, design for test, pipelined analog to digital converters
28	Abdelhakim Khouas, Anne Derieux	Fault Simulation for Analog Circuits Under Parameter Variations.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	test optimisation, fault simulation, analog testing
28	Jun-Weir Lin, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	Fault diagnosis for linear analog circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	discrete signal flow graph, equivalent faults, fault diagnosis, fault diagnosis, signal flow graphs, analogue circuits, linear analog circuits
28	Paolo Migliavacca	Faster Time-to-Market, Lower Cost of Development and Test for Standard Analog IC.	IOLTW	2000	DBLP DOI BibTeX RDF	Bipolar array, standard analog IC, time-to-market, Voltage Reference
28	Mohamed Dessouky, Marie-Minerve Louërat	A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Analog layout, layout generation
28	Abdelhakim Khouas, Mohamed Dessouky, Anne Derieux	Optimized Statistical Analog Fault Simulation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Fault Simulation, Analog Testing, Statistical Simulation
28	Bertram Emil Shi	Real-Time Gabor-Type Filtering Using Analog Focal Plane Image Processors.	CVPR	1999	DBLP DOI BibTeX RDF	oriented filters, image fixation, analog processing circuits, mobile robots, scale-space, image sensors, steerable filters
28	Bruno Crespi, Alex Cozzi, Luigi Raffo, Silvio P. Sabatini	Analog computation for phase-based disparity estimation: continuous and discrete models.	Mach. Vis. Appl.	1998	DBLP DOI BibTeX RDF	Phase-based technique, VLSI, Differential equations, Disparity, Analog computation
28	Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb	Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults.	DATE	1998	DBLP DOI BibTeX RDF	analog and mixed-signal test design, IDD spectral measurements, test decision criteria, yield coverage, fault modeling, fault coverage, discrimination analysis, measurement noise
28	Prakash Gopalakrishnan, Vinita Vasudevan	A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	routing, layout, analog circuits
28	Pramodchandran N. Variyam, Abhijit Chatterjee	Test generation for comprehensive testing of linear analog circuits using transient response sampling.	ICCAD	1997	DBLP DOI BibTeX RDF	Implicit functional testing, Transient testing, Linear Analog Circuits
28	Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen	Automated test pattern generation for analog integrated circuits.	VTS	1997	DBLP DOI BibTeX RDF	automated test pattern generation, generated fault list, optimal test signals, statistical fluctuations, statistical test criterion, ATPG algorithm, analogue integrated circuits, analog integrated circuits
28	Eduardo J. Peralías, Adoración Rueda, José L. Huertas	A DFT Technique for Analog-to-Digital Converters with digital correction.	VTS	1997	DBLP DOI BibTeX RDF	Design for Testability of Data Converters, Analog and Mixed Signal Test
28	Karim Arabi, Bozena Kaminska	Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology.	VTS	1997	DBLP DOI BibTeX RDF	Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits
28	Walter M. Lindermeir	Design of robust test criteria in analog testing.	ICCAD	1996	DBLP DOI BibTeX RDF	measurement selection, sample generation, analog testing, measurement noise
28	Karim Arabi, Bozena Kaminska	Oscillation-test strategy for analog and mixed-signal integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs
28	Eric Felt, Alberto L. Sangiovanni-Vincentelli	Optimization of analog IC test structures.	VTS	1996	DBLP DOI BibTeX RDF	integrated circuit measurement, analog IC test structures, circuit parameters, statistical analysis, integrated circuit testing, accuracy, circuit optimisation, design of experiments, design of experiments, analogue integrated circuits, statistical techniques, network parameters, integrated circuit noise, measurement noise
28	A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri	A micropower analog hearing aid on low voltage CMOS digital process.	VLSI Design	1996	DBLP DOI BibTeX RDF	differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids
28	Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi	Low-cost DC built-in self-test of linear analog circuits using checksums.	VLSI Design	1996	DBLP DOI BibTeX RDF	DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes
28	Eugenia Penn, Leo N. Schelovanov	A new approach for modeling and optimization of analog systems.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	recurrent procedure, complex analog systems, diverse systems, computer-aided optimization design, system optimisation, modelling, modeling, CAD, optimisation, digital simulation, digital simulation
28	Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana	CODAC-a characterization system for digital and analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	CODAC, characterization system, electrical simulator, procedural interface, customized analysis functions, parallel processing, circuit analysis computing, Monte Carlo methods, circuit CAD, SPICE, SPICE, analog circuits, digital circuits, CAD tool, digital integrated circuits, analogue integrated circuits, circuit analysis, Monte Carlo analysis
27	Ender Yilmaz, Günhan Dündar	Analog Layout Generator for CMOS Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
27	Sha Yao, Mikael Skoglund	Hybrid Digital-Analog Relaying for Cooperative Transmission Over Slow Fading Channels.	IEEE Trans. Inf. Theory	2009	DBLP DOI BibTeX RDF
27	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
27	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann	The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
27	Angelo Ciccazzo, Piero Conca, Giuseppe Nicosia, Giovanni Stracquadanio	An Advanced Clonal Selection Algorithm with Ad-Hoc Network-Based Hypermutation Operators for Synthesis of Topology and Sizing of Analog Electrical Circuits.	ICARIS	2008	DBLP DOI BibTeX RDF
27	Sheng-Yu Peng, Yu Tsao 0001, Paul E. Hasler, David V. Anderson	A programmable analog radial-basis-function based classifier.	ICASSP	2008	DBLP DOI BibTeX RDF
27	Joachim Becker, Fabian Henrici, Stanis Trendelenburg, Yiannos Manoli	A rapid prototyping environment for high-speed reconfigurable analog signal processing.	IPDPS	2008	DBLP DOI BibTeX RDF
27	Luiz Carlos Gouveia, Thomas Jacob Koickal, Alister Hamilton	An asynchronous spike event coding scheme for programmable analog arrays.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Sri Chandra	Driving Analog Mixed Signal Verification through Verilog-AMS.	VLSI Design	2008	DBLP DOI BibTeX RDF
27	Joaquin Sitte, Liang Zhang, Ulrich Rückert 0001	Characterization of Analog Local Cluster Neural Network Hardware for Control.	IEEE Trans. Neural Networks	2007	DBLP DOI BibTeX RDF
27	Lauri Koskinen, Joona Marku, Ari Paasio, Kari Halonen	Architecture for Analog Variable Block-Size Motion Estimation.	ICIP (2)	2007	DBLP DOI BibTeX RDF
27	Sheng-Yu Peng, Paul E. Hasler, David V. Anderson	An analog programmable multi-dimensional radial basis function based classifier.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
27	I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson	Placement for large-scale floating-gate field-programable analog arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
27	Mikael Skoglund, Nam Phamdo, Fady Alajaji	Hybrid Digital-Analog Source-Channel Coding for Bandwidth Compression/Expansion.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
27	Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa	Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
27	Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa	Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
27	Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani	Adaptive Porting of Analog IPs with Reusable Conservative Properties.	ISVLSI	2006	DBLP DOI BibTeX RDF
27	Fujita Tomohiro, Iiduka Osamu	Analog circuit sizing with dynamic search window.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Shantanu Chakrabartty	CMOS analog iterative decoders using margin propagation circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Josep Soler Garrido, Robert J. Piechocki, Koushik Maharatna, Darren P. McNamara	MIMO detection in analog VLSI.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Varun Aggarwal, Meng Mao, Una-May O'Reilly	A Self-Tuning Analog Proportional-Integral-Derivative (PID) Controller.	AHS	2006	DBLP DOI BibTeX RDF
27	Kaiping Zeng, Sorin A. Huss	Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques.	ISQED	2006	DBLP DOI BibTeX RDF
27	Rodrigo Cardim, Marcelo C. M. Teixeira, Edvaldo Assunção, Nobuo Oki, Aparecido Augusto de Carvalho, Márcio R. Covacic	Hardware Implementation of an Analog Neural Nonderivative Optimizer.	ICONIP (3)	2006	DBLP DOI BibTeX RDF
27	Michael Unser	Cardinal exponential splines: part II - think analog, act digital.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
27	Jianyun Hu, Hao Min	A Low Power and High Performance Analog Front End for Passive RFID Transponder.	AutoID	2005	DBLP DOI BibTeX RDF
27	Hongrak Son, Hyunjung Kim, Hyongsuk Kim, Kil To Chong	Feasibility of the Circularly Connected Analog CNN Cell Array-Based Viterbi Decoder.	PaCT	2005	DBLP DOI BibTeX RDF
27	Chris Winstead	Analog Soft Decoding for Multi-Level Memories.	ISMVL	2005	DBLP DOI BibTeX RDF
27	Dayu Yang, Foster F. Dai, Charles E. Stroud	Built-in self-test for automatic analog frequency response measurement.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
27	Ravi Chawla, Christopher M. Twigg, Paul E. Hasler	An analog modulator/demodulator using a programmable arbitrary waveform generator.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
27	Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli	A Methodology for System-Level Analog Design Space Exploration.	DATE	2004	DBLP DOI BibTeX RDF
27	Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski	Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.	SBCCI	2004	DBLP DOI BibTeX RDF	system-on-chip, BIST, power aware, mixed-signal test
27	Chin-Long Wey, Mohammad Athar Khalil, Jim Liu, Gregory Wierzba	Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	IC reliability
27	José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Ricardo Tanscheit, Marley M. B. R. Vellasco, Marco Aurélio Cavalcanti Pacheco	Towards Evolvable Analog Artificial Neural Networks Controllers.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
27	Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, Martin Trefzer	Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
27	Junwei Hou, Abhijit Chatterjee	Concurrent transient fault simulation for analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
27	Wallace B. Leigh	Simplifying Analog CMOS Design for Undergraduates.	MSE	2003	DBLP DOI BibTeX RDF
27	Alain Vachoux, Christoph Grimm 0001, Karsten Einwich	Analog and mixed signal modelling with SystemC-AMS.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
27	Yuan-Pei Lin, See-May Phoong	Analog representation and digital implementation of OFDM systems.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
27	Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu	A digital background calibration technique for pipelined analog-to-digital converters.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
27	Marco S. Dragic, Martin Margala	Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits.	DFT	2003	DBLP DOI BibTeX RDF