Search results for "superscalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Norman P. Jouppi, David W. Wall	Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines.	ASPLOS	1989	DBLP DOI BibTeX RDF
23	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
23	Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu	Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	superscalar pipeline, non-blocking cache, synthesis flow, bit-sliced placement, crafted cell, performance evaluation, physical design, out-of-order execution, general-purpose processor
23	Michael Ferdman, Babak Falsafi	Last-Touch Correlated Data Streaming.	ISPASS	2007	DBLP DOI BibTeX RDF	predictor lookahead, last-touch correlated data streaming, address-correlating predictor, cache block address identification, correlation data storage, program active memory footprint, prediction lookahead, off-chip correlation data lookup, scalable on-chip table, low-latency lookup, on-chip storage, last-touch predictor, prefetch, superscalar processor, cycle-accurate simulation
23	ElMoustapha Ould-Ahmed-Vall, James Woodlee, Charles Yount, Kshitij A. Doshi, Seth Abraham	Using Model Trees for Computer Architecture Performance Analysis of Software Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	superscalar machine, computer architecture performance analysis, tuning software, statistical regression modeling, M5' algorithm, SPEC CPU2006 suite, performance model tree, prefetching, software application
23	Matt T. Yourst	PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator.	ISPASS	2007	DBLP DOI BibTeX RDF	client-server networked benchmark, PTLsim, cycle accurate full system, x86-64 microarchitectural simulator, superscalar x86-64 processor core, full-speed native execution, microarchitectural simulators, x86 ISA, microoperation level, multiprocessor capable simulation, Xen hypervisor, AMD Athlon 64 machine, virtual machine
23	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra	Modeling out-of-order processors for WCET analysis.	Real Time Syst.	2006	DBLP DOI BibTeX RDF	Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache
23	Oguz Ergin, Deniz Balkan, Dmitry Ponomarev 0001, Kanad Ghose	Early Register Deallocation Mechanisms Using Checkpointed Register Files.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	register file optimization, Superscalar processors, precise interrupts
23	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
23	Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg	Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing.	CASES	2005	DBLP DOI BibTeX RDF	worst-case execution time, schedulability analysis, superscalar processor, simultaneous multithreading, hard real-time, resource partitioning
23	Muhammad Shaaban, Edward Mulrane	Improving trace cache hit rates using the sliding window fill mechanism and fill select table.	Memory System Performance	2004	DBLP DOI BibTeX RDF	branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache
23	Fadi Busaba, Timothy J. Slegel, Steven R. Carlough, Christopher A. Krygowski, John G. Rell	The design of the fixed point unit for the z990 microprocessor.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	superscalar FXU, microprocessor
23	Isak Jonsson, Bo Kågström	RECSY - A High Performance Library for Sylvester-Type Matrix Equations.	Euro-Par	2003	DBLP DOI BibTeX RDF	Sylvester-type matrix equations, RECSY, recursion, superscalar, LAPACK, level 3 BLAS, GEMM-based, SLICOT, automatic blocking
23	Isak Jonsson, Bo Kågström	Recursive blocked algorithms for solving triangular systems - Part I: one-sided and coupled Sylvester-type matrix equations.	ACM Trans. Math. Softw.	2002	DBLP DOI BibTeX RDF	SMP parallelization, generalized coupled Sylvester, standard Sylvester and Lyapunov, recursion, superscalar, LAPACK, level-3 BLAS, GEMM-based, SLICOT, Matrix equations, automatic blocking
23	Sébastien Nussbaum, James E. Smith 0001	Statistical Simulation of Symmetric Multiprocessor Systems.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF	SimpleMP, Simulation, Performance, Architecture, multiprocessor, Statistical, Memory Hierarchy, systems, SMP, superscalar, Fast, shared bus, out-of-order
23	Kazunori Ogata, Hideaki Komatsu, Toshio Nakatani	Bytecode fetch optimization for a Java interpreter.	ASPLOS	2002	DBLP DOI BibTeX RDF	pipelined interpreter, stack caching, Java, performance, superscalar processor, PowerPC, bytecode interpreter
23	José González 0002, Antonio González 0001	Control-Flow Speculation through Value Prediction.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	path-based selector, Branch prediction, superscalar processors, value prediction, hybrid predictor
23	Ramon Canal, Antonio González 0001	Reducing the complexity of the issue logic.	ICS	2001	DBLP DOI BibTeX RDF	complexity-effective design, instruction issue logic, wide-issue superscalar, out-of-order issue
23	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck	Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	geometry pipeline, paired-single instructions, 3D graphics, superscalar processors, SIMD instructions
23	Sang Jeong Lee, Yuan Wang, Pen-Chung Yew	Decoupled Value Prediction on Trace Processors.	HPCA	2000	DBLP DOI BibTeX RDF	Wide-issue superscalar processors, Trace processors, Speculative execution, Value prediction
23	Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung	Design of Instruction Stream Buffer with Trace Support for X86 Processors.	ICCD	2000	DBLP DOI BibTeX RDF	instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache
23	Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari	Inductive Noise Reduction at the Architectural Level.	VLSI Design	2000	DBLP DOI BibTeX RDF	SIMD, superscalar, Clock-gating, Ground Bounce
23	Eric Rotenberg, Steve Bennett, James E. Smith 0001	A Trace Cache Microarchitecture and Evaluation.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching
23	Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind	Execution-Based Scheduling for VLIW Architectures.	Euro-Par	1999	DBLP DOI BibTeX RDF	INSTRUCTION-LEVEL PARALLELISM, SUPERSCALAR, BINARY TRANSLATION, DYNAMIC COMPILATION
23	Bohuslav Rychlik, John Faistl, Bryon Krug, John Paul Shen	Efficacy and Performance Impact of Value Prediction.	IEEE PACT	1998	DBLP DOI BibTeX RDF	usefulness tracking, instruction level parallelism, speculative execution, superscalar processor, value prediction, hybrid predictor
23	Soo-Mook Moon, Kemal Ebcioglu	Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar
23	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
23	A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble	Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces.	EUROMICRO	1997	DBLP DOI BibTeX RDF	memory hierarchy simulation, desktop PC, commodity chips, PC microcomputers, synthetic bus traces, dynamically scheduled superscalar microprocessor, performance evaluation, memory architecture
23	Eric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt	The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference.	ISCA	1997	DBLP DOI BibTeX RDF	two-level branch prediction, branch prediction, speculative execution, superscalar
23	Mayan Moudgill, Stamatis Vassiliadis	Precise Interrupts.	IEEE Micro	1996	DBLP DOI BibTeX RDF	interrupt handlers, out-of-order issue processors, instruction level parallel processors, pipelining, exceptions, superscalar processors, traps, precise interrupts
23	Wolfgang K. Giloi, Ulrich Brüning 0001, Wolfgang Schröder-Preikschat	MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance.	PDP	1996	DBLP DOI BibTeX RDF	maximized sustained performance, compiler problem, innovative architectural solutions, overlapping communication, MANNA computer, benchmark performance, performance evaluation, parallel computers, operating system, parallel machines, distributed memory systems, parallelizing compilers, operating systems (computers), programmability, virtual storage, parallelising compilers, latency hiding, distributed memory parallel computer, distributed memory architecture, virtual shared memory, global address space, superscalar microprocessors
23	Eric Rotenberg, Steve Bennett, James E. Smith 0001	Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.	MICRO	1996	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, instruction cache, trace cache, instruction fetching
23	Jian Wang, Guang R. Gao	Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops.	CC	1996	DBLP DOI BibTeX RDF	Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism
23	Raymond Lo, Sun Chan, James C. Dehnert, Ross A. Towle	Aggregate Operation Movement: A Min-Cut Approach to Global Code Motion.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF	global code motion, software pipelining, network flow, superscalar, minimum cut, global scheduling
23	Marius Evers, Po-Yung Chang, Yale N. Patt	Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches.	ISCA	1996	DBLP DOI BibTeX RDF	branch prediction, speculative execution, superscalar, context switch
23	Thomas W. Lynch, Ashraf Ahmed, Michael J. Schulte, Thomas K. Callaway, Robert Tisdale	The K5 transcendental functions.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	K5 transcendental functions, AMD x86 compatible superscalar microprocessor, multi-level development cycle, design schedule, table-driven reductions, multiprecision arithmetic operations, encoding, polynomials, floating point arithmetic, microprocessor chips, approximation theory, polynomial approximations
23	Aaron Goldberg, John A. Trotter	Interrupt-based hardware support for profiling memory system performance.	ICCD	1995	DBLP DOI BibTeX RDF	profiling memory system performance, superscalar technologies, Mprof prototype, data stall cycles, first level cache misses, Sun Sparc 10/41, performance evaluation, storage management, memory architecture, hardware support, sampling techniques, memory system performance
23	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
23	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
23	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution
23	Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt	Branch classification: a new mechanism for improving branch predictor performance.	MICRO	1994	DBLP DOI BibTeX RDF	branch classification, speculative execution, superscalar, processor performance, branch predictor
23	Manoj Franklin, Mark Smotherman	A fill-unit approach to multiple instruction issue.	MICRO	1994	DBLP DOI BibTeX RDF	multiple operation issue, instruction-level parallelism, VLIW, superscalar
23	M. Anton Ertl, Andreas Krall	Delayed Exceptions - Speculative Execution of Trapping Instructions.	CC	1994	DBLP DOI BibTeX RDF	instruction-level parallelism, software pipelining, exception, speculative execution, superscalar
17	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
17	Eduard Ayguadé, Rosa M. Badia, Francisco D. Igual, Jesús Labarta, Rafael Mayo 0002, Enrique S. Quintana-Ortí	An Extension of the StarSs Programming Model for Platforms with Multiple GPUs.	Euro-Par	2009	DBLP DOI BibTeX RDF	heterogeneous systems, programming models, graphics processors, Task-level parallelism
17	Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design
17	Jack Whitham, Neil C. Audsley	Forming Virtual Traces for WCET Analysis and Reduction.	RTCSA	2008	DBLP DOI BibTeX RDF
17	Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai	Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.	ICCD	2008	DBLP DOI BibTeX RDF
17	Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song	A simple latency tolerant processor.	ICCD	2008	DBLP DOI BibTeX RDF
17	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
17	Ruchira Sasanka, Man-Lap Li, Sarita V. Adve, Yen-Kuang Chen, Eric Debes	ALP: Efficient support for all levels of parallelism for complex media applications.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	media applications, multimedia, Parallelism, SIMD, vector, TLP, DLP, data-level parallelism
17	Yongfeng Pan, Xiaoya Fan, Liqiang He, Deli Wang	A Bypass Mechanism to Enhance Branch Predictor for SMT Processors.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
17	Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat	By-passing the out-of-order execution pipeline to increase energy-efficiency.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	instruction wake-up, energy-efficiency, instruction scheduling, out-of-order execution
17	Neal A. Harman	Algebraic Models of Simultaneous Multithreaded and Multi-core Processors.	CALCO	2007	DBLP DOI BibTeX RDF	many-sorted algebra, verification, microprocessors, correctness, threaded
17	Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler	Late-binding: enabling unordered load-store queues.	ISCA	2007	DBLP DOI BibTeX RDF	network flow control, memory disambiguation, late binding
17	Luis Ceze, Karin Strauss, James Tuck 0001, Josep Torrellas, Jose Renau	CAVA: Using checkpoint-assisted value prediction to hide L2 misses.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	checkpointed processor architectures, multiprocessor, memory hierarchies, Value prediction
17	Olivier Rochecouste, Gilles Pokam, André Seznec	A case for a complexity-effective, width-partitioned microarchitecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Power analysis
17	Chengmo Yang, Alex Orailoglu	Power-efficient instruction delivery through trace reuse.	PACT	2006	DBLP DOI BibTeX RDF	adaptive processor, low-power design, instruction delivery
17	Won Woo Ro, Jean-Luc Gaudiot	Design and Effectiveness of Small-Sized Decoupled Dispatch Queues.	Euro-Par	2006	DBLP DOI BibTeX RDF
17	Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan	A scalable low power issue queue for large instruction window processors.	ICS	2006	DBLP DOI BibTeX RDF	complexity-effective architecture, wakeup logic, low-power architecture, issue logic
17	In-Pyo Hong, Yong-Joo Lee, Yong-Surk Lee	Next Generation Embedded Processor Architecture for Personal Information Devices.	EUC	2006	DBLP DOI BibTeX RDF
17	Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein, Mihai Budiu	Tartan: evaluating spatial computation for whole program execution.	ASPLOS	2006	DBLP DOI BibTeX RDF	low power, asynchronous circuits, reconfigurable hardware, defect tolerance, spatial computation, dataflow machine
17	James Laudon	Performance/Watt: the new server focus.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
17	Pramod Ramarao, Akhilesh Tyagi	An Integrated Partitioning and Scheduling Based Branch Decoupling.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
17	Qing Zhao, David J. Lilja	Static Classification of Value Predictability Using Compiler Hints.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
17	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
17	Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya	Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures.	ASP-DAC	2004	DBLP DOI BibTeX RDF
17	Rama Sangireddy, Arun K. Somani	Exploiting Quiescent States in Register Lifetime.	ICCD	2004	DBLP DOI BibTeX RDF
17	Leonid Oliker, Andrew Canning, Jonathan Carter, John Shalf, Stéphane Ethier	Scientific Computations on Modern Parallel Vector Systems.	SC	2004	DBLP DOI BibTeX RDF
17	Leonid Oliker, Rupak Biswas, Julian Borrill, Andrew Canning, Jonathan Carter, M. Jahed Djomehri, Hongzhang Shan, David Skinner	A Performance Evaluation of the Cray X1 for Scientific Applications.	VECPAR	2004	DBLP DOI BibTeX RDF
17	Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam	A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy.	ISCA	2004	DBLP DOI BibTeX RDF	Complexity-effective design, Temporal Redundancy, Instruction Reuse
17	Rubén González 0001, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero	A Content Aware Integer Register File Organization.	ISCA	2004	DBLP DOI BibTeX RDF
17	Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar	Heat-and-run: leveraging SMT and CMP to manage power density through the operating system.	ASPLOS	2004	DBLP DOI BibTeX RDF	CMP, migration, SMT, heat, power density
17	Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills	Modeling technology impact on cluster microprocessor performance.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
17	Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter M. Kogge	Energy-efficient issue queue design.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
17	Jian Huang, David J. Lilja	Balancing Reuse Opportunities and Performance Gains with Subblock Value Reuse.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Block reuse, subblock reuse, compiler flow analysis, value reuse, value locality
17	Theo Ungerer, Borut Robic, Jurij Silc	A survey of processors with explicit multithreading.	ACM Comput. Surv.	2003	DBLP DOI BibTeX RDF	interleaved multithreading, simultaneous multithreading, Blocked multithreading
17	Shuvendu K. Lahiri, Randal E. Bryant	Deductive Verification of Advanced Out-of-Order Microprocessors.	CAV	2003	DBLP DOI BibTeX RDF
17	Joydeep Ray, James C. Hoe	High-level modeling and FPGA prototyping of microprocessors.	FPGA	2003	DBLP DOI BibTeX RDF	operation-centric, FPGA, evaluation, prototyping, microprocessor, microarchitecture
17	Ho-Seop Kim, James E. Smith 0001	Dynamic Binary Translation for Accumulator-Oriented Architectures.	CGO	2003	DBLP DOI BibTeX RDF
17	Pramod Ramarao, Akhilesh Tyagi	An Adiabatic Framework for a Low Energy µ-Architecture & Compiler.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF
17	Paul Racunas, Yale N. Patt	Partitioned first-level cache design for clustered microarchitectures.	ICS	2003	DBLP DOI BibTeX RDF	partitioned cache, clustered microarchitecture
17	Venkata Syam P. Rapaka, Diana Marculescu	A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores.	ISLPED	2003	DBLP DOI BibTeX RDF	issue window design, mixed-clock circuits, GALS
17	Rama Sangireddy, Arun K. Somani	Application-Specific Computing with Adaptive Register File Architectures.	ASAP	2003	DBLP DOI BibTeX RDF	Computing capacity, compute-intensive Function, Memory bandwidth, Register File
17	Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir	Ditto Processor.	DSN	2002	DBLP DOI BibTeX RDF
17	Girish Venkataramani, Suraj Sudhir, Mihai Budiu, Seth Copen Goldstein	Factors Influencing the Performance of a CPU-RFU Hybrid Architecture.	FPL	2002	DBLP DOI BibTeX RDF
17	Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff	Performance Scalability of Multimedia Instruction Set Extensions.	Euro-Par	2002	DBLP DOI BibTeX RDF
17	Ho-Seop Kim, James E. Smith 0001	An Instruction Set and Microarchitecture for Instruction Level Distributed Processing.	ISCA	2002	DBLP DOI BibTeX RDF
17	Allan Hartstein, Thomas R. Puzak	The Optimum Pipeline Depth for a Microprocessor.	ISCA	2002	DBLP DOI BibTeX RDF
17	Joan-Manuel Parcerisa, Antonio González 0001	Improving Latency Tolerance of Multithreading through Decoupling.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Access/execute decoupling, instruction-level parallelism, simultaneous multithreading, latency hiding, hardware complexity
17	Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler	A design space evaluation of grid processor architectures.	MICRO	2001	DBLP DOI BibTeX RDF
17	Zhen Fang 0002, Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee	Reevaluating Online Superpage Promotion with Hardware Support.	HPCA	2001	DBLP DOI BibTeX RDF
17	Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana	The MOLEN rho-mu-Coded Processor.	FPL	2001	DBLP DOI BibTeX RDF
17	Mark N. Yankelevsky, Constantine D. Polychronopoulos	alpha-coral: a multigrain, multithreaded processor architecture.	ICS	2001	DBLP DOI BibTeX RDF	processor archietecture, multithreaded, parallelizing compiler
17	Shu-Lin Hwang, Feipei Lai	Two Cache Lines Prediction for a Wide-Issue Micro-architecture.	ACSAC	2001	DBLP DOI BibTeX RDF
17	Daniele Folegnani, Antonio González 0001	Energy-effective issue logic.	ISCA	2001	DBLP DOI BibTeX RDF	adaptive hardware, low power, energy consumption, issue logic
17	Jan Hoogerbrugge	Dynamic Branch Prediction for a VLIW Processor.	IEEE PACT	2000	DBLP DOI BibTeX RDF
17	Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna	Performance of On-Chip Multiprocessors for Vision Tasks.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
17	James E. Smith 0001	Instruction Level Distributed Processing: Adapting to Future Technology.	ISHPC	2000	DBLP DOI BibTeX RDF
17	Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee	CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit.	ISCA	2000	DBLP DOI BibTeX RDF